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1da177e4 LT |
1 | /* |
2 | * include/asm-v850/v850e_uarta.h -- original V850E on-chip UART | |
3 | * | |
4 | * Copyright (C) 2001,02,03 NEC Electronics Corporation | |
5 | * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General | |
8 | * Public License. See the file COPYING in the main directory of this | |
9 | * archive for more details. | |
10 | * | |
11 | * Written by Miles Bader <miles@gnu.org> | |
12 | */ | |
13 | ||
14 | /* This is the original V850E UART implementation is called just `UART' in | |
15 | the docs, but we name this header file <asm/v850e_uarta.h> because the | |
16 | name <asm/v850e_uart.h> is used for the common driver that handles both | |
17 | `UART' and `UARTB' implementations. */ | |
18 | ||
19 | #ifndef __V850_V850E_UARTA_H__ | |
20 | #define __V850_V850E_UARTA_H__ | |
21 | ||
22 | \f | |
23 | /* Raw hardware interface. */ | |
24 | ||
25 | /* The base address of the UART control registers for channel N. | |
26 | The default is the address used on the V850E/MA1. */ | |
27 | #ifndef V850E_UART_BASE_ADDR | |
28 | #define V850E_UART_BASE_ADDR(n) (0xFFFFFA00 + 0x10 * (n)) | |
29 | #endif | |
30 | ||
31 | /* Addresses of specific UART control registers for channel N. | |
32 | The defaults are the addresses used on the V850E/MA1; if a platform | |
33 | wants to redefine any of these, it must redefine them all. */ | |
34 | #ifndef V850E_UART_ASIM_ADDR | |
35 | #define V850E_UART_ASIM_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x0) | |
36 | #define V850E_UART_RXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x2) | |
37 | #define V850E_UART_ASIS_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x3) | |
38 | #define V850E_UART_TXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x4) | |
39 | #define V850E_UART_ASIF_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x5) | |
40 | #define V850E_UART_CKSR_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x6) | |
41 | #define V850E_UART_BRGC_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x7) | |
42 | #endif | |
43 | ||
44 | /* UART config registers. */ | |
45 | #define V850E_UART_ASIM(n) (*(volatile u8 *)V850E_UART_ASIM_ADDR(n)) | |
46 | /* Control bits for config registers. */ | |
47 | #define V850E_UART_ASIM_CAE 0x80 /* clock enable */ | |
48 | #define V850E_UART_ASIM_TXE 0x40 /* transmit enable */ | |
49 | #define V850E_UART_ASIM_RXE 0x20 /* receive enable */ | |
50 | #define V850E_UART_ASIM_PS_MASK 0x18 /* mask covering parity-select bits */ | |
51 | #define V850E_UART_ASIM_PS_NONE 0x00 /* no parity */ | |
52 | #define V850E_UART_ASIM_PS_ZERO 0x08 /* zero parity */ | |
53 | #define V850E_UART_ASIM_PS_ODD 0x10 /* odd parity */ | |
54 | #define V850E_UART_ASIM_PS_EVEN 0x18 /* even parity */ | |
55 | #define V850E_UART_ASIM_CL_8 0x04 /* char len is 8 bits (otherwise, 7) */ | |
56 | #define V850E_UART_ASIM_SL_2 0x02 /* 2 stop bits (otherwise, 1) */ | |
57 | #define V850E_UART_ASIM_ISRM 0x01 /* generate INTSR interrupt on errors | |
58 | (otherwise, generate INTSER) */ | |
59 | ||
60 | /* UART serial interface status registers. */ | |
61 | #define V850E_UART_ASIS(n) (*(volatile u8 *)V850E_UART_ASIS_ADDR(n)) | |
62 | /* Control bits for status registers. */ | |
63 | #define V850E_UART_ASIS_PE 0x04 /* parity error */ | |
64 | #define V850E_UART_ASIS_FE 0x02 /* framing error */ | |
65 | #define V850E_UART_ASIS_OVE 0x01 /* overrun error */ | |
66 | ||
67 | /* UART serial interface transmission status registers. */ | |
68 | #define V850E_UART_ASIF(n) (*(volatile u8 *)V850E_UART_ASIF_ADDR(n)) | |
69 | #define V850E_UART_ASIF_TXBF 0x02 /* transmit buffer flag (data in TXB) */ | |
70 | #define V850E_UART_ASIF_TXSF 0x01 /* transmit shift flag (sending data) */ | |
71 | ||
72 | /* UART receive buffer register. */ | |
73 | #define V850E_UART_RXB(n) (*(volatile u8 *)V850E_UART_RXB_ADDR(n)) | |
74 | ||
75 | /* UART transmit buffer register. */ | |
76 | #define V850E_UART_TXB(n) (*(volatile u8 *)V850E_UART_TXB_ADDR(n)) | |
77 | ||
78 | /* UART baud-rate generator control registers. */ | |
79 | #define V850E_UART_CKSR(n) (*(volatile u8 *)V850E_UART_CKSR_ADDR(n)) | |
80 | #define V850E_UART_CKSR_MAX 11 | |
81 | #define V850E_UART_BRGC(n) (*(volatile u8 *)V850E_UART_BRGC_ADDR(n)) | |
82 | #define V850E_UART_BRGC_MIN 8 | |
83 | ||
84 | ||
85 | #ifndef V850E_UART_CKSR_MAX_FREQ | |
86 | #define V850E_UART_CKSR_MAX_FREQ (25*1000*1000) | |
87 | #endif | |
88 | ||
89 | /* Calculate the minimum value for CKSR on this processor. */ | |
90 | static inline unsigned v850e_uart_cksr_min (void) | |
91 | { | |
92 | int min = 0; | |
93 | unsigned freq = V850E_UART_BASE_FREQ; | |
94 | while (freq > V850E_UART_CKSR_MAX_FREQ) { | |
95 | freq >>= 1; | |
96 | min++; | |
97 | } | |
98 | return min; | |
99 | } | |
100 | ||
101 | \f | |
102 | /* Slightly abstract interface used by driver. */ | |
103 | ||
104 | ||
105 | /* Interrupts used by the UART. */ | |
106 | ||
107 | /* Received when the most recently transmitted character has been sent. */ | |
108 | #define V850E_UART_TX_IRQ(chan) IRQ_INTST (chan) | |
109 | /* Received when a new character has been received. */ | |
110 | #define V850E_UART_RX_IRQ(chan) IRQ_INTSR (chan) | |
111 | ||
112 | ||
113 | /* UART clock generator interface. */ | |
114 | ||
115 | /* This type encapsulates a particular uart frequency. */ | |
116 | typedef struct { | |
117 | unsigned clk_divlog2; | |
118 | unsigned brgen_count; | |
119 | } v850e_uart_speed_t; | |
120 | ||
121 | /* Calculate a uart speed from BAUD for this uart. */ | |
122 | static inline v850e_uart_speed_t v850e_uart_calc_speed (unsigned baud) | |
123 | { | |
124 | v850e_uart_speed_t speed; | |
125 | ||
126 | /* Calculate the log2 clock divider and baud-rate counter values | |
127 | (note that the UART divides the resulting clock by 2, so | |
128 | multiply BAUD by 2 here to compensate). */ | |
129 | calc_counter_params (V850E_UART_BASE_FREQ, baud * 2, | |
130 | v850e_uart_cksr_min(), | |
131 | V850E_UART_CKSR_MAX, 8/*bits*/, | |
132 | &speed.clk_divlog2, &speed.brgen_count); | |
133 | ||
134 | return speed; | |
135 | } | |
136 | ||
137 | /* Return the current speed of uart channel CHAN. */ | |
138 | static inline v850e_uart_speed_t v850e_uart_speed (unsigned chan) | |
139 | { | |
140 | v850e_uart_speed_t speed; | |
141 | speed.clk_divlog2 = V850E_UART_CKSR (chan); | |
142 | speed.brgen_count = V850E_UART_BRGC (chan); | |
143 | return speed; | |
144 | } | |
145 | ||
146 | /* Set the current speed of uart channel CHAN. */ | |
147 | static inline void v850e_uart_set_speed(unsigned chan,v850e_uart_speed_t speed) | |
148 | { | |
149 | V850E_UART_CKSR (chan) = speed.clk_divlog2; | |
150 | V850E_UART_BRGC (chan) = speed.brgen_count; | |
151 | } | |
152 | ||
153 | static inline int | |
154 | v850e_uart_speed_eq (v850e_uart_speed_t speed1, v850e_uart_speed_t speed2) | |
155 | { | |
156 | return speed1.clk_divlog2 == speed2.clk_divlog2 | |
157 | && speed1.brgen_count == speed2.brgen_count; | |
158 | } | |
159 | ||
160 | /* Minimum baud rate possible. */ | |
161 | #define v850e_uart_min_baud() \ | |
162 | ((V850E_UART_BASE_FREQ >> V850E_UART_CKSR_MAX) / (2 * 255) + 1) | |
163 | ||
164 | /* Maximum baud rate possible. The error is quite high at max, though. */ | |
165 | #define v850e_uart_max_baud() \ | |
166 | ((V850E_UART_BASE_FREQ >> v850e_uart_cksr_min()) / (2 *V850E_UART_BRGC_MIN)) | |
167 | ||
168 | /* The `maximum' clock rate the uart can used, which is wanted (though not | |
169 | really used in any useful way) by the serial framework. */ | |
170 | #define v850e_uart_max_clock() \ | |
171 | ((V850E_UART_BASE_FREQ >> v850e_uart_cksr_min()) / 2) | |
172 | ||
173 | ||
174 | /* UART configuration interface. */ | |
175 | ||
176 | /* Type of the uart config register; must be a scalar. */ | |
177 | typedef u16 v850e_uart_config_t; | |
178 | ||
179 | /* The uart hardware config register for channel CHAN. */ | |
180 | #define V850E_UART_CONFIG(chan) V850E_UART_ASIM (chan) | |
181 | ||
182 | /* This config bit set if the uart is enabled. */ | |
183 | #define V850E_UART_CONFIG_ENABLED V850E_UART_ASIM_CAE | |
184 | /* If the uart _isn't_ enabled, store this value to it to do so. */ | |
185 | #define V850E_UART_CONFIG_INIT V850E_UART_ASIM_CAE | |
186 | /* Store this config value to disable the uart channel completely. */ | |
187 | #define V850E_UART_CONFIG_FINI 0 | |
188 | ||
189 | /* Setting/clearing these bits enable/disable TX/RX, respectively (but | |
190 | otherwise generally leave things running). */ | |
191 | #define V850E_UART_CONFIG_RX_ENABLE V850E_UART_ASIM_RXE | |
192 | #define V850E_UART_CONFIG_TX_ENABLE V850E_UART_ASIM_TXE | |
193 | ||
194 | /* These masks define which config bits affect TX/RX modes, respectively. */ | |
195 | #define V850E_UART_CONFIG_RX_BITS \ | |
196 | (V850E_UART_ASIM_PS_MASK | V850E_UART_ASIM_CL_8 | V850E_UART_ASIM_ISRM) | |
197 | #define V850E_UART_CONFIG_TX_BITS \ | |
198 | (V850E_UART_ASIM_PS_MASK | V850E_UART_ASIM_CL_8 | V850E_UART_ASIM_SL_2) | |
199 | ||
200 | static inline v850e_uart_config_t v850e_uart_calc_config (unsigned cflags) | |
201 | { | |
202 | v850e_uart_config_t config = 0; | |
203 | ||
204 | /* Figure out new configuration of control register. */ | |
205 | if (cflags & CSTOPB) | |
206 | /* Number of stop bits, 1 or 2. */ | |
207 | config |= V850E_UART_ASIM_SL_2; | |
208 | if ((cflags & CSIZE) == CS8) | |
209 | /* Number of data bits, 7 or 8. */ | |
210 | config |= V850E_UART_ASIM_CL_8; | |
211 | if (! (cflags & PARENB)) | |
212 | /* No parity check/generation. */ | |
213 | config |= V850E_UART_ASIM_PS_NONE; | |
214 | else if (cflags & PARODD) | |
215 | /* Odd parity check/generation. */ | |
216 | config |= V850E_UART_ASIM_PS_ODD; | |
217 | else | |
218 | /* Even parity check/generation. */ | |
219 | config |= V850E_UART_ASIM_PS_EVEN; | |
220 | if (cflags & CREAD) | |
221 | /* Reading enabled. */ | |
222 | config |= V850E_UART_ASIM_RXE; | |
223 | ||
224 | config |= V850E_UART_ASIM_CAE; | |
225 | config |= V850E_UART_ASIM_TXE; /* Writing is always enabled. */ | |
226 | config |= V850E_UART_ASIM_ISRM; /* Errors generate a read-irq. */ | |
227 | ||
228 | return config; | |
229 | } | |
230 | ||
231 | /* This should delay as long as necessary for a recently written config | |
232 | setting to settle, before we turn the uart back on. */ | |
233 | static inline void | |
234 | v850e_uart_config_delay (v850e_uart_config_t config, v850e_uart_speed_t speed) | |
235 | { | |
236 | /* The UART may not be reset properly unless we wait at least 2 | |
237 | `basic-clocks' until turning on the TXE/RXE bits again. | |
238 | A `basic clock' is the clock used by the baud-rate generator, | |
239 | i.e., the cpu clock divided by the 2^new_clk_divlog2. | |
240 | The loop takes 2 insns, so loop CYCLES / 2 times. */ | |
241 | register unsigned count = 1 << speed.clk_divlog2; | |
242 | while (--count != 0) | |
243 | /* nothing */; | |
244 | } | |
245 | ||
246 | ||
247 | /* RX/TX interface. */ | |
248 | ||
249 | /* Return true if all characters awaiting transmission on uart channel N | |
250 | have been transmitted. */ | |
251 | #define v850e_uart_xmit_done(n) \ | |
252 | (! (V850E_UART_ASIF(n) & V850E_UART_ASIF_TXBF)) | |
253 | /* Wait for this to be true. */ | |
254 | #define v850e_uart_wait_for_xmit_done(n) \ | |
255 | do { } while (! v850e_uart_xmit_done (n)) | |
256 | ||
257 | /* Return true if uart channel N is ready to transmit a character. */ | |
258 | #define v850e_uart_xmit_ok(n) \ | |
259 | (v850e_uart_xmit_done(n) && v850e_uart_cts(n)) | |
260 | /* Wait for this to be true. */ | |
261 | #define v850e_uart_wait_for_xmit_ok(n) \ | |
262 | do { } while (! v850e_uart_xmit_ok (n)) | |
263 | ||
264 | /* Write character CH to uart channel CHAN. */ | |
265 | #define v850e_uart_putc(chan, ch) (V850E_UART_TXB(chan) = (ch)) | |
266 | ||
267 | /* Return latest character read on channel CHAN. */ | |
268 | #define v850e_uart_getc(chan) V850E_UART_RXB (chan) | |
269 | ||
270 | /* Return bit-mask of uart error status. */ | |
271 | #define v850e_uart_err(chan) V850E_UART_ASIS (chan) | |
272 | /* Various error bits set in the error result. */ | |
273 | #define V850E_UART_ERR_OVERRUN V850E_UART_ASIS_OVE | |
274 | #define V850E_UART_ERR_FRAME V850E_UART_ASIS_FE | |
275 | #define V850E_UART_ERR_PARITY V850E_UART_ASIS_PE | |
276 | ||
277 | ||
278 | #endif /* __V850_V850E_UARTA_H__ */ |