[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / include / asm-sparc64 / io.h

/* $Id: io.h,v 1.47 2001/12/13 10:36:02 davem Exp $ */
#ifndef __SPARC64_IO_H
#define __SPARC64_IO_H

#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/types.h>

#include <asm/page.h>      /* IO address mapping routines need this */
#include <asm/system.h>
#include <asm/asi.h>

/* PC crapola... */
#define __SLOW_DOWN_IO	do { } while (0)
#define SLOW_DOWN_IO	do { } while (0)

/* BIO layer definitions. */
extern unsigned long kern_base, kern_size;
#define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)
#define BIO_VMERGE_BOUNDARY	8192

static __inline__ u8 _inb(unsigned long addr)
{
	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));

	return ret;
}

static __inline__ u16 _inw(unsigned long addr)
{
	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));

	return ret;
}

static __inline__ u32 _inl(unsigned long addr)
{
	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));

	return ret;
}

static __inline__ void _outb(u8 b, unsigned long addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

static __inline__ void _outw(u16 w, unsigned long addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

static __inline__ void _outl(u32 l, unsigned long addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

#define inb(__addr)		(_inb((unsigned long)(__addr)))
#define inw(__addr)		(_inw((unsigned long)(__addr)))
#define inl(__addr)		(_inl((unsigned long)(__addr)))
#define outb(__b, __addr)	(_outb((u8)(__b), (unsigned long)(__addr)))
#define outw(__w, __addr)	(_outw((u16)(__w), (unsigned long)(__addr)))
#define outl(__l, __addr)	(_outl((u32)(__l), (unsigned long)(__addr)))

#define inb_p(__addr) 		inb(__addr)
#define outb_p(__b, __addr)	outb(__b, __addr)
#define inw_p(__addr)		inw(__addr)
#define outw_p(__w, __addr)	outw(__w, __addr)
#define inl_p(__addr)		inl(__addr)
#define outl_p(__l, __addr)	outl(__l, __addr)

extern void outsb(unsigned long, const void *, unsigned long);
extern void outsw(unsigned long, const void *, unsigned long);
extern void outsl(unsigned long, const void *, unsigned long);
extern void insb(unsigned long, void *, unsigned long);
extern void insw(unsigned long, void *, unsigned long);
extern void insl(unsigned long, void *, unsigned long);

static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
{
	insb((unsigned long __force)port, buf, count);
}
static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
{
	insw((unsigned long __force)port, buf, count);
}

static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
{
	insl((unsigned long __force)port, buf, count);
}

static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsb((unsigned long __force)port, buf, count);
}

static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsw((unsigned long __force)port, buf, count);
}

static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsl((unsigned long __force)port, buf, count);
}

/* Memory functions, same as I/O accesses on Ultra. */
static inline u8 _readb(const volatile void __iomem *addr)
{	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	return ret;
}

static inline u16 _readw(const volatile void __iomem *addr)
{	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));

	return ret;
}

static inline u32 _readl(const volatile void __iomem *addr)
{	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));

	return ret;
}

static inline u64 _readq(const volatile void __iomem *addr)
{	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));

	return ret;
}

static inline void _writeb(u8 b, volatile void __iomem *addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

static inline void _writew(u16 w, volatile void __iomem *addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

static inline void _writel(u32 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

static inline void _writeq(u64 q, volatile void __iomem *addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}

#define readb(__addr)		_readb(__addr)
#define readw(__addr)		_readw(__addr)
#define readl(__addr)		_readl(__addr)
#define readq(__addr)		_readq(__addr)
#define readb_relaxed(__addr)	_readb(__addr)
#define readw_relaxed(__addr)	_readw(__addr)
#define readl_relaxed(__addr)	_readl(__addr)
#define readq_relaxed(__addr)	_readq(__addr)
#define writeb(__b, __addr)	_writeb(__b, __addr)
#define writew(__w, __addr)	_writew(__w, __addr)
#define writel(__l, __addr)	_writel(__l, __addr)
#define writeq(__q, __addr)	_writeq(__q, __addr)

/* Now versions without byte-swapping. */
static __inline__ u8 _raw_readb(unsigned long addr)
{
	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static __inline__ u16 _raw_readw(unsigned long addr)
{
	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static __inline__ u32 _raw_readl(unsigned long addr)
{
	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static __inline__ u64 _raw_readq(unsigned long addr)
{
	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static __inline__ void _raw_writeb(u8 b, unsigned long addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static __inline__ void _raw_writew(u16 w, unsigned long addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static __inline__ void _raw_writel(u32 l, unsigned long addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static __inline__ void _raw_writeq(u64 q, unsigned long addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

#define __raw_readb(__addr)		(_raw_readb((unsigned long)(__addr)))
#define __raw_readw(__addr)		(_raw_readw((unsigned long)(__addr)))
#define __raw_readl(__addr)		(_raw_readl((unsigned long)(__addr)))
#define __raw_readq(__addr)		(_raw_readq((unsigned long)(__addr)))
#define __raw_writeb(__b, __addr)	(_raw_writeb((u8)(__b), (unsigned long)(__addr)))
#define __raw_writew(__w, __addr)	(_raw_writew((u16)(__w), (unsigned long)(__addr)))
#define __raw_writel(__l, __addr)	(_raw_writel((u32)(__l), (unsigned long)(__addr)))
#define __raw_writeq(__q, __addr)	(_raw_writeq((u64)(__q), (unsigned long)(__addr)))

/* Valid I/O Space regions are anywhere, because each PCI bus supported
 * can live in an arbitrary area of the physical address range.
 */
#define IO_SPACE_LIMIT 0xffffffffffffffffUL

/* Now, SBUS variants, only difference from PCI is that we do
 * not use little-endian ASIs.
 */
static inline u8 _sbus_readb(const volatile void __iomem *addr)
{
	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline u16 _sbus_readw(const volatile void __iomem *addr)
{
	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline u32 _sbus_readl(const volatile void __iomem *addr)
{
	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline u64 _sbus_readq(const volatile void __iomem *addr)
{
	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

#define sbus_readb(__addr)		_sbus_readb(__addr)
#define sbus_readw(__addr)		_sbus_readw(__addr)
#define sbus_readl(__addr)		_sbus_readl(__addr)
#define sbus_readq(__addr)		_sbus_readq(__addr)
#define sbus_writeb(__b, __addr)	_sbus_writeb(__b, __addr)
#define sbus_writew(__w, __addr)	_sbus_writew(__w, __addr)
#define sbus_writel(__l, __addr)	_sbus_writel(__l, __addr)
#define sbus_writeq(__l, __addr)	_sbus_writeq(__l, __addr)

static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
	while(n--) {
		sbus_writeb(c, dst);
		dst++;
	}
}

#define sbus_memset_io(d,c,sz)	_sbus_memset_io(d,c,sz)

static inline void
_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
	volatile void __iomem *d = dst;

	while (n--) {
		writeb(c, d);
		d++;
	}
}

#define memset_io(d,c,sz)	_memset_io(d,c,sz)

static inline void
_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
{
	char *d = dst;

	while (n--) {
		char tmp = readb(src);
		*d++ = tmp;
		src++;
	}
}

#define memcpy_fromio(d,s,sz)	_memcpy_fromio(d,s,sz)

static inline void 
_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
{
	const char *s = src;
	volatile void __iomem *d = dst;

	while (n--) {
		char tmp = *s++;
		writeb(tmp, d);
		d++;
	}
}

#define memcpy_toio(d,s,sz)	_memcpy_toio(d,s,sz)

#define mmiowb()

#ifdef __KERNEL__

/* On sparc64 we have the whole physical IO address space accessible
 * using physically addressed loads and stores, so this does nothing.
 */
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
	return (void __iomem *)offset;
}

#define ioremap_nocache(X,Y)		ioremap((X),(Y))

static inline void iounmap(volatile void __iomem *addr)
{
}

#define ioread8(X)			readb(X)
#define ioread16(X)			readw(X)
#define ioread32(X)			readl(X)
#define iowrite8(val,X)			writeb(val,X)
#define iowrite16(val,X)		writew(val,X)
#define iowrite32(val,X)		writel(val,X)

/* Create a virtual mapping cookie for an IO port range */
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *);

/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);

/* Similarly for SBUS. */
#define sbus_ioremap(__res, __offset, __size, __name) \
({	unsigned long __ret; \
	__ret  = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
	__ret += (unsigned long) (__offset); \
	if (! request_region((__ret), (__size), (__name))) \
		__ret = 0UL; \
	(void __iomem *) __ret; \
})

#define sbus_iounmap(__addr, __size)	\
	release_region((unsigned long)(__addr), (__size))

/* Nothing to do */

#define dma_cache_inv(_start,_size)		do { } while (0)
#define dma_cache_wback(_start,_size)		do { } while (0)
#define dma_cache_wback_inv(_start,_size)	do { } while (0)

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#endif

#endif /* !(__SPARC64_IO_H) */
Commit	Line	Data
1da177e4 LT	1	/* $Id: io.h,v 1.47 2001/12/13 10:36:02 davem Exp $ */
	2	#ifndef __SPARC64_IO_H
	3	#define __SPARC64_IO_H
	4
	5	#include <linux/kernel.h>
	6	#include <linux/compiler.h>
	7	#include <linux/types.h>
	8
	9	#include <asm/page.h> /* IO address mapping routines need this */
	10	#include <asm/system.h>
	11	#include <asm/asi.h>
	12
	13	/* PC crapola... */
	14	#define __SLOW_DOWN_IO do { } while (0)
	15	#define SLOW_DOWN_IO do { } while (0)
	16
1da177e4 LT	17	/* BIO layer definitions. */
	18	extern unsigned long kern_base, kern_size;
	19	#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
	20	#define BIO_VMERGE_BOUNDARY 8192
	21
1da177e4 LT	22	static __inline__ u8 _inb(unsigned long addr)
	23	{
	24	u8 ret;
	25
	26	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
	27	: "=r" (ret)
	28	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	29
	30	return ret;
	31	}
	32
	33	static __inline__ u16 _inw(unsigned long addr)
	34	{
	35	u16 ret;
	36
	37	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
	38	: "=r" (ret)
	39	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	40
	41	return ret;
	42	}
	43
	44	static __inline__ u32 _inl(unsigned long addr)
	45	{
	46	u32 ret;
	47
	48	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
	49	: "=r" (ret)
	50	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	51
	52	return ret;
	53	}
	54
	55	static __inline__ void _outb(u8 b, unsigned long addr)
	56	{
	57	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
	58	: /* no outputs */
	59	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	60	}
	61
	62	static __inline__ void _outw(u16 w, unsigned long addr)
	63	{
	64	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
	65	: /* no outputs */
	66	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	67	}
	68
	69	static __inline__ void _outl(u32 l, unsigned long addr)
	70	{
	71	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
	72	: /* no outputs */
	73	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	74	}
	75
	76	#define inb(__addr) (_inb((unsigned long)(__addr)))
	77	#define inw(__addr) (_inw((unsigned long)(__addr)))
	78	#define inl(__addr) (_inl((unsigned long)(__addr)))
	79	#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
	80	#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
	81	#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
	82
	83	#define inb_p(__addr) inb(__addr)
	84	#define outb_p(__b, __addr) outb(__b, __addr)
	85	#define inw_p(__addr) inw(__addr)
86	#define outw_p(__w, __addr) outw(__w, __addr)
87	#define inl_p(__addr) inl(__addr)
88	#define outl_p(__l, __addr) outl(__l, __addr)
89
8a36895c DM	90	extern void outsb(unsigned long, const void *, unsigned long);
	91	extern void outsw(unsigned long, const void *, unsigned long);
	92	extern void outsl(unsigned long, const void *, unsigned long);
	93	extern void insb(unsigned long, void *, unsigned long);
	94	extern void insw(unsigned long, void *, unsigned long);
	95	extern void insl(unsigned long, void *, unsigned long);
	96
	97	static inline void ioread8_rep(void __iomem port, void buf, unsigned long count)
	98	{
	99	insb((unsigned long __force)port, buf, count);
	100	}
	101	static inline void ioread16_rep(void __iomem port, void buf, unsigned long count)
	102	{
	103	insw((unsigned long __force)port, buf, count);
	104	}
	105
	106	static inline void ioread32_rep(void __iomem port, void buf, unsigned long count)
	107	{
	108	insl((unsigned long __force)port, buf, count);
	109	}
	110
	111	static inline void iowrite8_rep(void __iomem port, const void buf, unsigned long count)
	112	{
	113	outsb((unsigned long __force)port, buf, count);
	114	}
	115
	116	static inline void iowrite16_rep(void __iomem port, const void buf, unsigned long count)
	117	{
	118	outsw((unsigned long __force)port, buf, count);
	119	}
	120
	121	static inline void iowrite32_rep(void __iomem port, const void buf, unsigned long count)
	122	{
	123	outsl((unsigned long __force)port, buf, count);
	124	}
1da177e4 LT	125
	126	/* Memory functions, same as I/O accesses on Ultra. */
	127	static inline u8 _readb(const volatile void __iomem *addr)
	128	{ u8 ret;
	129
	130	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
	131	: "=r" (ret)
	132	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	133	return ret;
	134	}
	135
	136	static inline u16 _readw(const volatile void __iomem *addr)
	137	{ u16 ret;
	138
	139	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
	140	: "=r" (ret)
	141	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	142
	143	return ret;
	144	}
	145
	146	static inline u32 _readl(const volatile void __iomem *addr)
	147	{ u32 ret;
	148
	149	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
	150	: "=r" (ret)
	151	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	152
	153	return ret;
	154	}
	155
	156	static inline u64 _readq(const volatile void __iomem *addr)
	157	{ u64 ret;
	158
	159	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
	160	: "=r" (ret)
	161	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	162
	163	return ret;
	164	}
	165
	166	static inline void _writeb(u8 b, volatile void __iomem *addr)
	167	{
	168	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
	169	: /* no outputs */
	170	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	171	}
	172
	173	static inline void _writew(u16 w, volatile void __iomem *addr)
	174	{
	175	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
	176	: /* no outputs */
	177	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	178	}
	179
	180	static inline void _writel(u32 l, volatile void __iomem *addr)
	181	{
	182	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
	183	: /* no outputs */
	184	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
	185	}
	186
	187	static inline void _writeq(u64 q, volatile void __iomem *addr)
	188	{
189	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
190	: /* no outputs */
191	: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
192	}
193
194	#define readb(__addr) _readb(__addr)
195	#define readw(__addr) _readw(__addr)
196	#define readl(__addr) _readl(__addr)
197	#define readq(__addr) _readq(__addr)
198	#define readb_relaxed(__addr) _readb(__addr)
199	#define readw_relaxed(__addr) _readw(__addr)
200	#define readl_relaxed(__addr) _readl(__addr)
201	#define readq_relaxed(__addr) _readq(__addr)
202	#define writeb(__b, __addr) _writeb(__b, __addr)
203	#define writew(__w, __addr) _writew(__w, __addr)
204	#define writel(__l, __addr) _writel(__l, __addr)
205	#define writeq(__q, __addr) _writeq(__q, __addr)
206
207	/* Now versions without byte-swapping. */
208	static __inline__ u8 _raw_readb(unsigned long addr)
209	{
210	u8 ret;
211
212	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
213	: "=r" (ret)
214	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
215
216	return ret;
217	}
218
219	static __inline__ u16 _raw_readw(unsigned long addr)
220	{
221	u16 ret;
222
223	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
224	: "=r" (ret)
225	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
226
227	return ret;
228	}
229
230	static __inline__ u32 _raw_readl(unsigned long addr)
231	{
232	u32 ret;
233
234	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
235	: "=r" (ret)
236	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
237
238	return ret;
239	}
240
241	static __inline__ u64 _raw_readq(unsigned long addr)
242	{
243	u64 ret;
244
245	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
246	: "=r" (ret)
247	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
248
249	return ret;
250	}
251
252	static __inline__ void _raw_writeb(u8 b, unsigned long addr)
253	{
254	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
255	: /* no outputs */
256	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
257	}
258
259	static __inline__ void _raw_writew(u16 w, unsigned long addr)
260	{
261	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
262	: /* no outputs */
263	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
264	}
265
266	static __inline__ void _raw_writel(u32 l, unsigned long addr)
267	{
268	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
269	: /* no outputs */
270	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
271	}
272
273	static __inline__ void _raw_writeq(u64 q, unsigned long addr)
274	{
275	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
276	: /* no outputs */
277	: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
278	}
279
280	#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
281	#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
282	#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
283	#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
284	#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
285	#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
286	#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
287	#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
288
289	/* Valid I/O Space regions are anywhere, because each PCI bus supported
290	* can live in an arbitrary area of the physical address range.
291	*/
292	#define IO_SPACE_LIMIT 0xffffffffffffffffUL
293
294	/* Now, SBUS variants, only difference from PCI is that we do
295	* not use little-endian ASIs.
296	*/
297	static inline u8 _sbus_readb(const volatile void __iomem *addr)
298	{
299	u8 ret;
300
301	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
302	: "=r" (ret)
303	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
304
305	return ret;
306	}
307
308	static inline u16 _sbus_readw(const volatile void __iomem *addr)
309	{
310	u16 ret;
311
312	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
313	: "=r" (ret)
314	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
315
316	return ret;
317	}
318
319	static inline u32 _sbus_readl(const volatile void __iomem *addr)
320	{
321	u32 ret;
322
323	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
324	: "=r" (ret)
325	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
326
327	return ret;
328	}
329
330	static inline u64 _sbus_readq(const volatile void __iomem *addr)
331	{
332	u64 ret;
333
334	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
335	: "=r" (ret)
336	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
337
338	return ret;
339	}
340
341	static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
342	{
343	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
344	: /* no outputs */
345	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
346	}
347
348	static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
349	{
350	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
351	: /* no outputs */
352	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
353	}
354
355	static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
356	{
357	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
358	: /* no outputs */
359	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
360	}
361
362	static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
363	{
364	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
365	: /* no outputs */
366	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
367	}
368
369	#define sbus_readb(__addr) _sbus_readb(__addr)
370	#define sbus_readw(__addr) _sbus_readw(__addr)
371	#define sbus_readl(__addr) _sbus_readl(__addr)
372	#define sbus_readq(__addr) _sbus_readq(__addr)
373	#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
374	#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
375	#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
376	#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
377
378	static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
379	{
380	while(n--) {
381	sbus_writeb(c, dst);
382	dst++;
383	}
384	}
385
386	#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
387
388	static inline void
389	_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
390	{
391	volatile void __iomem *d = dst;
392
393	while (n--) {
394	writeb(c, d);
395	d++;
396	}
397	}
398
399	#define memset_io(d,c,sz) _memset_io(d,c,sz)
400
401	static inline void
402	_memcpy_fromio(void dst, const volatile void __iomem src, __kernel_size_t n)
403	{
404	char *d = dst;
405
406	while (n--) {
407	char tmp = readb(src);
408	*d++ = tmp;
409	src++;
410	}
411	}
412
413	#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
414
415	static inline void
416	_memcpy_toio(volatile void __iomem dst, const void src, __kernel_size_t n)
417	{
418	const char *s = src;
419	volatile void __iomem *d = dst;
420
421	while (n--) {
422	char tmp = *s++;
423	writeb(tmp, d);
424	d++;
425	}
426	}
427
428	#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
429
1da177e4 LT	430	#define mmiowb()
	431
	432	#ifdef __KERNEL__
	433
	434	/* On sparc64 we have the whole physical IO address space accessible
	435	* using physically addressed loads and stores, so this does nothing.
	436	*/
	437	static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
	438	{
	439	return (void __iomem *)offset;
	440	}
	441
	442	#define ioremap_nocache(X,Y) ioremap((X),(Y))
	443
	444	static inline void iounmap(volatile void __iomem *addr)
	445	{
	446	}
	447
	448	#define ioread8(X) readb(X)
	449	#define ioread16(X) readw(X)
	450	#define ioread32(X) readl(X)
	451	#define iowrite8(val,X) writeb(val,X)
	452	#define iowrite16(val,X) writew(val,X)
	453	#define iowrite32(val,X) writel(val,X)
	454
	455	/* Create a virtual mapping cookie for an IO port range */
	456	extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
	457	extern void ioport_unmap(void __iomem *);
	458
	459	/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
	460	struct pci_dev;
	461	extern void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long max);
	462	extern void pci_iounmap(struct pci_dev dev, void __iomem );
	463
	464	/* Similarly for SBUS. */
	465	#define sbus_ioremap(__res, __offset, __size, __name) \
	466	({ unsigned long __ret; \
	467	__ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
	468	__ret += (unsigned long) (__offset); \
	469	if (! request_region((__ret), (__size), (__name))) \
	470	__ret = 0UL; \
	471	(void __iomem *) __ret; \
	472	})
	473
	474	#define sbus_iounmap(__addr, __size) \
	475	release_region((unsigned long)(__addr), (__size))
	476
	477	/* Nothing to do */
	478
	479	#define dma_cache_inv(_start,_size) do { } while (0)
	480	#define dma_cache_wback(_start,_size) do { } while (0)
	481	#define dma_cache_wback_inv(_start,_size) do { } while (0)
	482
	483	/*
	484	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	485	* access
	486	*/
	487	#define xlate_dev_mem_ptr(p) __va(p)
	488
	489	/*
	490	* Convert a virtual cached pointer to an uncached pointer
	491	*/
	492	#define xlate_dev_kmem_ptr(p) p
	493
494	#endif
495
496	#endif /* !(__SPARC64_IO_H) */