[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-ppc64 / oprofile_impl.h

/*
 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * Based on alpha version.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef OP_IMPL_H
#define OP_IMPL_H 1

#define OP_MAX_COUNTER 8

/* Per-counter configuration as set via oprofilefs.  */
struct op_counter_config {
	unsigned long valid;
	unsigned long enabled;
	unsigned long event;
	unsigned long count;
	unsigned long kernel;
	/* We dont support per counter user/kernel selection */
	unsigned long user;
	unsigned long unit_mask;
};

/* System-wide configuration as set via oprofilefs.  */
struct op_system_config {
	unsigned long mmcr0;
	unsigned long mmcr1;
	unsigned long mmcra;
	unsigned long enable_kernel;
	unsigned long enable_user;
	unsigned long backtrace_spinlocks;
};

/* Per-arch configuration */
struct op_ppc64_model {
	void (*reg_setup) (struct op_counter_config *,
			   struct op_system_config *,
			   int num_counters);
	void (*cpu_setup) (void *);
	void (*start) (struct op_counter_config *);
	void (*stop) (void);
	void (*handle_interrupt) (struct pt_regs *,
				  struct op_counter_config *);
	int num_counters;
};

extern struct op_ppc64_model op_model_rs64;
extern struct op_ppc64_model op_model_power4;

static inline unsigned int ctr_read(unsigned int i)
{
	switch(i) {
	case 0:
		return mfspr(SPRN_PMC1);
	case 1:
		return mfspr(SPRN_PMC2);
	case 2:
		return mfspr(SPRN_PMC3);
	case 3:
		return mfspr(SPRN_PMC4);
	case 4:
		return mfspr(SPRN_PMC5);
	case 5:
		return mfspr(SPRN_PMC6);
	case 6:
		return mfspr(SPRN_PMC7);
	case 7:
		return mfspr(SPRN_PMC8);
	default:
		return 0;
	}
}

static inline void ctr_write(unsigned int i, unsigned int val)
{
	switch(i) {
	case 0:
		mtspr(SPRN_PMC1, val);
		break;
	case 1:
		mtspr(SPRN_PMC2, val);
		break;
	case 2:
		mtspr(SPRN_PMC3, val);
		break;
	case 3:
		mtspr(SPRN_PMC4, val);
		break;
	case 4:
		mtspr(SPRN_PMC5, val);
		break;
	case 5:
		mtspr(SPRN_PMC6, val);
		break;
	case 6:
		mtspr(SPRN_PMC7, val);
		break;
	case 7:
		mtspr(SPRN_PMC8, val);
		break;
	default:
		break;
	}
}

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
	3	*
	4	* Based on alpha version.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#ifndef OP_IMPL_H
	13	#define OP_IMPL_H 1
	14
	15	#define OP_MAX_COUNTER 8
	16
	17	/* Per-counter configuration as set via oprofilefs. */
	18	struct op_counter_config {
	19	unsigned long valid;
	20	unsigned long enabled;
	21	unsigned long event;
	22	unsigned long count;
	23	unsigned long kernel;
	24	/* We dont support per counter user/kernel selection */
	25	unsigned long user;
	26	unsigned long unit_mask;
	27	};
	28
	29	/* System-wide configuration as set via oprofilefs. */
	30	struct op_system_config {
	31	unsigned long mmcr0;
	32	unsigned long mmcr1;
	33	unsigned long mmcra;
	34	unsigned long enable_kernel;
	35	unsigned long enable_user;
	36	unsigned long backtrace_spinlocks;
	37	};
	38
	39	/* Per-arch configuration */
	40	struct op_ppc64_model {
	41	void (reg_setup) (struct op_counter_config ,
	42	struct op_system_config *,
	43	int num_counters);
	44	void (cpu_setup) (void );
	45	void (start) (struct op_counter_config );
	46	void (*stop) (void);
	47	void (handle_interrupt) (struct pt_regs ,
	48	struct op_counter_config *);
	49	int num_counters;
	50	};
	51
dca85932 AB	52	extern struct op_ppc64_model op_model_rs64;
	53	extern struct op_ppc64_model op_model_power4;
	54
1da177e4 LT	55	static inline unsigned int ctr_read(unsigned int i)
	56	{
	57	switch(i) {
	58	case 0:
	59	return mfspr(SPRN_PMC1);
	60	case 1:
	61	return mfspr(SPRN_PMC2);
	62	case 2:
	63	return mfspr(SPRN_PMC3);
	64	case 3:
	65	return mfspr(SPRN_PMC4);
	66	case 4:
	67	return mfspr(SPRN_PMC5);
	68	case 5:
	69	return mfspr(SPRN_PMC6);
	70	case 6:
	71	return mfspr(SPRN_PMC7);
	72	case 7:
	73	return mfspr(SPRN_PMC8);
	74	default:
	75	return 0;
	76	}
	77	}
	78
	79	static inline void ctr_write(unsigned int i, unsigned int val)
	80	{
	81	switch(i) {
	82	case 0:
	83	mtspr(SPRN_PMC1, val);
	84	break;
	85	case 1:
	86	mtspr(SPRN_PMC2, val);
	87	break;
	88	case 2:
	89	mtspr(SPRN_PMC3, val);
	90	break;
	91	case 3:
	92	mtspr(SPRN_PMC4, val);
	93	break;
	94	case 4:
	95	mtspr(SPRN_PMC5, val);
	96	break;
	97	case 5:
	98	mtspr(SPRN_PMC6, val);
	99	break;
	100	case 6:
	101	mtspr(SPRN_PMC7, val);
	102	break;
	103	case 7:
	104	mtspr(SPRN_PMC8, val);
	105	break;
	106	default:
	107	break;
	108	}
	109	}
	110
	111	#endif