projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 82876526 BB |
1 | /* |
| 2 | * Contains register definitions common to the Book E PowerPC | |
| 3 | * specification. Notice that while the IBM-40x series of CPUs | |
| 4 | * are not true Book E PowerPCs, they borrowed a number of features | |
| 5 | * before Book E was finalized, and are included here as well. Unfortunatly, | |
| 6 | * they sometimes used different locations than true Book E CPUs did. | |
| 7 | */ | |
| 8 | #ifdef __KERNEL__ | |
| 9 | #ifndef __ASM_POWERPC_REG_BOOKE_H__ | |
| 10 | #define __ASM_POWERPC_REG_BOOKE_H__ | |
| 11 | ||
| 82876526 BB |
12 | /* Machine State Register (MSR) Fields */ |
| 13 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ | |
| 14 | #define MSR_SPE (1<<25) /* Enable SPE */ | |
| 15 | #define MSR_DWE (1<<10) /* Debug Wait Enable */ | |
| 16 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | |
| 17 | #define MSR_IS MSR_IR /* Instruction Space */ | |
| 18 | #define MSR_DS MSR_DR /* Data Space */ | |
| 19 | #define MSR_PMM (1<<2) /* Performance monitor mark bit */ | |
| 20 | ||
| 21 | /* Default MSR for kernel mode. */ | |
| 22 | #if defined (CONFIG_40x) | |
| 23 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) | |
| 24 | #elif defined(CONFIG_BOOKE) | |
| 25 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) | |
| 26 | #endif | |
| 27 | ||
| 28 | /* Special Purpose Registers (SPRNs)*/ | |
| 29 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | |
| 30 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ | |
| 31 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ | |
| 32 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ | |
| 33 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | |
| 34 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | |
| 35 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | |
| 36 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | |
| 37 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | |
| 38 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | |
| 39 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | |
| 40 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ | |
| 41 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ | |
| 42 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | |
| 43 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ | |
| 44 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | |
| 45 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ | |
| 46 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | |
| 47 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | |
| 48 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | |
| 49 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | |
| 50 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | |
| 51 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | |
| 52 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | |
| 53 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | |
| 54 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | |
| 55 | #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ | |
| 56 | #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ | |
| 57 | #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ | |
| 58 | #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ | |
| 59 | #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ | |
| 60 | #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ | |
| 61 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ | |
| 62 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ | |
| 63 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | |
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64 | #define SPRN_ATB 0x20E /* Alternate Time Base */ |
| 65 | #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ | |
| 66 | #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ | |
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67 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ |
| 68 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | |
| 69 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | |
| 70 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | |
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71 | #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ |
| 72 | #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ | |
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73 | #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ |
| 74 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ | |
| 75 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ | |
| 76 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ | |
| 77 | #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ | |
| 78 | #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ | |
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79 | #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ |
| 80 | #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ | |
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81 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ |
| 82 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | |
| 83 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | |
| 84 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | |
| 85 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | |
| 86 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | |
| 87 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | |
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88 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ |
| 89 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ | |
| 90 | #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ | |
| 91 | #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ | |
| fd351b89 | 92 | #define SPRN_EPR 0x2BE /* External Proxy Register */ |
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93 | #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ |
| 94 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ | |
| fd351b89 | 95 | #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ |
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96 | #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ |
| 97 | #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ | |
| fd351b89 KG |
98 | #define SPRN_EPLC 0x3B3 /* External Process ID Load Context */ |
| 99 | #define SPRN_EPSC 0x3B4 /* External Process ID Store Context */ | |
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100 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ |
| 101 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | |
| 102 | #define SPRN_SLER 0x3BB /* Little-endian real mode */ | |
| 103 | #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ | |
| 104 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ | |
| 105 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | |
| 106 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | |
| 107 | #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ | |
| 108 | #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ | |
| 109 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ | |
| fd351b89 | 110 | #define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ |
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111 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ |
| 112 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ | |
| 113 | #define SPRN_SVR 0x3FF /* System Version Register */ | |
| 114 | ||
| 115 | /* | |
| 116 | * SPRs which have conflicting definitions on true Book E versus classic, | |
| 117 | * or IBM 40x. | |
| 118 | */ | |
| 119 | #ifdef CONFIG_BOOKE | |
| 120 | #define SPRN_PID 0x030 /* Process ID */ | |
| 121 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | |
| 122 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ | |
| 123 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ | |
| 124 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ | |
| 125 | #define SPRN_ESR 0x03E /* Exception Syndrome Register */ | |
| 126 | #define SPRN_PIR 0x11E /* Processor Identification Register */ | |
| 127 | #define SPRN_DBSR 0x130 /* Debug Status Register */ | |
| 128 | #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ | |
| 129 | #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ | |
| 130 | #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ | |
| 131 | #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ | |
| 132 | #define SPRN_DAC1 0x13C /* Data Address Compare 1 */ | |
| 133 | #define SPRN_DAC2 0x13D /* Data Address Compare 2 */ | |
| 134 | #define SPRN_TSR 0x150 /* Timer Status Register */ | |
| 135 | #define SPRN_TCR 0x154 /* Timer Control Register */ | |
| 136 | #endif /* Book E */ | |
| 137 | #ifdef CONFIG_40x | |
| 138 | #define SPRN_PID 0x3B1 /* Process ID */ | |
| 139 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ | |
| 140 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ | |
| 141 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ | |
| 142 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ | |
| 143 | #define SPRN_TCR 0x3DA /* Timer Control Register */ | |
| 144 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | |
| 145 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ | |
| 146 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | |
| 147 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ | |
| 148 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ | |
| 149 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | |
| 150 | #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ | |
| 151 | #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ | |
| 152 | #endif | |
| 153 | ||
| 154 | /* Bit definitions for CCR1. */ | |
| 155 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ | |
| 156 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | |
| 157 | ||
| 158 | /* Bit definitions for the MCSR. */ | |
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159 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ |
| 160 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | |
| 161 | #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ | |
| 162 | #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ | |
| 163 | #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ | |
| 164 | #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ | |
| 165 | #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ | |
| 166 | #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ | |
| 167 | #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ | |
| 47c0bd1a | 168 | |
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169 | #ifdef CONFIG_E500 |
| 170 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | |
| 171 | #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ | |
| 172 | #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ | |
| 173 | #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ | |
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174 | #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ |
| 175 | #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ | |
| 176 | #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ | |
| 177 | #define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ | |
| 178 | #define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ | |
| 179 | #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ | |
| 180 | #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ | |
| 181 | #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ | |
| 86d7a9a9 BB |
182 | |
| 183 | /* e500 parts may set unused bits in MCSR; mask these off */ | |
| 184 | #define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \ | |
| 185 | MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \ | |
| 186 | MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \ | |
| 187 | MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR) | |
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188 | #endif |
| 189 | #ifdef CONFIG_E200 | |
| 190 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | |
| 191 | #define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ | |
| 192 | #define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ | |
| 193 | #define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn | |
| 194 | fetch for an exception handler */ | |
| 195 | #define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ | |
| 196 | #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ | |
| 197 | #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered | |
| 198 | store or cache line push */ | |
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199 | |
| 200 | /* e200 parts may set unused bits in MCSR; mask these off */ | |
| 201 | #define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \ | |
| 202 | MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \ | |
| 203 | MCSR_BUS_WRERR) | |
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204 | #endif |
| 205 | ||
| 206 | /* Bit definitions for the DBSR. */ | |
| 207 | /* | |
| 208 | * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. | |
| 209 | */ | |
| 210 | #ifdef CONFIG_BOOKE | |
| 211 | #define DBSR_IC 0x08000000 /* Instruction Completion */ | |
| 212 | #define DBSR_BT 0x04000000 /* Branch Taken */ | |
| 213 | #define DBSR_TIE 0x01000000 /* Trap Instruction Event */ | |
| 214 | #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ | |
| 215 | #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ | |
| 216 | #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ | |
| 217 | #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ | |
| 218 | #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ | |
| 219 | #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ | |
| 220 | #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ | |
| 221 | #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ | |
| 222 | #endif | |
| 223 | #ifdef CONFIG_40x | |
| 224 | #define DBSR_IC 0x80000000 /* Instruction Completion */ | |
| 225 | #define DBSR_BT 0x40000000 /* Branch taken */ | |
| 226 | #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ | |
| 227 | #define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ | |
| 228 | #define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ | |
| 229 | #define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ | |
| 230 | #define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ | |
| 231 | #define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ | |
| 232 | #define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ | |
| 233 | #define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ | |
| 234 | #define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ | |
| 235 | #endif | |
| 236 | ||
| 237 | /* Bit definitions related to the ESR. */ | |
| 238 | #define ESR_MCI 0x80000000 /* Machine Check - Instruction */ | |
| 239 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ | |
| 240 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | |
| 241 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | |
| 242 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | |
| 243 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | |
| 567e9fdd | 244 | #define ESR_PPR 0x04000000 /* Program Exception - Privileged */ |
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245 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ |
| 246 | #define ESR_FP 0x01000000 /* Floating Point Operation */ | |
| 247 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | |
| 248 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | |
| 249 | #define ESR_ST 0x00800000 /* Store Operation */ | |
| 250 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ | |
| 251 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ | |
| 252 | #define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ | |
| 253 | #define ESR_BO 0x00020000 /* Byte Ordering */ | |
| 254 | ||
| 255 | /* Bit definitions related to the DBCR0. */ | |
| 256 | #define DBCR0_EDM 0x80000000 /* External Debug Mode */ | |
| 257 | #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ | |
| 258 | #define DBCR0_RST 0x30000000 /* all the bits in the RST field */ | |
| 259 | #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ | |
| 260 | #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ | |
| 261 | #define DBCR0_RST_CORE 0x10000000 /* Core Reset */ | |
| 262 | #define DBCR0_RST_NONE 0x00000000 /* No Reset */ | |
| 263 | #define DBCR0_IC 0x08000000 /* Instruction Completion */ | |
| 264 | #define DBCR0_BT 0x04000000 /* Branch Taken */ | |
| 265 | #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ | |
| 266 | #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ | |
| 267 | #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ | |
| 268 | #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ | |
| 269 | #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ | |
| 270 | #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ | |
| 271 | #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ | |
| 272 | #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ | |
| 273 | #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ | |
| 274 | #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ | |
| 275 | #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ | |
| 276 | #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ | |
| 277 | #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ | |
| 278 | ||
| 279 | /* Bit definitions related to the TCR. */ | |
| 280 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ | |
| 281 | #define TCR_WP_MASK TCR_WP(3) | |
| 282 | #define WP_2_17 0 /* 2^17 clocks */ | |
| 283 | #define WP_2_21 1 /* 2^21 clocks */ | |
| 284 | #define WP_2_25 2 /* 2^25 clocks */ | |
| 285 | #define WP_2_29 3 /* 2^29 clocks */ | |
| 286 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | |
| 287 | #define TCR_WRC_MASK TCR_WRC(3) | |
| 288 | #define WRC_NONE 0 /* No reset will occur */ | |
| 289 | #define WRC_CORE 1 /* Core reset will occur */ | |
| 290 | #define WRC_CHIP 2 /* Chip reset will occur */ | |
| 291 | #define WRC_SYSTEM 3 /* System reset will occur */ | |
| 292 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | |
| 293 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | |
| 294 | #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ | |
| 295 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | |
| 296 | #define TCR_FP_MASK TCR_FP(3) | |
| 297 | #define FP_2_9 0 /* 2^9 clocks */ | |
| 298 | #define FP_2_13 1 /* 2^13 clocks */ | |
| 299 | #define FP_2_17 2 /* 2^17 clocks */ | |
| 300 | #define FP_2_21 3 /* 2^21 clocks */ | |
| 301 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | |
| 302 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | |
| 303 | ||
| 304 | /* Bit definitions for the TSR. */ | |
| 305 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ | |
| 306 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | |
| 307 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | |
| 308 | #define WRS_NONE 0 /* No WDT reset occurred */ | |
| 309 | #define WRS_CORE 1 /* WDT forced core reset */ | |
| 310 | #define WRS_CHIP 2 /* WDT forced chip reset */ | |
| 311 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | |
| 312 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | |
| 313 | #define TSR_DIS TSR_PIS /* DEC Interrupt Status */ | |
| 314 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | |
| 315 | ||
| 316 | /* Bit definitions for the DCCR. */ | |
| 317 | #define DCCR_NOCACHE 0 /* Noncacheable */ | |
| 318 | #define DCCR_CACHE 1 /* Cacheable */ | |
| 319 | ||
| 320 | /* Bit definitions for DCWR. */ | |
| 321 | #define DCWR_COPY 0 /* Copy-back */ | |
| 322 | #define DCWR_WRITE 1 /* Write-through */ | |
| 323 | ||
| 324 | /* Bit definitions for ICCR. */ | |
| 325 | #define ICCR_NOCACHE 0 /* Noncacheable */ | |
| 326 | #define ICCR_CACHE 1 /* Cacheable */ | |
| 327 | ||
| 328 | /* Bit definitions for L1CSR0. */ | |
| 329 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ | |
| 330 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | |
| 331 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | |
| 332 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | |
| 333 | ||
| 334 | /* Bit definitions for L1CSR1. */ | |
| 335 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | |
| 336 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | |
| 337 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | |
| 338 | ||
| 339 | /* Bit definitions for SGR. */ | |
| 340 | #define SGR_NORMAL 0 /* Speculative fetching allowed. */ | |
| 341 | #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ | |
| 342 | ||
| 343 | /* Bit definitions for SPEFSCR. */ | |
| 344 | #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ | |
| 345 | #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ | |
| 346 | #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ | |
| 347 | #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ | |
| 348 | #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ | |
| 349 | #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ | |
| 350 | #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ | |
| 351 | #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ | |
| 352 | #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ | |
| 353 | #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ | |
| 354 | #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ | |
| 355 | #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ | |
| 356 | #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ | |
| 357 | #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ | |
| 358 | #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ | |
| 359 | #define SPEFSCR_OV 0x00004000 /* Integer overflow */ | |
| 360 | #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ | |
| 361 | #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ | |
| 362 | #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ | |
| 363 | #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ | |
| 364 | #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ | |
| 365 | #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ | |
| 366 | #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ | |
| 367 | #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ | |
| 368 | #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ | |
| 369 | #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ | |
| 370 | #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ | |
| 371 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ | |
| 372 | ||
| 373 | /* | |
| 374 | * The IBM-403 is an even more odd special case, as it is much | |
| 375 | * older than the IBM-405 series. We put these down here incase someone | |
| 376 | * wishes to support these machines again. | |
| 377 | */ | |
| 378 | #ifdef CONFIG_403GCX | |
| 379 | /* Special Purpose Registers (SPRNs)*/ | |
| 380 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | |
| 381 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | |
| 382 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ | |
| 383 | #define SPRN_TBHI 0x3DC /* Time Base High */ | |
| 384 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | |
| 385 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ | |
| 386 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ | |
| 387 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | |
| 388 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | |
| 389 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | |
| 390 | ||
| 391 | ||
| 392 | /* Bit definitions for the DBCR. */ | |
| 393 | #define DBCR_EDM DBCR0_EDM | |
| 394 | #define DBCR_IDM DBCR0_IDM | |
| 395 | #define DBCR_RST(x) (((x) & 0x3) << 28) | |
| 396 | #define DBCR_RST_NONE 0 | |
| 397 | #define DBCR_RST_CORE 1 | |
| 398 | #define DBCR_RST_CHIP 2 | |
| 399 | #define DBCR_RST_SYSTEM 3 | |
| 400 | #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ | |
| 401 | #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ | |
| 402 | #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ | |
| 403 | #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ | |
| 404 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | |
| 405 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | |
| 406 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | |
| 407 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | |
| 408 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | |
| 409 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | |
| 410 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | |
| 411 | #define DAC_BYTE 0 | |
| 412 | #define DAC_HALF 1 | |
| 413 | #define DAC_WORD 2 | |
| 414 | #define DAC_QUAD 3 | |
| 415 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | |
| 416 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | |
| 417 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | |
| 418 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | |
| 419 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | |
| 420 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | |
| 421 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | |
| 422 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | |
| 423 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | |
| 424 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | |
| 425 | #endif /* 403GCX */ | |
| 426 | #endif /* __ASM_POWERPC_REG_BOOKE_H__ */ | |
| 427 | #endif /* __KERNEL__ */ |