[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / qe_ic.h

/*
 * include/asm-powerpc/qe_ic.h
 *
 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
 *
 * Authors: 	Shlomi Gridish <gridish@freescale.com>
 * 		Li Yang <leoli@freescale.com>
 *
 * Description:
 * QE IC external definitions and structure.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#ifndef _ASM_POWERPC_QE_IC_H
#define _ASM_POWERPC_QE_IC_H

#include <linux/irq.h>

#define NUM_OF_QE_IC_GROUPS	6

/* Flags when we init the QE IC */
#define QE_IC_SPREADMODE_GRP_W			0x00000001
#define QE_IC_SPREADMODE_GRP_X			0x00000002
#define QE_IC_SPREADMODE_GRP_Y			0x00000004
#define QE_IC_SPREADMODE_GRP_Z			0x00000008
#define QE_IC_SPREADMODE_GRP_RISCA		0x00000010
#define QE_IC_SPREADMODE_GRP_RISCB		0x00000020

#define QE_IC_LOW_SIGNAL			0x00000100
#define QE_IC_HIGH_SIGNAL			0x00000200

#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH	0x00001000
#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH	0x00002000
#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH	0x00004000
#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH	0x00008000
#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH	0x00010000
#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH	0x00020000
#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH	0x00040000
#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH	0x00080000
#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH	0x00100000
#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH	0x00200000
#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH	0x00400000
#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH	0x00800000
#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT		(12)

/* QE interrupt sources groups */
enum qe_ic_grp_id {
	QE_IC_GRP_W = 0,	/* QE interrupt controller group W */
	QE_IC_GRP_X,		/* QE interrupt controller group X */
	QE_IC_GRP_Y,		/* QE interrupt controller group Y */
	QE_IC_GRP_Z,		/* QE interrupt controller group Z */
	QE_IC_GRP_RISCA,	/* QE interrupt controller RISC group A */
	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */
};

void qe_ic_init(struct device_node *node, unsigned int flags,
		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
		void (*high_handler)(unsigned int irq, struct irq_desc *desc));
void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);

struct qe_ic;
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);

static inline void qe_ic_cascade_low_ipic(unsigned int irq,
					  struct irq_desc *desc)
{
	struct qe_ic *qe_ic = desc->handler_data;
	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);
}

static inline void qe_ic_cascade_high_ipic(unsigned int irq,
					   struct irq_desc *desc)
{
	struct qe_ic *qe_ic = desc->handler_data;
	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);
}

static inline void qe_ic_cascade_low_mpic(unsigned int irq,
					  struct irq_desc *desc)
{
	struct qe_ic *qe_ic = desc->handler_data;
	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);

	desc->chip->eoi(irq);
}

static inline void qe_ic_cascade_high_mpic(unsigned int irq,
					   struct irq_desc *desc)
{
	struct qe_ic *qe_ic = desc->handler_data;
	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);

	desc->chip->eoi(irq);
}

static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
					    struct irq_desc *desc)
{
	struct qe_ic *qe_ic = desc->handler_data;
	unsigned int cascade_irq;

	cascade_irq = qe_ic_get_high_irq(qe_ic);
	if (cascade_irq == NO_IRQ)
		cascade_irq = qe_ic_get_low_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);

	desc->chip->eoi(irq);
}

#endif /* _ASM_POWERPC_QE_IC_H */
Commit	Line	Data
98658538 LY	1	/*
	2	* include/asm-powerpc/qe_ic.h
	3	*
	4	* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
	5	*
	6	* Authors: Shlomi Gridish <gridish@freescale.com>
	7	* Li Yang <leoli@freescale.com>
	8	*
	9	* Description:
	10	* QE IC external definitions and structure.
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*/
	17	#ifndef _ASM_POWERPC_QE_IC_H
	18	#define _ASM_POWERPC_QE_IC_H
	19
	20	#include <linux/irq.h>
	21
	22	#define NUM_OF_QE_IC_GROUPS 6
	23
	24	/* Flags when we init the QE IC */
	25	#define QE_IC_SPREADMODE_GRP_W 0x00000001
	26	#define QE_IC_SPREADMODE_GRP_X 0x00000002
	27	#define QE_IC_SPREADMODE_GRP_Y 0x00000004
	28	#define QE_IC_SPREADMODE_GRP_Z 0x00000008
	29	#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
	30	#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
	31
	32	#define QE_IC_LOW_SIGNAL 0x00000100
	33	#define QE_IC_HIGH_SIGNAL 0x00000200
	34
	35	#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
	36	#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
	37	#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
	38	#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
	39	#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
	40	#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
	41	#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
	42	#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
	43	#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
	44	#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
	45	#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
	46	#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
	47	#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
	48
	49	/* QE interrupt sources groups */
	50	enum qe_ic_grp_id {
	51	QE_IC_GRP_W = 0, /* QE interrupt controller group W */
	52	QE_IC_GRP_X, /* QE interrupt controller group X */
	53	QE_IC_GRP_Y, /* QE interrupt controller group Y */
	54	QE_IC_GRP_Z, /* QE interrupt controller group Z */
	55	QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
	56	QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
	57	};
	58
cccd2102 AV	59	void qe_ic_init(struct device_node *node, unsigned int flags,
	60	void (low_handler)(unsigned int irq, struct irq_desc desc),
	61	void (high_handler)(unsigned int irq, struct irq_desc desc));
98658538 LY	62	void qe_ic_set_highest_priority(unsigned int virq, int high);
	63	int qe_ic_set_priority(unsigned int virq, unsigned int priority);
	64	int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
	65
cccd2102 AV	66	struct qe_ic;
	67	unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
	68	unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
	69
	70	static inline void qe_ic_cascade_low_ipic(unsigned int irq,
	71	struct irq_desc *desc)
	72	{
	73	struct qe_ic *qe_ic = desc->handler_data;
	74	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
	75
	76	if (cascade_irq != NO_IRQ)
	77	generic_handle_irq(cascade_irq);
	78	}
	79
	80	static inline void qe_ic_cascade_high_ipic(unsigned int irq,
	81	struct irq_desc *desc)
	82	{
	83	struct qe_ic *qe_ic = desc->handler_data;
	84	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
	85
	86	if (cascade_irq != NO_IRQ)
	87	generic_handle_irq(cascade_irq);
	88	}
	89
	90	static inline void qe_ic_cascade_low_mpic(unsigned int irq,
	91	struct irq_desc *desc)
	92	{
	93	struct qe_ic *qe_ic = desc->handler_data;
	94	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
	95
	96	if (cascade_irq != NO_IRQ)
	97	generic_handle_irq(cascade_irq);
	98
	99	desc->chip->eoi(irq);
	100	}
	101
	102	static inline void qe_ic_cascade_high_mpic(unsigned int irq,
	103	struct irq_desc *desc)
	104	{
	105	struct qe_ic *qe_ic = desc->handler_data;
	106	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
	107
	108	if (cascade_irq != NO_IRQ)
	109	generic_handle_irq(cascade_irq);
	110
	111	desc->chip->eoi(irq);
	112	}
	113
	114	static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
	115	struct irq_desc *desc)
	116	{
	117	struct qe_ic *qe_ic = desc->handler_data;
	118	unsigned int cascade_irq;
	119
	120	cascade_irq = qe_ic_get_high_irq(qe_ic);
	121	if (cascade_irq == NO_IRQ)
	122	cascade_irq = qe_ic_get_low_irq(qe_ic);
	123
	124	if (cascade_irq != NO_IRQ)
	125	generic_handle_irq(cascade_irq);
	126
	127	desc->chip->eoi(irq);
	128	}
	129
98658538	130	#endif /* _ASM_POWERPC_QE_IC_H */