[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / ppc_asm.h

/*
 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
 */
#ifndef _ASM_POWERPC_PPC_ASM_H
#define _ASM_POWERPC_PPC_ASM_H

#include <linux/stringify.h>
#include <asm/asm-compat.h>

#ifndef __ASSEMBLY__
#error __FILE__ should only be used in assembler files
#else

#define SZL			(BITS_PER_LONG/8)

/*
 * Stuff for accurate CPU time accounting.
 * These macros handle transitions between user and system state
 * in exception entry and exit and accumulate time to the
 * user_time and system_time fields in the paca.
 */

#ifndef CONFIG_VIRT_CPU_ACCOUNTING
#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
#define ACCOUNT_CPU_USER_EXIT(ra, rb)
#else
#define ACCOUNT_CPU_USER_ENTRY(ra, rb)					\
	beq	2f;			/* if from kernel mode */	\
BEGIN_FTR_SECTION;							\
	mfspr	ra,SPRN_PURR;		/* get processor util. reg */	\
END_FTR_SECTION_IFSET(CPU_FTR_PURR);					\
BEGIN_FTR_SECTION;							\
	MFTB(ra);			/* or get TB if no PURR */	\
END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
	ld	rb,PACA_STARTPURR(r13);					\
	std	ra,PACA_STARTPURR(r13);					\
	subf	rb,rb,ra;		/* subtract start value */	\
	ld	ra,PACA_USER_TIME(r13);					\
	add	ra,ra,rb;		/* add on to user time */	\
	std	ra,PACA_USER_TIME(r13);					\
2:

#define ACCOUNT_CPU_USER_EXIT(ra, rb)					\
BEGIN_FTR_SECTION;							\
	mfspr	ra,SPRN_PURR;		/* get processor util. reg */	\
END_FTR_SECTION_IFSET(CPU_FTR_PURR);					\
BEGIN_FTR_SECTION;							\
	MFTB(ra);			/* or get TB if no PURR */	\
END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
	ld	rb,PACA_STARTPURR(r13);					\
	std	ra,PACA_STARTPURR(r13);					\
	subf	rb,rb,ra;		/* subtract start value */	\
	ld	ra,PACA_SYSTEM_TIME(r13);				\
	add	ra,ra,rb;		/* add on to user time */	\
	std	ra,PACA_SYSTEM_TIME(r13);
#endif

/*
 * Macros for storing registers into and loading registers from
 * exception frames.
 */
#ifdef __powerpc64__
#define SAVE_GPR(n, base)	std	n,GPR0+8*(n)(base)
#define REST_GPR(n, base)	ld	n,GPR0+8*(n)(base)
#define SAVE_NVGPRS(base)	SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_8GPRS(14, base); REST_10GPRS(22, base)
#else
#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
				SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \
				REST_10GPRS(22, base)
#endif


#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)

#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*(n)(base)
#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)
#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
#define SAVE_8FPRS(n, base)	SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
#define SAVE_16FPRS(n, base)	SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
#define SAVE_32FPRS(n, base)	SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
#define REST_FPR(n, base)	lfd	n,THREAD_FPR0+8*(n)(base)
#define REST_2FPRS(n, base)	REST_FPR(n, base); REST_FPR(n+1, base)
#define REST_4FPRS(n, base)	REST_2FPRS(n, base); REST_2FPRS(n+2, base)
#define REST_8FPRS(n, base)	REST_4FPRS(n, base); REST_4FPRS(n+4, base)
#define REST_16FPRS(n, base)	REST_8FPRS(n, base); REST_8FPRS(n+8, base)
#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)

#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,b,base
#define SAVE_2VRS(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
#define SAVE_4VRS(n,b,base)	SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
#define SAVE_8VRS(n,b,base)	SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
#define SAVE_16VRS(n,b,base)	SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
#define SAVE_32VRS(n,b,base)	SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,b,base
#define REST_2VRS(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)
#define REST_4VRS(n,b,base)	REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
#define REST_8VRS(n,b,base)	REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
#define REST_16VRS(n,b,base)	REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
#define REST_32VRS(n,b,base)	REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)

#define SAVE_EVR(n,s,base)	evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
#define SAVE_2EVRS(n,s,base)	SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
#define SAVE_4EVRS(n,s,base)	SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
#define SAVE_8EVRS(n,s,base)	SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
#define SAVE_16EVRS(n,s,base)	SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
#define SAVE_32EVRS(n,s,base)	SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
#define REST_EVR(n,s,base)	lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
#define REST_2EVRS(n,s,base)	REST_EVR(n,s,base); REST_EVR(n+1,s,base)
#define REST_4EVRS(n,s,base)	REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
#define REST_8EVRS(n,s,base)	REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
#define REST_16EVRS(n,s,base)	REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
#define REST_32EVRS(n,s,base)	REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)

/* Macros to adjust thread priority for hardware multithreading */
#define HMT_VERY_LOW	or	31,31,31	# very low priority
#define HMT_LOW		or	1,1,1
#define HMT_MEDIUM_LOW  or	6,6,6		# medium low priority
#define HMT_MEDIUM	or	2,2,2
#define HMT_MEDIUM_HIGH or	5,5,5		# medium high priority
#define HMT_HIGH	or	3,3,3

/* handle instructions that older assemblers may not know */
#define RFCI		.long 0x4c000066	/* rfci instruction */
#define RFDI		.long 0x4c00004e	/* rfdi instruction */
#define RFMCI		.long 0x4c00004c	/* rfmci instruction */

#ifdef __KERNEL__
#ifdef CONFIG_PPC64

#define XGLUE(a,b) a##b
#define GLUE(a,b) XGLUE(a,b)

#define _GLOBAL(name) \
	.section ".text"; \
	.align 2 ; \
	.globl name; \
	.globl GLUE(.,name); \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#define _INIT_GLOBAL(name) \
	.section ".text.init.refok"; \
	.align 2 ; \
	.globl name; \
	.globl GLUE(.,name); \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#define _KPROBE(name) \
	.section ".kprobes.text","a"; \
	.align 2 ; \
	.globl name; \
	.globl GLUE(.,name); \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#define _STATIC(name) \
	.section ".text"; \
	.align 2 ; \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#define _INIT_STATIC(name) \
	.section ".text.init.refok"; \
	.align 2 ; \
	.section ".opd","aw"; \
name: \
	.quad GLUE(.,name); \
	.quad .TOC.@tocbase; \
	.quad 0; \
	.previous; \
	.type GLUE(.,name),@function; \
GLUE(.,name):

#else /* 32-bit */

#define _ENTRY(n)	\
	.globl n;	\
n:

#define _GLOBAL(n)	\
	.text;		\
	.stabs __stringify(n:F-1),N_FUN,0,0,n;\
	.globl n;	\
n:

#define _KPROBE(n)	\
	.section ".kprobes.text","a";	\
	.globl	n;	\
n:

#endif

/* 
 * LOAD_REG_IMMEDIATE(rn, expr)
 *   Loads the value of the constant expression 'expr' into register 'rn'
 *   using immediate instructions only.  Use this when it's important not
 *   to reference other data (i.e. on ppc64 when the TOC pointer is not
 *   valid).
 *
 * LOAD_REG_ADDR(rn, name)
 *   Loads the address of label 'name' into register 'rn'.  Use this when
 *   you don't particularly need immediate instructions only, but you need
 *   the whole address in one register (e.g. it's a structure address and
 *   you want to access various offsets within it).  On ppc32 this is
 *   identical to LOAD_REG_IMMEDIATE.
 *
 * LOAD_REG_ADDRBASE(rn, name)
 * ADDROFF(name)
 *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
 *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
 *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
 *   in size, so is suitable for use directly as an offset in load and store
 *   instructions.  Use this when loading/storing a single word or less as:
 *      LOAD_REG_ADDRBASE(rX, name)
 *      ld	rY,ADDROFF(name)(rX)
 */
#ifdef __powerpc64__
#define LOAD_REG_IMMEDIATE(reg,expr)		\
	lis     (reg),(expr)@highest;		\
	ori     (reg),(reg),(expr)@higher;	\
	rldicr  (reg),(reg),32,31;		\
	oris    (reg),(reg),(expr)@h;		\
	ori     (reg),(reg),(expr)@l;

#define LOAD_REG_ADDR(reg,name)			\
	ld	(reg),name@got(r2)

#define LOAD_REG_ADDRBASE(reg,name)	LOAD_REG_ADDR(reg,name)
#define ADDROFF(name)			0

/* offsets for stack frame layout */
#define LRSAVE	16

#else /* 32-bit */

#define LOAD_REG_IMMEDIATE(reg,expr)		\
	lis	(reg),(expr)@ha;		\
	addi	(reg),(reg),(expr)@l;

#define LOAD_REG_ADDR(reg,name)		LOAD_REG_IMMEDIATE(reg, name)

#define LOAD_REG_ADDRBASE(reg, name)	lis	(reg),name@ha
#define ADDROFF(name)			name@l

/* offsets for stack frame layout */
#define LRSAVE	4

#endif

/* various errata or part fixups */
#ifdef CONFIG_PPC601_SYNC_FIX
#define SYNC				\
BEGIN_FTR_SECTION			\
	sync;				\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define SYNC_601			\
BEGIN_FTR_SECTION			\
	sync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define ISYNC_601			\
BEGIN_FTR_SECTION			\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#else
#define	SYNC
#define SYNC_601
#define ISYNC_601
#endif

#ifdef CONFIG_PPC_CELL
#define MFTB(dest)			\
90:	mftb  dest;			\
BEGIN_FTR_SECTION_NESTED(96);		\
	cmpwi dest,0;			\
	beq-  90b;			\
END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
#else
#define MFTB(dest)			mftb dest
#endif

#ifndef CONFIG_SMP
#define TLBSYNC
#else /* CONFIG_SMP */
/* tlbsync is not implemented on 601 */
#define TLBSYNC				\
BEGIN_FTR_SECTION			\
	tlbsync;			\
	sync;				\
END_FTR_SECTION_IFCLR(CPU_FTR_601)
#endif

	
/*
 * This instruction is not implemented on the PPC 603 or 601; however, on
 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 * All of these instructions exist in the 8xx, they have magical powers,
 * and they must be used.
 */

#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
#define tlbia					\
	li	r4,1024;			\
	mtctr	r4;				\
	lis	r4,KERNELBASE@h;		\
0:	tlbie	r4;				\
	addi	r4,r4,0x1000;			\
	bdnz	0b
#endif


#ifdef CONFIG_IBM440EP_ERR42
#define PPC440EP_ERR42 isync
#else
#define PPC440EP_ERR42
#endif


#if defined(CONFIG_BOOKE)
#define toreal(rd)
#define fromreal(rd)

#define tophys(rd,rs)				\
	addis	rd,rs,0

#define tovirt(rd,rs)				\
	addis	rd,rs,0

#elif defined(CONFIG_PPC64)
#define toreal(rd)		/* we can access c000... in real mode */
#define fromreal(rd)

#define tophys(rd,rs)                           \
	clrldi	rd,rs,2

#define tovirt(rd,rs)                           \
	rotldi	rd,rs,16;			\
	ori	rd,rd,((KERNELBASE>>48)&0xFFFF);\
	rotldi	rd,rd,48
#else
/*
 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 * physical base address of RAM at compile time.
 */
#define toreal(rd)	tophys(rd,rd)
#define fromreal(rd)	tovirt(rd,rd)

#define tophys(rd,rs)				\
0:	addis	rd,rs,-KERNELBASE@h;		\
	.section ".vtop_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous

#define tovirt(rd,rs)				\
0:	addis	rd,rs,KERNELBASE@h;		\
	.section ".ptov_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous
#endif

#ifdef CONFIG_PPC64
#define RFI		rfid
#define MTMSRD(r)	mtmsrd	r

#else
#define FIX_SRR1(ra, rb)
#ifndef CONFIG_40x
#define	RFI		rfi
#else
#define RFI		rfi; b .	/* Prevent prefetch past rfi */
#endif
#define MTMSRD(r)	mtmsr	r
#define CLR_TOP32(r)
#endif

#endif /* __KERNEL__ */

/* The boring bits... */

/* Condition Register Bit Fields */

#define	cr0	0
#define	cr1	1
#define	cr2	2
#define	cr3	3
#define	cr4	4
#define	cr5	5
#define	cr6	6
#define	cr7	7


/* General Purpose Registers (GPRs) */

#define	r0	0
#define	r1	1
#define	r2	2
#define	r3	3
#define	r4	4
#define	r5	5
#define	r6	6
#define	r7	7
#define	r8	8
#define	r9	9
#define	r10	10
#define	r11	11
#define	r12	12
#define	r13	13
#define	r14	14
#define	r15	15
#define	r16	16
#define	r17	17
#define	r18	18
#define	r19	19
#define	r20	20
#define	r21	21
#define	r22	22
#define	r23	23
#define	r24	24
#define	r25	25
#define	r26	26
#define	r27	27
#define	r28	28
#define	r29	29
#define	r30	30
#define	r31	31


/* Floating Point Registers (FPRs) */

#define	fr0	0
#define	fr1	1
#define	fr2	2
#define	fr3	3
#define	fr4	4
#define	fr5	5
#define	fr6	6
#define	fr7	7
#define	fr8	8
#define	fr9	9
#define	fr10	10
#define	fr11	11
#define	fr12	12
#define	fr13	13
#define	fr14	14
#define	fr15	15
#define	fr16	16
#define	fr17	17
#define	fr18	18
#define	fr19	19
#define	fr20	20
#define	fr21	21
#define	fr22	22
#define	fr23	23
#define	fr24	24
#define	fr25	25
#define	fr26	26
#define	fr27	27
#define	fr28	28
#define	fr29	29
#define	fr30	30
#define	fr31	31

/* AltiVec Registers (VPRs) */

#define	vr0	0
#define	vr1	1
#define	vr2	2
#define	vr3	3
#define	vr4	4
#define	vr5	5
#define	vr6	6
#define	vr7	7
#define	vr8	8
#define	vr9	9
#define	vr10	10
#define	vr11	11
#define	vr12	12
#define	vr13	13
#define	vr14	14
#define	vr15	15
#define	vr16	16
#define	vr17	17
#define	vr18	18
#define	vr19	19
#define	vr20	20
#define	vr21	21
#define	vr22	22
#define	vr23	23
#define	vr24	24
#define	vr25	25
#define	vr26	26
#define	vr27	27
#define	vr28	28
#define	vr29	29
#define	vr30	30
#define	vr31	31

/* SPE Registers (EVPRs) */

#define	evr0	0
#define	evr1	1
#define	evr2	2
#define	evr3	3
#define	evr4	4
#define	evr5	5
#define	evr6	6
#define	evr7	7
#define	evr8	8
#define	evr9	9
#define	evr10	10
#define	evr11	11
#define	evr12	12
#define	evr13	13
#define	evr14	14
#define	evr15	15
#define	evr16	16
#define	evr17	17
#define	evr18	18
#define	evr19	19
#define	evr20	20
#define	evr21	21
#define	evr22	22
#define	evr23	23
#define	evr24	24
#define	evr25	25
#define	evr26	26
#define	evr27	27
#define	evr28	28
#define	evr29	29
#define	evr30	30
#define	evr31	31

/* some stab codes */
#define N_FUN	36
#define N_RSYM	64
#define N_SLINE	68
#define N_SO	100

#endif /*  __ASSEMBLY__ */

#endif /* _ASM_POWERPC_PPC_ASM_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
1da177e4	3	*/
5f7c6907 KG	4	#ifndef _ASM_POWERPC_PPC_ASM_H
	5	#define _ASM_POWERPC_PPC_ASM_H
	6
40ef8cbc	7	#include <linux/stringify.h>
3ddfbcf1	8	#include <asm/asm-compat.h>
40ef8cbc	9
3ddfbcf1 DG	10	#ifndef __ASSEMBLY__
	11	#error __FILE__ should only be used in assembler files
	12	#else
	13
	14	#define SZL (BITS_PER_LONG/8)
1da177e4	15
c6622f63 PM	16	/*
	17	* Stuff for accurate CPU time accounting.
	18	* These macros handle transitions between user and system state
	19	* in exception entry and exit and accumulate time to the
	20	* user_time and system_time fields in the paca.
	21	*/
	22
	23	#ifndef CONFIG_VIRT_CPU_ACCOUNTING
	24	#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
	25	#define ACCOUNT_CPU_USER_EXIT(ra, rb)
	26	#else
	27	#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
	28	beq 2f; /* if from kernel mode */ \
	29	BEGIN_FTR_SECTION; \
	30	mfspr ra,SPRN_PURR; /* get processor util. reg */ \
	31	END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
	32	BEGIN_FTR_SECTION; \
859deea9	33	MFTB(ra); /* or get TB if no PURR */ \
c6622f63	34	END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
859deea9	35	ld rb,PACA_STARTPURR(r13); \
c6622f63 PM	36	std ra,PACA_STARTPURR(r13); \
	37	subf rb,rb,ra; /* subtract start value */ \
	38	ld ra,PACA_USER_TIME(r13); \
	39	add ra,ra,rb; /* add on to user time */ \
	40	std ra,PACA_USER_TIME(r13); \
	41	2:
	42
	43	#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
	44	BEGIN_FTR_SECTION; \
	45	mfspr ra,SPRN_PURR; /* get processor util. reg */ \
	46	END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
	47	BEGIN_FTR_SECTION; \
859deea9	48	MFTB(ra); /* or get TB if no PURR */ \
c6622f63	49	END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
859deea9	50	ld rb,PACA_STARTPURR(r13); \
c6622f63 PM	51	std ra,PACA_STARTPURR(r13); \
	52	subf rb,rb,ra; /* subtract start value */ \
	53	ld ra,PACA_SYSTEM_TIME(r13); \
	54	add ra,ra,rb; /* add on to user time */ \
	55	std ra,PACA_SYSTEM_TIME(r13);
	56	#endif
	57
1da177e4 LT	58	/*
	59	* Macros for storing registers into and loading registers from
	60	* exception frames.
	61	*/
5f7c6907 KG	62	#ifdef __powerpc64__
	63	#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
	64	#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
	65	#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
	66	#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
	67	#else
1da177e4	68	#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
5f7c6907 KG	69	#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
	70	#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
	71	SAVE_10GPRS(22, base)
	72	#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
	73	REST_10GPRS(22, base)
	74	#endif
	75
	76
1da177e4 LT	77	#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
	78	#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
	79	#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
	80	#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
1da177e4 LT	81	#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
	82	#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
	83	#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
	84	#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
	85
1da177e4 LT	86	#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
	87	#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
	88	#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
	89	#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
	90	#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
	91	#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
	92	#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
	93	#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
	94	#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
	95	#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
	96	#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
	97	#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
	98
	99	#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
5f7c6907 KG	100	#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
	101	#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
	102	#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
	103	#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
	104	#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
1da177e4	105	#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
5f7c6907 KG	106	#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
	107	#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
	108	#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
	109	#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
	110	#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
1da177e4 LT	111
1da177e4 LT	112	#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
5f7c6907 KG	113	#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
	114	#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
	115	#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
	116	#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
	117	#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
1da177e4	118	#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
5f7c6907 KG	119	#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
	120	#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
	121	#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
	122	#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
	123	#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
	124
8c71632f ME	125	/* Macros to adjust thread priority for hardware multithreading */
	126	#define HMT_VERY_LOW or 31,31,31 # very low priority
	127	#define HMT_LOW or 1,1,1
	128	#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
	129	#define HMT_MEDIUM or 2,2,2
	130	#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
	131	#define HMT_HIGH or 3,3,3
5f7c6907 KG	132
	133	/* handle instructions that older assemblers may not know */
	134	#define RFCI .long 0x4c000066 /* rfci instruction */
	135	#define RFDI .long 0x4c00004e /* rfdi instruction */
	136	#define RFMCI .long 0x4c00004c /* rfmci instruction */
	137
88ced031	138	#ifdef __KERNEL__
40ef8cbc PM	139	#ifdef CONFIG_PPC64
	140
	141	#define XGLUE(a,b) a##b
	142	#define GLUE(a,b) XGLUE(a,b)
	143
	144	#define _GLOBAL(name) \
	145	.section ".text"; \
	146	.align 2 ; \
	147	.globl name; \
	148	.globl GLUE(.,name); \
	149	.section ".opd","aw"; \
	150	name: \
	151	.quad GLUE(.,name); \
	152	.quad .TOC.@tocbase; \
	153	.quad 0; \
	154	.previous; \
	155	.type GLUE(.,name),@function; \
	156	GLUE(.,name):
	157
fc68e869 SR	158	#define _INIT_GLOBAL(name) \
	159	.section ".text.init.refok"; \
	160	.align 2 ; \
	161	.globl name; \
	162	.globl GLUE(.,name); \
	163	.section ".opd","aw"; \
	164	name: \
	165	.quad GLUE(.,name); \
	166	.quad .TOC.@tocbase; \
	167	.quad 0; \
	168	.previous; \
	169	.type GLUE(.,name),@function; \
	170	GLUE(.,name):
	171
40ef8cbc PM	172	#define _KPROBE(name) \
	173	.section ".kprobes.text","a"; \
	174	.align 2 ; \
	175	.globl name; \
	176	.globl GLUE(.,name); \
	177	.section ".opd","aw"; \
	178	name: \
	179	.quad GLUE(.,name); \
	180	.quad .TOC.@tocbase; \
	181	.quad 0; \
	182	.previous; \
	183	.type GLUE(.,name),@function; \
	184	GLUE(.,name):
	185
	186	#define _STATIC(name) \
	187	.section ".text"; \
	188	.align 2 ; \
	189	.section ".opd","aw"; \
	190	name: \
	191	.quad GLUE(.,name); \
	192	.quad .TOC.@tocbase; \
	193	.quad 0; \
	194	.previous; \
	195	.type GLUE(.,name),@function; \
c40b91b5 SR	196	GLUE(.,name):
	197
	198	#define _INIT_STATIC(name) \
	199	.section ".text.init.refok"; \
	200	.align 2 ; \
	201	.section ".opd","aw"; \
	202	name: \
	203	.quad GLUE(.,name); \
	204	.quad .TOC.@tocbase; \
	205	.quad 0; \
	206	.previous; \
	207	.type GLUE(.,name),@function; \
40ef8cbc PM	208	GLUE(.,name):
	209
	210	#else /* 32-bit */
	211
748a7683 KG	212	#define _ENTRY(n) \
	213	.globl n; \
	214	n:
	215
40ef8cbc PM	216	#define _GLOBAL(n) \
	217	.text; \
	218	.stabs __stringify(n:F-1),N_FUN,0,0,n;\
	219	.globl n; \
	220	n:
	221
	222	#define _KPROBE(n) \
	223	.section ".kprobes.text","a"; \
	224	.globl n; \
	225	n:
	226
	227	#endif
	228
5f7c6907	229	/*
e58c3495 DG	230	* LOAD_REG_IMMEDIATE(rn, expr)
	231	* Loads the value of the constant expression 'expr' into register 'rn'
	232	* using immediate instructions only. Use this when it's important not
	233	* to reference other data (i.e. on ppc64 when the TOC pointer is not
	234	* valid).
5f7c6907	235	*
e58c3495 DG	236	* LOAD_REG_ADDR(rn, name)
	237	* Loads the address of label 'name' into register 'rn'. Use this when
	238	* you don't particularly need immediate instructions only, but you need
	239	* the whole address in one register (e.g. it's a structure address and
	240	* you want to access various offsets within it). On ppc32 this is
	241	* identical to LOAD_REG_IMMEDIATE.
	242	*
	243	* LOAD_REG_ADDRBASE(rn, name)
	244	* ADDROFF(name)
	245	* LOAD_REG_ADDRBASE loads part of the address of label 'name' into
	246	* register 'rn'. ADDROFF(name) returns the remainder of the address as
	247	* a constant expression. ADDROFF(name) is a signed expression < 16 bits
	248	* in size, so is suitable for use directly as an offset in load and store
	249	* instructions. Use this when loading/storing a single word or less as:
	250	* LOAD_REG_ADDRBASE(rX, name)
	251	* ld rY,ADDROFF(name)(rX)
5f7c6907 KG	252	*/
5f7c6907 KG	253	#ifdef __powerpc64__
e58c3495 DG	254	#define LOAD_REG_IMMEDIATE(reg,expr) \
	255	lis (reg),(expr)@highest; \
	256	ori (reg),(reg),(expr)@higher; \
	257	rldicr (reg),(reg),32,31; \
	258	oris (reg),(reg),(expr)@h; \
	259	ori (reg),(reg),(expr)@l;
	260
	261	#define LOAD_REG_ADDR(reg,name) \
	262	ld (reg),name@got(r2)
	263
	264	#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
	265	#define ADDROFF(name) 0
b85a046a	266
f78541dc PM	267	/* offsets for stack frame layout */
f78541dc PM	268	#define LRSAVE 16
b85a046a PM	269
b85a046a PM	270	#else /* 32-bit */
70620186	271
e58c3495 DG	272	#define LOAD_REG_IMMEDIATE(reg,expr) \
	273	lis (reg),(expr)@ha; \
	274	addi (reg),(reg),(expr)@l;
	275
	276	#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
b85a046a	277
e58c3495 DG	278	#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
e58c3495 DG	279	#define ADDROFF(name) name@l
b85a046a	280
f78541dc PM	281	/* offsets for stack frame layout */
f78541dc PM	282	#define LRSAVE 4
b85a046a	283
5f7c6907	284	#endif
1da177e4	285
5f7c6907	286	/* various errata or part fixups */
1da177e4 LT	287	#ifdef CONFIG_PPC601_SYNC_FIX
	288	#define SYNC \
	289	BEGIN_FTR_SECTION \
	290	sync; \
	291	isync; \
	292	END_FTR_SECTION_IFSET(CPU_FTR_601)
	293	#define SYNC_601 \
	294	BEGIN_FTR_SECTION \
	295	sync; \
	296	END_FTR_SECTION_IFSET(CPU_FTR_601)
	297	#define ISYNC_601 \
	298	BEGIN_FTR_SECTION \
	299	isync; \
	300	END_FTR_SECTION_IFSET(CPU_FTR_601)
	301	#else
	302	#define SYNC
	303	#define SYNC_601
	304	#define ISYNC_601
	305	#endif
	306
859deea9 BH	307	#ifdef CONFIG_PPC_CELL
	308	#define MFTB(dest) \
	309	90: mftb dest; \
	310	BEGIN_FTR_SECTION_NESTED(96); \
	311	cmpwi dest,0; \
	312	beq- 90b; \
	313	END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
	314	#else
	315	#define MFTB(dest) mftb dest
	316	#endif
5f7c6907	317
1da177e4 LT	318	#ifndef CONFIG_SMP
	319	#define TLBSYNC
	320	#else /* CONFIG_SMP */
	321	/* tlbsync is not implemented on 601 */
	322	#define TLBSYNC \
	323	BEGIN_FTR_SECTION \
	324	tlbsync; \
	325	sync; \
	326	END_FTR_SECTION_IFCLR(CPU_FTR_601)
	327	#endif
	328
5f7c6907	329
1da177e4 LT	330	/*
	331	* This instruction is not implemented on the PPC 603 or 601; however, on
	332	* the 403GCX and 405GP tlbia IS defined and tlbie is not.
	333	* All of these instructions exist in the 8xx, they have magical powers,
	334	* and they must be used.
	335	*/
	336
	337	#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
	338	#define tlbia \
	339	li r4,1024; \
	340	mtctr r4; \
	341	lis r4,KERNELBASE@h; \
	342	0: tlbie r4; \
	343	addi r4,r4,0x1000; \
	344	bdnz 0b
	345	#endif
	346
5f7c6907	347
5f7c6907 KG	348	#ifdef CONFIG_IBM440EP_ERR42
	349	#define PPC440EP_ERR42 isync
	350	#else
	351	#define PPC440EP_ERR42
	352	#endif
	353
	354
	355	#if defined(CONFIG_BOOKE)
6316222e PM	356	#define toreal(rd)
	357	#define fromreal(rd)
	358
1da177e4 LT	359	#define tophys(rd,rs) \
	360	addis rd,rs,0
	361
	362	#define tovirt(rd,rs) \
	363	addis rd,rs,0
	364
5f7c6907	365	#elif defined(CONFIG_PPC64)
6316222e PM	366	#define toreal(rd) /* we can access c000... in real mode */
	367	#define fromreal(rd)
	368
5f7c6907	369	#define tophys(rd,rs) \
6316222e	370	clrldi rd,rs,2
5f7c6907 KG	371
5f7c6907 KG	372	#define tovirt(rd,rs) \
6316222e PM	373	rotldi rd,rs,16; \
	374	ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
	375	rotldi rd,rd,48
5f7c6907	376	#else
1da177e4 LT	377	/*
	378	* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
	379	* physical base address of RAM at compile time.
	380	*/
6316222e PM	381	#define toreal(rd) tophys(rd,rd)
	382	#define fromreal(rd) tovirt(rd,rd)
	383
1da177e4 LT	384	#define tophys(rd,rs) \
	385	0: addis rd,rs,-KERNELBASE@h; \
	386	.section ".vtop_fixup","aw"; \
	387	.align 1; \
	388	.long 0b; \
	389	.previous
	390
	391	#define tovirt(rd,rs) \
	392	0: addis rd,rs,KERNELBASE@h; \
	393	.section ".ptov_fixup","aw"; \
	394	.align 1; \
	395	.long 0b; \
	396	.previous
5f7c6907	397	#endif
1da177e4	398
40ef8cbc PM	399	#ifdef CONFIG_PPC64
	400	#define RFI rfid
	401	#define MTMSRD(r) mtmsrd r
1da177e4 LT	402
	403	#else
	404	#define FIX_SRR1(ra, rb)
	405	#ifndef CONFIG_40x
	406	#define RFI rfi
	407	#else
	408	#define RFI rfi; b . /* Prevent prefetch past rfi */
	409	#endif
	410	#define MTMSRD(r) mtmsr r
	411	#define CLR_TOP32(r)
c9cf73ae MP	412	#endif
c9cf73ae MP	413
88ced031 AB	414	#endif /* __KERNEL__ */
88ced031 AB	415
1da177e4 LT	416	/* The boring bits... */
	417
	418	/* Condition Register Bit Fields */
	419
	420	#define cr0 0
	421	#define cr1 1
	422	#define cr2 2
	423	#define cr3 3
	424	#define cr4 4
	425	#define cr5 5
	426	#define cr6 6
	427	#define cr7 7
	428
	429
	430	/* General Purpose Registers (GPRs) */
	431
	432	#define r0 0
	433	#define r1 1
	434	#define r2 2
	435	#define r3 3
	436	#define r4 4
	437	#define r5 5
	438	#define r6 6
	439	#define r7 7
	440	#define r8 8
	441	#define r9 9
	442	#define r10 10
	443	#define r11 11
	444	#define r12 12
	445	#define r13 13
	446	#define r14 14
	447	#define r15 15
	448	#define r16 16
	449	#define r17 17
	450	#define r18 18
	451	#define r19 19
	452	#define r20 20
	453	#define r21 21
	454	#define r22 22
	455	#define r23 23
	456	#define r24 24
	457	#define r25 25
	458	#define r26 26
	459	#define r27 27
	460	#define r28 28
	461	#define r29 29
	462	#define r30 30
	463	#define r31 31
	464
	465
	466	/* Floating Point Registers (FPRs) */
	467
	468	#define fr0 0
	469	#define fr1 1
	470	#define fr2 2
	471	#define fr3 3
	472	#define fr4 4
	473	#define fr5 5
	474	#define fr6 6
	475	#define fr7 7
	476	#define fr8 8
	477	#define fr9 9
	478	#define fr10 10
	479	#define fr11 11
480	#define fr12 12
481	#define fr13 13
482	#define fr14 14
483	#define fr15 15
484	#define fr16 16
485	#define fr17 17
486	#define fr18 18
487	#define fr19 19
488	#define fr20 20
489	#define fr21 21
490	#define fr22 22
491	#define fr23 23
492	#define fr24 24
493	#define fr25 25
494	#define fr26 26
495	#define fr27 27
496	#define fr28 28
497	#define fr29 29
498	#define fr30 30
499	#define fr31 31
500
5f7c6907 KG	501	/* AltiVec Registers (VPRs) */
5f7c6907 KG	502
1da177e4 LT	503	#define vr0 0
	504	#define vr1 1
	505	#define vr2 2
	506	#define vr3 3
	507	#define vr4 4
	508	#define vr5 5
	509	#define vr6 6
	510	#define vr7 7
	511	#define vr8 8
	512	#define vr9 9
	513	#define vr10 10
	514	#define vr11 11
	515	#define vr12 12
	516	#define vr13 13
	517	#define vr14 14
	518	#define vr15 15
	519	#define vr16 16
	520	#define vr17 17
	521	#define vr18 18
	522	#define vr19 19
	523	#define vr20 20
	524	#define vr21 21
	525	#define vr22 22
	526	#define vr23 23
	527	#define vr24 24
	528	#define vr25 25
	529	#define vr26 26
	530	#define vr27 27
	531	#define vr28 28
	532	#define vr29 29
	533	#define vr30 30
	534	#define vr31 31
	535
5f7c6907 KG	536	/* SPE Registers (EVPRs) */
5f7c6907 KG	537
1da177e4 LT	538	#define evr0 0
	539	#define evr1 1
	540	#define evr2 2
	541	#define evr3 3
	542	#define evr4 4
	543	#define evr5 5
	544	#define evr6 6
	545	#define evr7 7
	546	#define evr8 8
	547	#define evr9 9
	548	#define evr10 10
	549	#define evr11 11
	550	#define evr12 12
	551	#define evr13 13
	552	#define evr14 14
	553	#define evr15 15
	554	#define evr16 16
	555	#define evr17 17
	556	#define evr18 18
	557	#define evr19 19
	558	#define evr20 20
	559	#define evr21 21
	560	#define evr22 22
	561	#define evr23 23
	562	#define evr24 24
	563	#define evr25 25
	564	#define evr26 26
	565	#define evr27 27
	566	#define evr28 28
	567	#define evr29 29
	568	#define evr30 30
	569	#define evr31 31
	570
	571	/* some stab codes */
	572	#define N_FUN 36
	573	#define N_RSYM 64
	574	#define N_SLINE 68
	575	#define N_SO 100
5f7c6907	576
5f7c6907 KG	577	#endif /* __ASSEMBLY__ */
	578
	579	#endif /* _ASM_POWERPC_PPC_ASM_H */