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f88df14b DG |
1 | #ifndef _ASM_POWERPC_PGTABLE_PPC64_H_ |
2 | #define _ASM_POWERPC_PGTABLE_PPC64_H_ | |
3 | /* | |
4 | * This file contains the functions and defines necessary to modify and use | |
5 | * the ppc64 hashed page table. | |
6 | */ | |
7 | ||
8 | #ifndef __ASSEMBLY__ | |
9 | #include <linux/stddef.h> | |
f88df14b | 10 | #include <asm/tlbflush.h> |
f88df14b DG |
11 | #endif /* __ASSEMBLY__ */ |
12 | ||
13 | #ifdef CONFIG_PPC_64K_PAGES | |
14 | #include <asm/pgtable-64k.h> | |
15 | #else | |
16 | #include <asm/pgtable-4k.h> | |
17 | #endif | |
18 | ||
19 | #define FIRST_USER_ADDRESS 0 | |
20 | ||
21 | /* | |
22 | * Size of EA range mapped by our pagetables. | |
23 | */ | |
24 | #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ | |
25 | PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) | |
3d5134ee | 26 | #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE) |
f88df14b DG |
27 | |
28 | #if TASK_SIZE_USER64 > PGTABLE_RANGE | |
29 | #error TASK_SIZE_USER64 exceeds pagetable range | |
30 | #endif | |
31 | ||
32 | #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT)) | |
33 | #error TASK_SIZE_USER64 exceeds user VSID range | |
34 | #endif | |
35 | ||
3d5134ee | 36 | |
f88df14b DG |
37 | /* |
38 | * Define the address range of the vmalloc VM area. | |
39 | */ | |
40 | #define VMALLOC_START ASM_CONST(0xD000000000000000) | |
3d5134ee | 41 | #define VMALLOC_SIZE (PGTABLE_RANGE >> 1) |
f88df14b DG |
42 | #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) |
43 | ||
44 | /* | |
3d5134ee BH |
45 | * Define the address ranges for MMIO and IO space : |
46 | * | |
47 | * ISA_IO_BASE = VMALLOC_END, 64K reserved area | |
48 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
49 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
f88df14b | 50 | */ |
3d5134ee BH |
51 | #define FULL_IO_SIZE 0x80000000ul |
52 | #define ISA_IO_BASE (VMALLOC_END) | |
53 | #define ISA_IO_END (VMALLOC_END + 0x10000ul) | |
54 | #define PHB_IO_BASE (ISA_IO_END) | |
55 | #define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE) | |
56 | #define IOREMAP_BASE (PHB_IO_END) | |
57 | #define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE) | |
f88df14b DG |
58 | |
59 | /* | |
60 | * Region IDs | |
61 | */ | |
62 | #define REGION_SHIFT 60UL | |
63 | #define REGION_MASK (0xfUL << REGION_SHIFT) | |
64 | #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) | |
65 | ||
66 | #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START)) | |
67 | #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET)) | |
68 | #define USER_REGION_ID (0UL) | |
69 | ||
70 | /* | |
71 | * Common bits in a linux-style PTE. These match the bits in the | |
72 | * (hardware-defined) PowerPC PTE as closely as possible. Additional | |
73 | * bits may be defined in pgtable-*.h | |
74 | */ | |
75 | #define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */ | |
76 | #define _PAGE_USER 0x0002 /* matches one of the PP bits */ | |
77 | #define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */ | |
78 | #define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */ | |
79 | #define _PAGE_GUARDED 0x0008 | |
80 | #define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */ | |
81 | #define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */ | |
82 | #define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */ | |
83 | #define _PAGE_DIRTY 0x0080 /* C: page changed */ | |
84 | #define _PAGE_ACCESSED 0x0100 /* R: page referenced */ | |
85 | #define _PAGE_RW 0x0200 /* software: user write access allowed */ | |
86 | #define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */ | |
87 | #define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ | |
88 | ||
89 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT) | |
90 | ||
91 | #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY) | |
92 | ||
93 | /* __pgprot defined in asm-powerpc/page.h */ | |
94 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) | |
95 | ||
96 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER) | |
97 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC) | |
98 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) | |
99 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | |
100 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) | |
101 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) | |
102 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE) | |
103 | #define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \ | |
104 | _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED) | |
105 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC) | |
106 | ||
107 | #define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE) | |
108 | #define HAVE_PAGE_AGP | |
109 | ||
110 | /* PTEIDX nibble */ | |
111 | #define _PTEIDX_SECONDARY 0x8 | |
112 | #define _PTEIDX_GROUP_IX 0x7 | |
113 | ||
114 | ||
115 | /* | |
116 | * POWER4 and newer have per page execute protection, older chips can only | |
117 | * do this on a segment (256MB) basis. | |
118 | * | |
119 | * Also, write permissions imply read permissions. | |
120 | * This is the closest we can get.. | |
121 | * | |
122 | * Note due to the way vm flags are laid out, the bits are XWR | |
123 | */ | |
124 | #define __P000 PAGE_NONE | |
125 | #define __P001 PAGE_READONLY | |
126 | #define __P010 PAGE_COPY | |
127 | #define __P011 PAGE_COPY | |
128 | #define __P100 PAGE_READONLY_X | |
129 | #define __P101 PAGE_READONLY_X | |
130 | #define __P110 PAGE_COPY_X | |
131 | #define __P111 PAGE_COPY_X | |
132 | ||
133 | #define __S000 PAGE_NONE | |
134 | #define __S001 PAGE_READONLY | |
135 | #define __S010 PAGE_SHARED | |
136 | #define __S011 PAGE_SHARED | |
137 | #define __S100 PAGE_READONLY_X | |
138 | #define __S101 PAGE_READONLY_X | |
139 | #define __S110 PAGE_SHARED_X | |
140 | #define __S111 PAGE_SHARED_X | |
141 | ||
f88df14b DG |
142 | #ifdef CONFIG_HUGETLB_PAGE |
143 | ||
144 | #define HAVE_ARCH_UNMAPPED_AREA | |
145 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
146 | ||
147 | #endif | |
148 | ||
149 | #ifndef __ASSEMBLY__ | |
150 | ||
151 | /* | |
152 | * Conversion functions: convert a page and protection to a page entry, | |
153 | * and a page entry and page directory to the page they refer to. | |
154 | * | |
155 | * mk_pte takes a (struct page *) as input | |
156 | */ | |
157 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
158 | ||
159 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
160 | { | |
161 | pte_t pte; | |
162 | ||
163 | ||
164 | pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot); | |
165 | return pte; | |
166 | } | |
167 | ||
168 | #define pte_modify(_pte, newprot) \ | |
169 | (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))) | |
170 | ||
171 | #define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0) | |
172 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) | |
173 | ||
174 | /* pte_clear moved to later in this file */ | |
175 | ||
176 | #define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT))) | |
177 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
178 | ||
179 | #define PMD_BAD_BITS (PTE_TABLE_SIZE-1) | |
180 | #define PUD_BAD_BITS (PMD_TABLE_SIZE-1) | |
181 | ||
182 | #define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval)) | |
183 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
184 | #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \ | |
185 | || (pmd_val(pmd) & PMD_BAD_BITS)) | |
186 | #define pmd_present(pmd) (pmd_val(pmd) != 0) | |
187 | #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0) | |
188 | #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS) | |
189 | #define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd)) | |
190 | ||
191 | #define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval)) | |
192 | #define pud_none(pud) (!pud_val(pud)) | |
193 | #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \ | |
194 | || (pud_val(pud) & PUD_BAD_BITS)) | |
195 | #define pud_present(pud) (pud_val(pud) != 0) | |
196 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0) | |
197 | #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS) | |
198 | #define pud_page(pud) virt_to_page(pud_page_vaddr(pud)) | |
199 | ||
200 | #define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);}) | |
201 | ||
202 | /* | |
203 | * Find an entry in a page-table-directory. We combine the address region | |
204 | * (the high order N bits) and the pgd portion of the address. | |
205 | */ | |
206 | /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */ | |
207 | #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff) | |
208 | ||
209 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
210 | ||
211 | #define pmd_offset(pudp,addr) \ | |
212 | (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) | |
213 | ||
214 | #define pte_offset_kernel(dir,addr) \ | |
215 | (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) | |
216 | ||
217 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
218 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) | |
219 | #define pte_unmap(pte) do { } while(0) | |
220 | #define pte_unmap_nested(pte) do { } while(0) | |
221 | ||
222 | /* to find an entry in a kernel page-table-directory */ | |
223 | /* This now only contains the vmalloc pages */ | |
224 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
225 | ||
226 | /* | |
227 | * The following only work if pte_present() is true. | |
228 | * Undefined behaviour if not.. | |
229 | */ | |
f88df14b | 230 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;} |
f88df14b DG |
231 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;} |
232 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;} | |
233 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;} | |
234 | ||
235 | static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } | |
236 | static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } | |
237 | ||
f88df14b DG |
238 | static inline pte_t pte_wrprotect(pte_t pte) { |
239 | pte_val(pte) &= ~(_PAGE_RW); return pte; } | |
240 | static inline pte_t pte_mkclean(pte_t pte) { | |
241 | pte_val(pte) &= ~(_PAGE_DIRTY); return pte; } | |
242 | static inline pte_t pte_mkold(pte_t pte) { | |
243 | pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } | |
f88df14b DG |
244 | static inline pte_t pte_mkwrite(pte_t pte) { |
245 | pte_val(pte) |= _PAGE_RW; return pte; } | |
246 | static inline pte_t pte_mkdirty(pte_t pte) { | |
247 | pte_val(pte) |= _PAGE_DIRTY; return pte; } | |
248 | static inline pte_t pte_mkyoung(pte_t pte) { | |
249 | pte_val(pte) |= _PAGE_ACCESSED; return pte; } | |
250 | static inline pte_t pte_mkhuge(pte_t pte) { | |
251 | return pte; } | |
252 | ||
253 | /* Atomic PTE updates */ | |
254 | static inline unsigned long pte_update(struct mm_struct *mm, | |
255 | unsigned long addr, | |
256 | pte_t *ptep, unsigned long clr, | |
257 | int huge) | |
258 | { | |
259 | unsigned long old, tmp; | |
260 | ||
261 | __asm__ __volatile__( | |
262 | "1: ldarx %0,0,%3 # pte_update\n\ | |
263 | andi. %1,%0,%6\n\ | |
264 | bne- 1b \n\ | |
265 | andc %1,%0,%4 \n\ | |
266 | stdcx. %1,0,%3 \n\ | |
267 | bne- 1b" | |
268 | : "=&r" (old), "=&r" (tmp), "=m" (*ptep) | |
269 | : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY) | |
270 | : "cc" ); | |
271 | ||
272 | if (old & _PAGE_HASHPTE) | |
273 | hpte_need_flush(mm, addr, ptep, old, huge); | |
274 | return old; | |
275 | } | |
276 | ||
277 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
278 | unsigned long addr, pte_t *ptep) | |
279 | { | |
280 | unsigned long old; | |
281 | ||
282 | if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) | |
283 | return 0; | |
284 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0); | |
285 | return (old & _PAGE_ACCESSED) != 0; | |
286 | } | |
287 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
288 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
289 | ({ \ | |
290 | int __r; \ | |
291 | __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ | |
292 | __r; \ | |
293 | }) | |
294 | ||
f88df14b DG |
295 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
296 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
297 | pte_t *ptep) | |
298 | { | |
299 | unsigned long old; | |
300 | ||
301 | if ((pte_val(*ptep) & _PAGE_RW) == 0) | |
302 | return; | |
303 | old = pte_update(mm, addr, ptep, _PAGE_RW, 0); | |
304 | } | |
305 | ||
306 | /* | |
307 | * We currently remove entries from the hashtable regardless of whether | |
308 | * the entry was young or dirty. The generic routines only flush if the | |
309 | * entry was young or dirty which is not good enough. | |
310 | * | |
311 | * We should be more intelligent about this but for the moment we override | |
312 | * these functions and force a tlb flush unconditionally | |
313 | */ | |
314 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
315 | #define ptep_clear_flush_young(__vma, __address, __ptep) \ | |
316 | ({ \ | |
317 | int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \ | |
318 | __ptep); \ | |
319 | __young; \ | |
320 | }) | |
321 | ||
f88df14b DG |
322 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
323 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
324 | unsigned long addr, pte_t *ptep) | |
325 | { | |
326 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0); | |
327 | return __pte(old); | |
328 | } | |
329 | ||
330 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
331 | pte_t * ptep) | |
332 | { | |
333 | pte_update(mm, addr, ptep, ~0UL, 0); | |
334 | } | |
335 | ||
336 | /* | |
337 | * set_pte stores a linux PTE into the linux page table. | |
338 | */ | |
339 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
340 | pte_t *ptep, pte_t pte) | |
341 | { | |
342 | if (pte_present(*ptep)) | |
343 | pte_clear(mm, addr, ptep); | |
344 | pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); | |
345 | *ptep = pte; | |
346 | } | |
347 | ||
348 | /* Set the dirty and/or accessed bits atomically in a linux PTE, this | |
349 | * function doesn't need to flush the hash entry | |
350 | */ | |
351 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
352 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) | |
353 | { | |
354 | unsigned long bits = pte_val(entry) & | |
355 | (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); | |
356 | unsigned long old, tmp; | |
357 | ||
358 | __asm__ __volatile__( | |
359 | "1: ldarx %0,0,%4\n\ | |
360 | andi. %1,%0,%6\n\ | |
361 | bne- 1b \n\ | |
362 | or %0,%3,%0\n\ | |
363 | stdcx. %0,0,%4\n\ | |
364 | bne- 1b" | |
365 | :"=&r" (old), "=&r" (tmp), "=m" (*ptep) | |
366 | :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) | |
367 | :"cc"); | |
368 | } | |
369 | #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ | |
8dab5241 BH |
370 | ({ \ |
371 | int __changed = !pte_same(*(__ptep), __entry); \ | |
372 | if (__changed) { \ | |
373 | __ptep_set_access_flags(__ptep, __entry, __dirty); \ | |
374 | flush_tlb_page_nohash(__vma, __address); \ | |
375 | } \ | |
376 | __changed; \ | |
377 | }) | |
f88df14b DG |
378 | |
379 | /* | |
380 | * Macro to mark a page protection value as "uncacheable". | |
381 | */ | |
382 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) | |
383 | ||
384 | struct file; | |
385 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
386 | unsigned long size, pgprot_t vma_prot); | |
387 | #define __HAVE_PHYS_MEM_ACCESS_PROT | |
388 | ||
389 | #define __HAVE_ARCH_PTE_SAME | |
390 | #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) | |
391 | ||
392 | #define pte_ERROR(e) \ | |
393 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | |
394 | #define pmd_ERROR(e) \ | |
395 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
396 | #define pgd_ERROR(e) \ | |
397 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
398 | ||
f88df14b DG |
399 | /* Encode and de-code a swap entry */ |
400 | #define __swp_type(entry) (((entry).val >> 1) & 0x3f) | |
401 | #define __swp_offset(entry) ((entry).val >> 8) | |
402 | #define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)}) | |
403 | #define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT}) | |
404 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT }) | |
405 | #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT) | |
406 | #define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE}) | |
407 | #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT) | |
408 | ||
f88df14b DG |
409 | void pgtable_cache_init(void); |
410 | ||
411 | /* | |
412 | * find_linux_pte returns the address of a linux pte for a given | |
413 | * effective address and directory. If not found, it returns zero. | |
414 | */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea) | |
415 | { | |
416 | pgd_t *pg; | |
417 | pud_t *pu; | |
418 | pmd_t *pm; | |
419 | pte_t *pt = NULL; | |
420 | ||
421 | pg = pgdir + pgd_index(ea); | |
422 | if (!pgd_none(*pg)) { | |
423 | pu = pud_offset(pg, ea); | |
424 | if (!pud_none(*pu)) { | |
425 | pm = pmd_offset(pu, ea); | |
426 | if (pmd_present(*pm)) | |
427 | pt = pte_offset_kernel(pm, ea); | |
428 | } | |
429 | } | |
430 | return pt; | |
431 | } | |
432 | ||
433 | #endif /* __ASSEMBLY__ */ | |
434 | ||
435 | #endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */ |