[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / pci.h

#ifndef __ASM_POWERPC_PCI_H
#define __ASM_POWERPC_PCI_H
#ifdef __KERNEL__

/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/types.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/dma-mapping.h>

#include <asm/machdep.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>

#include <asm-generic/pci-dma-compat.h>

#define PCIBIOS_MIN_IO		0x1000
#define PCIBIOS_MIN_MEM		0x10000000

struct pci_dev;

/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
#define IOBASE_BRIDGE_NUMBER	0
#define IOBASE_MEMORY		1
#define IOBASE_IO		2
#define IOBASE_ISA_IO		3
#define IOBASE_ISA_MEM		4

/*
 * Set this to 1 if you want the kernel to re-assign all PCI
 * bus numbers (don't do that on ppc64 yet !)
 */
#define pcibios_assign_all_busses()    	(ppc_pci_flags & \
					 PPC_PCI_REASSIGN_ALL_BUS)
#define pcibios_scan_all_fns(a, b)	0

static inline void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling */
}

static inline void pcibios_penalize_isa_irq(int irq, int active)
{
	/* We don't do dynamic PCI IRQ allocation */
}

#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	if (ppc_md.pci_get_legacy_ide_irq)
		return ppc_md.pci_get_legacy_ide_irq(dev, channel);
	return channel ? 15 : 14;
}

#ifdef CONFIG_PPC64

/*
 * We want to avoid touching the cacheline size or MWI bit.
 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
 * size in all cases) and hardware treats MWI the same as memory write.
 */
#define PCI_DISABLE_MWI

#ifdef CONFIG_PCI
extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
extern struct dma_mapping_ops *get_pci_dma_ops(void);

static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	unsigned long cacheline_size;
	u8 byte;

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	if (byte == 0)
		cacheline_size = 1024;
	else
		cacheline_size = (int) byte * 4;

	*strat = PCI_DMA_BURST_MULTIPLE;
	*strategy_parameter = cacheline_size;
}
#else	/* CONFIG_PCI */
#define set_pci_dma_ops(d)
#define get_pci_dma_ops()	NULL
#endif

#else /* 32-bit */

#ifdef CONFIG_PCI
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	*strat = PCI_DMA_BURST_INFINITY;
	*strategy_parameter = ~0UL;
}
#endif
#endif /* CONFIG_PPC64 */

extern int pci_domain_nr(struct pci_bus *bus);

/* Decide whether to display the domain number in /proc */
extern int pci_proc_domain(struct pci_bus *bus);


struct vm_area_struct;
/* Map a range of PCI memory or I/O space for a device into user space */
int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine);

/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
#define HAVE_PCI_MMAP	1

#if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
/*
 * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
 * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
 * so on are not nops.
 * and thus...
 */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
	dma_addr_t ADDR_NAME;
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
	__u32 LEN_NAME;
#define pci_unmap_addr(PTR, ADDR_NAME)			\
	((PTR)->ADDR_NAME)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
	(((PTR)->ADDR_NAME) = (VAL))
#define pci_unmap_len(PTR, LEN_NAME)			\
	((PTR)->LEN_NAME)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
	(((PTR)->LEN_NAME) = (VAL))

#else /* 32-bit && coherent */

/* pci_unmap_{page,single} is a nop so... */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
#define pci_unmap_len(PTR, LEN_NAME)		(0)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)

#endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */

#ifdef CONFIG_PPC64

/* The PCI address space does not equal the physical memory address
 * space (we have an IOMMU).  The IDE and SCSI device layers use
 * this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS	(0)

#else /* 32-bit */

/* The PCI address space does equal the physical memory
 * address space (no IOMMU).  The IDE and SCSI device layers use
 * this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS     (1)

#endif /* CONFIG_PPC64 */

extern void pcibios_resource_to_bus(struct pci_dev *dev,
			struct pci_bus_region *region,
			struct resource *res);

extern void pcibios_bus_to_resource(struct pci_dev *dev,
			struct resource *res,
			struct pci_bus_region *region);

static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
			struct resource *res)
{
	struct resource *root = NULL;

	if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;
	if (res->flags & IORESOURCE_MEM)
		root = &iomem_resource;

	return root;
}

extern void pcibios_setup_new_device(struct pci_dev *dev);

extern void pcibios_claim_one_bus(struct pci_bus *b);

extern void pcibios_resource_survey(void);

extern struct pci_controller *init_phb_dynamic(struct device_node *dn);

extern struct pci_dev *of_create_pci_dev(struct device_node *node,
					struct pci_bus *bus, int devfn);

extern void of_scan_pci_bridge(struct device_node *node,
				struct pci_dev *dev);

extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);

extern int pci_read_irq_line(struct pci_dev *dev);

struct file;
extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
					 unsigned long pfn,
					 unsigned long size,
					 pgprot_t prot);

#define HAVE_ARCH_PCI_RESOURCE_TO_USER
extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
				 const struct resource *rsrc,
				 resource_size_t *start, resource_size_t *end);

extern void pcibios_do_bus_setup(struct pci_bus *bus);
extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);

#endif	/* __KERNEL__ */
#endif /* __ASM_POWERPC_PCI_H */
Commit	Line	Data
f8ef2705 PM	1	#ifndef __ASM_POWERPC_PCI_H
f8ef2705 PM	2	#define __ASM_POWERPC_PCI_H
1da177e4 LT	3	#ifdef __KERNEL__
	4
	5	/*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
	15	#include <linux/dma-mapping.h>
	16
	17	#include <asm/machdep.h>
	18	#include <asm/scatterlist.h>
	19	#include <asm/io.h>
	20	#include <asm/prom.h>
f8ef2705	21	#include <asm/pci-bridge.h>
1da177e4 LT	22
	23	#include <asm-generic/pci-dma-compat.h>
	24
	25	#define PCIBIOS_MIN_IO 0x1000
	26	#define PCIBIOS_MIN_MEM 0x10000000
	27
	28	struct pci_dev;
	29
f8ef2705 PM	30	/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
	31	#define IOBASE_BRIDGE_NUMBER 0
	32	#define IOBASE_MEMORY 1
	33	#define IOBASE_IO 2
	34	#define IOBASE_ISA_IO 3
	35	#define IOBASE_ISA_MEM 4
	36
	37	/*
	38	* Set this to 1 if you want the kernel to re-assign all PCI
3fd94c6b	39	* bus numbers (don't do that on ppc64 yet !)
f8ef2705	40	*/
fc3fb71c BH	41	#define pcibios_assign_all_busses() (ppc_pci_flags & \
fc3fb71c BH	42	PPC_PCI_REASSIGN_ALL_BUS)
1da177e4	43	#define pcibios_scan_all_fns(a, b) 0
1da177e4 LT	44
	45	static inline void pcibios_set_master(struct pci_dev *dev)
	46	{
	47	/* No special bus mastering setup handling */
	48	}
	49
c9c3e457	50	static inline void pcibios_penalize_isa_irq(int irq, int active)
1da177e4 LT	51	{
	52	/* We don't do dynamic PCI IRQ allocation */
	53	}
	54
	55	#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
	56	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	57	{
	58	if (ppc_md.pci_get_legacy_ide_irq)
	59	return ppc_md.pci_get_legacy_ide_irq(dev, channel);
	60	return channel ? 15 : 14;
	61	}
	62
f8ef2705	63	#ifdef CONFIG_PPC64
edb2d97e MW	64
	65	/*
	66	* We want to avoid touching the cacheline size or MWI bit.
	67	* pSeries firmware sets the cacheline size (which is not the cpu cacheline
	68	* size in all cases) and hardware treats MWI the same as memory write.
	69	*/
	70	#define PCI_DISABLE_MWI
1da177e4	71
98747770	72	#ifdef CONFIG_PCI
98747770	73	extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
57190708	74	extern struct dma_mapping_ops *get_pci_dma_ops(void);
98747770	75
e24c2d96 DM	76	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	77	enum pci_dma_burst_strategy *strat,
	78	unsigned long *strategy_parameter)
	79	{
	80	unsigned long cacheline_size;
	81	u8 byte;
	82
	83	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	84	if (byte == 0)
	85	cacheline_size = 1024;
	86	else
	87	cacheline_size = (int) byte * 4;
	88
	89	*strat = PCI_DMA_BURST_MULTIPLE;
	90	*strategy_parameter = cacheline_size;
	91	}
98747770 SR	92	#else /* CONFIG_PCI */
98747770 SR	93	#define set_pci_dma_ops(d)
57190708	94	#define get_pci_dma_ops() NULL
bb4a61b6	95	#endif
e24c2d96	96
f8ef2705 PM	97	#else /* 32-bit */
	98
	99	#ifdef CONFIG_PCI
	100	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	101	enum pci_dma_burst_strategy *strat,
	102	unsigned long *strategy_parameter)
	103	{
	104	*strat = PCI_DMA_BURST_INFINITY;
	105	*strategy_parameter = ~0UL;
	106	}
	107	#endif
f8ef2705 PM	108	#endif /* CONFIG_PPC64 */
f8ef2705 PM	109
5516b540 KG	110	extern int pci_domain_nr(struct pci_bus *bus);
5516b540 KG	111
fa462f2d BH	112	/* Decide whether to display the domain number in /proc */
	113	extern int pci_proc_domain(struct pci_bus *bus);
	114
	115
1da177e4 LT	116	struct vm_area_struct;
	117	/* Map a range of PCI memory or I/O space for a device into user space */
	118	int pci_mmap_page_range(struct pci_dev pdev, struct vm_area_struct vma,
	119	enum pci_mmap_state mmap_state, int write_combine);
	120
	121	/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
	122	#define HAVE_PCI_MMAP 1
	123
1d4454e7 RD	124	#if defined(CONFIG_PPC64) \|\| defined(CONFIG_NOT_COHERENT_CACHE)
	125	/*
	126	* For 64-bit kernels, pci_unmap_{single,page} is not a nop.
	127	* For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
	128	* so on are not nops.
	129	* and thus...
	130	*/
1da177e4 LT	131	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
	132	dma_addr_t ADDR_NAME;
	133	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
	134	__u32 LEN_NAME;
	135	#define pci_unmap_addr(PTR, ADDR_NAME) \
	136	((PTR)->ADDR_NAME)
	137	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
	138	(((PTR)->ADDR_NAME) = (VAL))
	139	#define pci_unmap_len(PTR, LEN_NAME) \
	140	((PTR)->LEN_NAME)
	141	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
	142	(((PTR)->LEN_NAME) = (VAL))
	143
1d4454e7 RD	144	#else /* 32-bit && coherent */
	145
	146	/* pci_unmap_{page,single} is a nop so... */
	147	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
	148	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
	149	#define pci_unmap_addr(PTR, ADDR_NAME) (0)
	150	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	151	#define pci_unmap_len(PTR, LEN_NAME) (0)
	152	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	153
	154	#endif /* CONFIG_PPC64 \|\| CONFIG_NOT_COHERENT_CACHE */
	155
	156	#ifdef CONFIG_PPC64
	157
f8ef2705 PM	158	/* The PCI address space does not equal the physical memory address
f8ef2705 PM	159	* space (we have an IOMMU). The IDE and SCSI device layers use
1da177e4 LT	160	* this boolean for bounce buffer decisions.
	161	*/
	162	#define PCI_DMA_BUS_IS_PHYS (0)
f8ef2705 PM	163
	164	#else /* 32-bit */
	165
	166	/* The PCI address space does equal the physical memory
	167	* address space (no IOMMU). The IDE and SCSI device layers use
	168	* this boolean for bounce buffer decisions.
	169	*/
	170	#define PCI_DMA_BUS_IS_PHYS (1)
	171
f8ef2705	172	#endif /* CONFIG_PPC64 */
1d4454e7	173
f8ef2705 PM	174	extern void pcibios_resource_to_bus(struct pci_dev *dev,
f8ef2705 PM	175	struct pci_bus_region *region,
1da177e4 LT	176	struct resource *res);
1da177e4 LT	177
f8ef2705 PM	178	extern void pcibios_bus_to_resource(struct pci_dev *dev,
f8ef2705 PM	179	struct resource *res,
43c34735 DB	180	struct pci_bus_region *region);
43c34735 DB	181
f8ef2705 PM	182	static inline struct resource pcibios_select_root(struct pci_dev pdev,
f8ef2705 PM	183	struct resource *res)
085ae41f DM	184	{
	185	struct resource *root = NULL;
	186
	187	if (res->flags & IORESOURCE_IO)
	188	root = &ioport_resource;
	189	if (res->flags & IORESOURCE_MEM)
	190	root = &iomem_resource;
	191
	192	return root;
	193	}
	194
12d04eef BH	195	extern void pcibios_setup_new_device(struct pci_dev *dev);
12d04eef BH	196
facf0787 LV	197	extern void pcibios_claim_one_bus(struct pci_bus *b);
facf0787 LV	198
3fd94c6b BH	199	extern void pcibios_resource_survey(void);
3fd94c6b BH	200
1da177e4 LT	201	extern struct pci_controller init_phb_dynamic(struct device_node dn);
1da177e4 LT	202
ead83717 JR	203	extern struct pci_dev of_create_pci_dev(struct device_node node,
	204	struct pci_bus *bus, int devfn);
	205
	206	extern void of_scan_pci_bridge(struct device_node *node,
	207	struct pci_dev *dev);
	208
	209	extern void of_scan_bus(struct device_node node, struct pci_bus bus);
	210
1da177e4 LT	211	extern int pci_read_irq_line(struct pci_dev *dev);
1da177e4 LT	212
1da177e4 LT	213	struct file;
1da177e4 LT	214	extern pgprot_t pci_phys_mem_access_prot(struct file *file,
8b150478	215	unsigned long pfn,
1da177e4 LT	216	unsigned long size,
	217	pgprot_t prot);
	218
2311b1f2 ME	219	#define HAVE_ARCH_PCI_RESOURCE_TO_USER
	220	extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
	221	const struct resource *rsrc,
e31dd6e4	222	resource_size_t start, resource_size_t end);
1da177e4	223
bf5e2ba2 BH	224	extern void pcibios_do_bus_setup(struct pci_bus *bus);
	225	extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
	226
1da177e4	227	#endif /* __KERNEL__ */
f8ef2705	228	#endif /* __ASM_POWERPC_PCI_H */