[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>

struct device_node;

extern unsigned int ppc_pci_flags;
enum {
	/* Force re-assigning all resources (ignore firmware
	 * setup completely)
	 */
	PPC_PCI_REASSIGN_ALL_RSRC	= 0x00000001,

	/* Re-assign all bus numbers */
	PPC_PCI_REASSIGN_ALL_BUS	= 0x00000002,

	/* Do not try to assign, just use existing setup */
	PPC_PCI_PROBE_ONLY		= 0x00000004,

	/* Don't bother with ISA alignment unless the bridge has
	 * ISA forwarding enabled
	 */
	PPC_PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,

	/* Enable domain numbers in /proc */
	PPC_PCI_ENABLE_PROC_DOMAINS	= 0x00000010,
	/* ... except for domain 0 */
	PPC_PCI_COMPAT_DOMAIN_0		= 0x00000020,
};


/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
#ifndef CONFIG_PPC64
	int self_busno;
#endif

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
#ifndef CONFIG_PPC64
	resource_size_t pci_io_size;
#endif

	/* Some machines (PReP) have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;
#ifdef CONFIG_PPC64
	unsigned long pci_io_size;
#endif

	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

#ifndef CONFIG_PPC64
	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
	u32 indirect_type;
#endif	/* !CONFIG_PPC64 */
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	int global_number;		/* PCI domain number */
#ifdef CONFIG_PPC64
	unsigned long buid;
	unsigned long dma_window_base_cur;
	unsigned long dma_window_size;

	void *private_data;
#endif	/* CONFIG_PPC64 */
};

#ifndef CONFIG_PPC64

static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
{
	return bus->sysdata;
}

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* No specific ISA handling on ppc32 at this stage, it
	 * all goes through PCI
	 */
	return 0;
}

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose);
#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */

	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

#ifdef CONFIG_EEH
	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
	int	class_code;		/* pci device class */
	int	eeh_mode;		/* See eeh.h for possible EEH_MODEs */
	int	eeh_config_addr;
	int	eeh_pe_config_addr; /* new-style partition endpoint address */
	int	eeh_check_count;	/* # times driver ignored error */
	int	eeh_freeze_count;	/* # times this device froze up. */
	int	eeh_false_positives;	/* # times this device reported #ff's */
	u32	config_space[16];	/* saved PCI config space */
#endif
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct device_node *fetch_dev_dn(struct pci_dev *dev);

/* Get a device_node from a pci_dev.  This code must be fast except
 * in the case where the sysdata is incorrect and needs to be fixed
 * up (this will only happen once).
 * In this case the sysdata will have been inherited from a PCI host
 * bridge or a PCI-PCI bridge further up the tree, so it will point
 * to a valid struct pci_dn, just not the one we want.
 */
static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
{
	struct device_node *dn = dev->sysdata;
	struct pci_dn *pdn = dn->data;

	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
		return dn;	/* fast path.  sysdata is good */
	return fetch_dev_dn(dev);
}

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	if (bus->self)
		return pci_device_to_OF_node(bus->self);
	else
		return bus->sysdata; /* Must be root bus (PHB) */
}

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pcibios_add_pci_devices(struct pci_bus *bus);
extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);

extern int pcibios_remove_root_bus(struct pci_controller *phb);

static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
{
	struct device_node *busdn = bus->sysdata;

	BUG_ON(busdn == NULL);
	return PCI_DN(busdn)->phb;
}


extern void isa_bridge_find_early(struct pci_controller *hose);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* Check if address hits the reserved legacy IO range */
	unsigned long ea = (unsigned long)address;
	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
}

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

/* Return values for ppc_md.pci_probe_mode function */
#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);

#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
	return (unsigned long)-1;
}
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
	12	#include <linux/ioport.h>
	13
44ef3390 SR	14	struct device_node;
44ef3390 SR	15
fc3fb71c BH	16	extern unsigned int ppc_pci_flags;
	17	enum {
	18	/* Force re-assigning all resources (ignore firmware
	19	* setup completely)
	20	*/
	21	PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
	22
	23	/* Re-assign all bus numbers */
	24	PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
	25
	26	/* Do not try to assign, just use existing setup */
	27	PPC_PCI_PROBE_ONLY = 0x00000004,
	28
	29	/* Don't bother with ISA alignment unless the bridge has
	30	* ISA forwarding enabled
	31	*/
	32	PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
fa462f2d BH	33
	34	/* Enable domain numbers in /proc */
	35	PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
	36	/* ... except for domain 0 */
	37	PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
fc3fb71c BH	38	};
	39
	40
5531e41b KG	41	/*
	42	* Structure of a PCI controller (host bridge)
	43	*/
	44	struct pci_controller {
	45	struct pci_bus *bus;
a4c9e328	46	char is_dynamic;
7211991f SR	47	#ifdef CONFIG_PPC64
	48	int node;
	49	#endif
44ef3390	50	struct device_node *dn;
a4c9e328	51	struct list_head list_node;
5531e41b KG	52	struct device *parent;
	53
	54	int first_busno;
	55	int last_busno;
7211991f	56	#ifndef CONFIG_PPC64
5531e41b	57	int self_busno;
7211991f	58	#endif
5531e41b KG	59
5531e41b KG	60	void __iomem *io_base_virt;
7211991f SR	61	#ifdef CONFIG_PPC64
	62	void *io_base_alloc;
	63	#endif
5531e41b	64	resource_size_t io_base_phys;
13dccb9e BH	65	#ifndef CONFIG_PPC64
	66	resource_size_t pci_io_size;
	67	#endif
5531e41b KG	68
	69	/* Some machines (PReP) have a non 1:1 mapping of
	70	* the PCI memory space in the CPU bus space
	71	*/
	72	resource_size_t pci_mem_offset;
7211991f SR	73	#ifdef CONFIG_PPC64
	74	unsigned long pci_io_size;
	75	#endif
5531e41b KG	76
5531e41b KG	77	struct pci_ops *ops;
70fbb938 SR	78	unsigned int __iomem *cfg_addr;
70fbb938 SR	79	void __iomem *cfg_data;
5531e41b	80
7211991f	81	#ifndef CONFIG_PPC64
5531e41b KG	82	/*
	83	* Used for variants of PCI indirect handling and possible quirks:
	84	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	85	* EXT_REG - provides access to PCI-e extended registers
	86	* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	87	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	88	* to determine which bus number to match on when generating type0
	89	* config cycles
62c66c8e KG	90	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	91	* hanging if we don't have link and try to do config cycles to
	92	* anything but the PHB. Only allow talking to the PHB if this is
	93	* set.
2e56ff20	94	* BIG_ENDIAN - cfg_addr is a big endian register
5531e41b	95	*/
7cd1de6b SR	96	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	97	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	98	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	99	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	100	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5531e41b	101	u32 indirect_type;
7211991f	102	#endif /* !CONFIG_PPC64 */
5531e41b KG	103	/* Currently, we limit ourselves to 1 IO range and 3 mem
	104	* ranges since the common pci_bus structure can't handle more
	105	*/
	106	struct resource io_resource;
	107	struct resource mem_resources[3];
5516b540	108	int global_number; /* PCI domain number */
7211991f SR	109	#ifdef CONFIG_PPC64
	110	unsigned long buid;
	111	unsigned long dma_window_base_cur;
	112	unsigned long dma_window_size;
	113
	114	void *private_data;
	115	#endif /* CONFIG_PPC64 */
5531e41b KG	116	};
5531e41b KG	117
7211991f SR	118	#ifndef CONFIG_PPC64
7211991f SR	119
5531e41b KG	120	static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
	121	{
	122	return bus->sysdata;
	123	}
	124
6dfbde20 BH	125	static inline int isa_vaddr_is_ioport(void __iomem *address)
	126	{
	127	/* No specific ISA handling on ppc32 at this stage, it
	128	* all goes through PCI
	129	*/
	130	return 0;
	131	}
	132
5531e41b KG	133	/* These are used for config access before all the PCI probing
5531e41b KG	134	has been done. */
7cd1de6b SR	135	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	136	int dev_fn, int where, u8 *val);
	137	extern int early_read_config_word(struct pci_controller *hose, int bus,
	138	int dev_fn, int where, u16 *val);
	139	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	140	int dev_fn, int where, u32 *val);
	141	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	142	int dev_fn, int where, u8 val);
	143	extern int early_write_config_word(struct pci_controller *hose, int bus,
	144	int dev_fn, int where, u16 val);
	145	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	146	int dev_fn, int where, u32 val);
5531e41b	147
38805e5f KG	148	extern int early_find_capability(struct pci_controller *hose, int bus,
	149	int dev_fn, int cap);
	150
5531e41b	151	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	152	resource_size_t cfg_addr,
d94bad82 VB	153	resource_size_t cfg_data, u32 flags);
5531e41b	154	extern void setup_grackle(struct pci_controller *hose);
7cd1de6b	155	#else /* CONFIG_PPC64 */
1da177e4	156
1635317f PM	157	/*
	158	* PCI stuff, for nodes representing PCI devices, pointed to
	159	* by device_node->data.
	160	*/
1635317f PM	161	struct iommu_table;
	162
	163	struct pci_dn {
7684b40c	164	int busno; /* pci bus number */
7684b40c	165	int devfn; /* pci device and function number */
b5166cc2	166
c2e221e8 LV	167	struct pci_controller phb; / for pci devices */
c2e221e8 LV	168	struct iommu_table iommu_table; / for phb's or bridges */
c2e221e8 LV	169	struct device_node node; / back-pointer to the device_node */
	170
	171	int pci_ext_config_space; /* for pci devices */
	172
	173	#ifdef CONFIG_EEH
b6ed42a7	174	struct pci_dev pcidev; / back-pointer to the pci device */
86bcab49	175	int class_code; /* pci device class */
1635317f PM	176	int eeh_mode; /* See eeh.h for possible EEH_MODEs */
1635317f PM	177	int eeh_config_addr;
25e591f6	178	int eeh_pe_config_addr; /* new-style partition endpoint address */
7cd1de6b SR	179	int eeh_check_count; /* # times driver ignored error */
	180	int eeh_freeze_count; /* # times this device froze up. */
	181	int eeh_false_positives; /* # times this device reported #ff's */
1635317f	182	u32 config_space[16]; /* saved PCI config space */
c2e221e8	183	#endif
1635317f PM	184	};
	185
	186	/* Get the pointer to a device_node's pci_dn */
	187	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	188
7cd1de6b	189	extern struct device_node fetch_dev_dn(struct pci_dev dev);
1da177e4	190
1635317f PM	191	/* Get a device_node from a pci_dev. This code must be fast except
	192	* in the case where the sysdata is incorrect and needs to be fixed
	193	* up (this will only happen once).
	194	* In this case the sysdata will have been inherited from a PCI host
	195	* bridge or a PCI-PCI bridge further up the tree, so it will point
	196	* to a valid struct pci_dn, just not the one we want.
1da177e4 LT	197	*/
	198	static inline struct device_node pci_device_to_OF_node(struct pci_dev dev)
	199	{
	200	struct device_node *dn = dev->sysdata;
1635317f	201	struct pci_dn *pdn = dn->data;
1da177e4	202
1635317f	203	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
1da177e4	204	return dn; /* fast path. sysdata is good */
1635317f	205	return fetch_dev_dn(dev);
1da177e4 LT	206	}
1da177e4 LT	207
40ef8cbc PM	208	static inline int pci_device_from_OF_node(struct device_node *np,
	209	u8 bus, u8 devfn)
	210	{
	211	if (!PCI_DN(np))
	212	return -ENODEV;
	213	*bus = PCI_DN(np)->busno;
	214	*devfn = PCI_DN(np)->devfn;
	215	return 0;
	216	}
	217
1da177e4 LT	218	static inline struct device_node pci_bus_to_OF_node(struct pci_bus bus)
	219	{
	220	if (bus->self)
	221	return pci_device_to_OF_node(bus->self);
	222	else
	223	return bus->sysdata; /* Must be root bus (PHB) */
	224	}
	225
2bf6a8fa	226	/** Find the bus corresponding to the indicated device node */
7cd1de6b	227	extern struct pci_bus pcibios_find_pci_bus(struct device_node dn);
2bf6a8fa	228
2bf6a8fa	229	/** Remove all of the PCI devices under this bus */
7cd1de6b	230	extern void pcibios_remove_pci_devices(struct pci_bus *bus);
2bf6a8fa LV	231
2bf6a8fa LV	232	/** Discover new pci devices under this bus, and add them */
7cd1de6b	233	extern void pcibios_add_pci_devices(struct pci_bus *bus);
bf5e2ba2	234	extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
2bf6a8fa	235
1da177e4 LT	236	extern int pcibios_remove_root_bus(struct pci_controller *phb);
1da177e4 LT	237
1da177e4 LT	238	static inline struct pci_controller pci_bus_to_host(struct pci_bus bus)
	239	{
	240	struct device_node *busdn = bus->sysdata;
	241
	242	BUG_ON(busdn == NULL);
1635317f	243	return PCI_DN(busdn)->phb;
1da177e4 LT	244	}
1da177e4 LT	245
b5166cc2	246
3d5134ee BH	247	extern void isa_bridge_find_early(struct pci_controller *hose);
3d5134ee BH	248
6dfbde20 BH	249	static inline int isa_vaddr_is_ioport(void __iomem *address)
	250	{
	251	/* Check if address hits the reserved legacy IO range */
	252	unsigned long ea = (unsigned long)address;
	253	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
	254	}
	255
3d5134ee BH	256	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	257	extern int pcibios_map_io_space(struct pci_bus *bus);
	258
4267292b PM	259	/* Return values for ppc_md.pci_probe_mode function */
	260	#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
	261	#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
	262	#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
	263
357518fa AB	264	#ifdef CONFIG_NUMA
	265	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	266	#else
	267	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	268	#endif
	269
7cd1de6b	270	#endif /* CONFIG_PPC64 */
5531e41b KG	271
5531e41b KG	272	/* Get the PCI host controller for an OF device */
7cd1de6b SR	273	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	274	struct device_node* node);
5531e41b KG	275
5531e41b KG	276	/* Fill up host controller resources from the OF node */
7cd1de6b SR	277	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	278	struct device_node *dev, int primary);
5531e41b	279
5131d4d8	280	/* Allocate & free a PCI host bridge structure */
7cd1de6b	281	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8 BH	282	extern void pcibios_free_controller(struct pci_controller *phb);
5131d4d8 BH	283
5531e41b KG	284	#ifdef CONFIG_PCI
5531e41b KG	285	extern unsigned long pci_address_to_pio(phys_addr_t address);
6dfbde20	286	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b KG	287	#else
	288	static inline unsigned long pci_address_to_pio(phys_addr_t address)
	289	{
	290	return (unsigned long)-1;
	291	}
6dfbde20 BH	292	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	293	{
	294	return 0;
	295	}
7cd1de6b	296	#endif /* CONFIG_PCI */
5531e41b	297
7cd1de6b SR	298	#endif /* __KERNEL__ */
7cd1de6b SR	299	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */