[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / oprofile_impl.h

/*
 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * Based on alpha version.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
#define _ASM_POWERPC_OPROFILE_IMPL_H
#ifdef __KERNEL__

#define OP_MAX_COUNTER 8

/* Per-counter configuration as set via oprofilefs.  */
struct op_counter_config {
	unsigned long enabled;
	unsigned long event;
	unsigned long count;
	/* Classic doesn't support per-counter user/kernel selection */
	unsigned long kernel;
	unsigned long user;
	unsigned long unit_mask;
};

/* System-wide configuration as set via oprofilefs.  */
struct op_system_config {
#ifdef CONFIG_PPC64
	unsigned long mmcr0;
	unsigned long mmcr1;
	unsigned long mmcra;
#endif
	unsigned long enable_kernel;
	unsigned long enable_user;
#ifdef CONFIG_PPC64
	unsigned long backtrace_spinlocks;
#endif
};

/* Per-arch configuration */
struct op_powerpc_model {
	void (*reg_setup) (struct op_counter_config *,
			   struct op_system_config *,
			   int num_counters);
	void (*cpu_setup) (void *);
	void (*start) (struct op_counter_config *);
	void (*stop) (void);
	void (*handle_interrupt) (struct pt_regs *,
				  struct op_counter_config *);
	int num_counters;
};

extern struct op_powerpc_model op_model_fsl_booke;
extern struct op_powerpc_model op_model_rs64;
extern struct op_powerpc_model op_model_power4;
extern struct op_powerpc_model op_model_7450;

#ifndef CONFIG_FSL_BOOKE

/* All the classic PPC parts use these */
static inline unsigned int ctr_read(unsigned int i)
{
	switch(i) {
	case 0:
		return mfspr(SPRN_PMC1);
	case 1:
		return mfspr(SPRN_PMC2);
	case 2:
		return mfspr(SPRN_PMC3);
	case 3:
		return mfspr(SPRN_PMC4);
	case 4:
		return mfspr(SPRN_PMC5);
	case 5:
		return mfspr(SPRN_PMC6);

/* No PPC32 chip has more than 6 so far */
#ifdef CONFIG_PPC64
	case 6:
		return mfspr(SPRN_PMC7);
	case 7:
		return mfspr(SPRN_PMC8);
#endif
	default:
		return 0;
	}
}

static inline void ctr_write(unsigned int i, unsigned int val)
{
	switch(i) {
	case 0:
		mtspr(SPRN_PMC1, val);
		break;
	case 1:
		mtspr(SPRN_PMC2, val);
		break;
	case 2:
		mtspr(SPRN_PMC3, val);
		break;
	case 3:
		mtspr(SPRN_PMC4, val);
		break;
	case 4:
		mtspr(SPRN_PMC5, val);
		break;
	case 5:
		mtspr(SPRN_PMC6, val);
		break;

/* No PPC32 chip has more than 6, yet */
#ifdef CONFIG_PPC64
	case 6:
		mtspr(SPRN_PMC7, val);
		break;
	case 7:
		mtspr(SPRN_PMC8, val);
		break;
#endif
	default:
		break;
	}
}
#endif /* !CONFIG_FSL_BOOKE */

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
	3	*
	4	* Based on alpha version.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
654810ec SR	12	#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
654810ec SR	13	#define _ASM_POWERPC_OPROFILE_IMPL_H
88ced031	14	#ifdef __KERNEL__
1da177e4 LT	15
	16	#define OP_MAX_COUNTER 8
	17
	18	/* Per-counter configuration as set via oprofilefs. */
	19	struct op_counter_config {
1da177e4 LT	20	unsigned long enabled;
	21	unsigned long event;
	22	unsigned long count;
555d97ac	23	/* Classic doesn't support per-counter user/kernel selection */
1da177e4	24	unsigned long kernel;
1da177e4 LT	25	unsigned long user;
	26	unsigned long unit_mask;
	27	};
	28
	29	/* System-wide configuration as set via oprofilefs. */
	30	struct op_system_config {
555d97ac	31	#ifdef CONFIG_PPC64
1da177e4 LT	32	unsigned long mmcr0;
	33	unsigned long mmcr1;
	34	unsigned long mmcra;
654810ec	35	#endif
1da177e4 LT	36	unsigned long enable_kernel;
1da177e4 LT	37	unsigned long enable_user;
555d97ac	38	#ifdef CONFIG_PPC64
1da177e4	39	unsigned long backtrace_spinlocks;
654810ec	40	#endif
1da177e4 LT	41	};
	42
	43	/* Per-arch configuration */
a3e48c10	44	struct op_powerpc_model {
1da177e4 LT	45	void (reg_setup) (struct op_counter_config ,
	46	struct op_system_config *,
	47	int num_counters);
	48	void (cpu_setup) (void );
	49	void (start) (struct op_counter_config );
	50	void (*stop) (void);
	51	void (handle_interrupt) (struct pt_regs ,
	52	struct op_counter_config *);
	53	int num_counters;
	54	};
	55
555d97ac	56	extern struct op_powerpc_model op_model_fsl_booke;
a3e48c10 SR	57	extern struct op_powerpc_model op_model_rs64;
a3e48c10 SR	58	extern struct op_powerpc_model op_model_power4;
555d97ac	59	extern struct op_powerpc_model op_model_7450;
72533db0 AB	60
72533db0 AB	61	#ifndef CONFIG_FSL_BOOKE
555d97ac AF	62
555d97ac AF	63	/* All the classic PPC parts use these */
1da177e4 LT	64	static inline unsigned int ctr_read(unsigned int i)
	65	{
	66	switch(i) {
	67	case 0:
	68	return mfspr(SPRN_PMC1);
	69	case 1:
	70	return mfspr(SPRN_PMC2);
	71	case 2:
	72	return mfspr(SPRN_PMC3);
	73	case 3:
	74	return mfspr(SPRN_PMC4);
	75	case 4:
	76	return mfspr(SPRN_PMC5);
	77	case 5:
	78	return mfspr(SPRN_PMC6);
555d97ac AF	79
	80	/* No PPC32 chip has more than 6 so far */
	81	#ifdef CONFIG_PPC64
1da177e4 LT	82	case 6:
	83	return mfspr(SPRN_PMC7);
	84	case 7:
	85	return mfspr(SPRN_PMC8);
555d97ac	86	#endif
1da177e4 LT	87	default:
	88	return 0;
	89	}
	90	}
	91
	92	static inline void ctr_write(unsigned int i, unsigned int val)
	93	{
	94	switch(i) {
	95	case 0:
	96	mtspr(SPRN_PMC1, val);
	97	break;
	98	case 1:
	99	mtspr(SPRN_PMC2, val);
	100	break;
	101	case 2:
	102	mtspr(SPRN_PMC3, val);
	103	break;
	104	case 3:
	105	mtspr(SPRN_PMC4, val);
	106	break;
	107	case 4:
	108	mtspr(SPRN_PMC5, val);
	109	break;
	110	case 5:
	111	mtspr(SPRN_PMC6, val);
	112	break;
555d97ac AF	113
	114	/* No PPC32 chip has more than 6, yet */
	115	#ifdef CONFIG_PPC64
1da177e4 LT	116	case 6:
	117	mtspr(SPRN_PMC7, val);
	118	break;
	119	case 7:
	120	mtspr(SPRN_PMC8, val);
	121	break;
555d97ac	122	#endif
1da177e4 LT	123	default:
	124	break;
	125	}
	126	}
555d97ac	127	#endif /* !CONFIG_FSL_BOOKE */
1da177e4	128
88ced031	129	#endif /* __KERNEL__ */
654810ec	130	#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */