[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / mmu-40x.h

#ifndef _ASM_POWERPC_MMU_40X_H_
#define _ASM_POWERPC_MMU_40X_H_

/*
 * PPC40x support
 */

#define PPC40X_TLB_SIZE 64

/*
 * TLB entries are defined by a "high" tag portion and a "low" data
 * portion.  On all architectures, the data portion is 32-bits.
 *
 * TLB entries are managed entirely under software control by reading,
 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 * instructions.
 */

#define	TLB_LO          1
#define	TLB_HI          0

#define	TLB_DATA        TLB_LO
#define	TLB_TAG         TLB_HI

/* Tag portion */

#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
#define TLB_PAGESZ_MASK 0x00000380
#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
#define   PAGESZ_1K		0
#define   PAGESZ_4K             1
#define   PAGESZ_16K            2
#define   PAGESZ_64K            3
#define   PAGESZ_256K           4
#define   PAGESZ_1M             5
#define   PAGESZ_4M             6
#define   PAGESZ_16M            7
#define TLB_VALID       0x00000040      /* Entry is valid */

/* Data portion */

#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
#define TLB_PERM_MASK   0x00000300
#define TLB_EX          0x00000200      /* Instruction execution allowed */
#define TLB_WR          0x00000100      /* Writes permitted */
#define TLB_ZSEL_MASK   0x000000F0
#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
#define TLB_ATTR_MASK   0x0000000F
#define TLB_W           0x00000008      /* Caching is write-through */
#define TLB_I           0x00000004      /* Caching is inhibited */
#define TLB_M           0x00000002      /* Memory is coherent */
#define TLB_G           0x00000001      /* Memory is guarded from prefetch */

#ifndef __ASSEMBLY__

typedef unsigned long phys_addr_t;

typedef struct {
	unsigned long id;
	unsigned long vdso_base;
} mm_context_t;

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_POWERPC_MMU_40X_H_ */
Commit	Line	Data
4d922c8d JB	1	#ifndef _ASM_POWERPC_MMU_40X_H_
	2	#define _ASM_POWERPC_MMU_40X_H_
	3
	4	/*
	5	* PPC40x support
	6	*/
	7
	8	#define PPC40X_TLB_SIZE 64
	9
	10	/*
	11	* TLB entries are defined by a "high" tag portion and a "low" data
	12	* portion. On all architectures, the data portion is 32-bits.
	13	*
	14	* TLB entries are managed entirely under software control by reading,
	15	* writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
	16	* instructions.
	17	*/
	18
	19	#define TLB_LO 1
	20	#define TLB_HI 0
	21
	22	#define TLB_DATA TLB_LO
	23	#define TLB_TAG TLB_HI
	24
	25	/* Tag portion */
	26
	27	#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
	28	#define TLB_PAGESZ_MASK 0x00000380
	29	#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
	30	#define PAGESZ_1K 0
	31	#define PAGESZ_4K 1
	32	#define PAGESZ_16K 2
	33	#define PAGESZ_64K 3
	34	#define PAGESZ_256K 4
	35	#define PAGESZ_1M 5
	36	#define PAGESZ_4M 6
	37	#define PAGESZ_16M 7
	38	#define TLB_VALID 0x00000040 /* Entry is valid */
	39
	40	/* Data portion */
	41
	42	#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
	43	#define TLB_PERM_MASK 0x00000300
	44	#define TLB_EX 0x00000200 /* Instruction execution allowed */
	45	#define TLB_WR 0x00000100 /* Writes permitted */
	46	#define TLB_ZSEL_MASK 0x000000F0
	47	#define TLB_ZSEL(x) (((x) & 0xF) << 4)
	48	#define TLB_ATTR_MASK 0x0000000F
	49	#define TLB_W 0x00000008 /* Caching is write-through */
	50	#define TLB_I 0x00000004 /* Caching is inhibited */
	51	#define TLB_M 0x00000002 /* Memory is coherent */
	52	#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
	53
	54	#ifndef __ASSEMBLY__
	55
	56	typedef unsigned long phys_addr_t;
	57
	58	typedef struct {
	59	unsigned long id;
	60	unsigned long vdso_base;
	61	} mm_context_t;
	62
	63	#endif /* !__ASSEMBLY__ */
	64
65	#endif /* _ASM_POWERPC_MMU_40X_H_ */