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[POWERPC] pasemi: Add flag management functions to dma_lib
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / elf.h
CommitLineData
a99eb2ef
BB		 1#ifndef _ASM_POWERPC_ELF_H
2#define _ASM_POWERPC_ELF_H
1da177e4 3
88ced031 4#ifdef __KERNEL__
8c65b4a6 5#include <linux/sched.h> /* for task_struct */
dd02ec3a
DW		 6#include <asm/page.h>
7#include <asm/string.h>
88ced031
AB		 8#endif
9
1da177e4
LT		 10#include <asm/types.h>
11#include <asm/ptrace.h>
12#include <asm/cputable.h>
36d57ac4 13#include <asm/auxvec.h>
1da177e4
LT		 14
15/* PowerPC relocations defined by the ABIs */
16#define R_PPC_NONE 0
17#define R_PPC_ADDR32 1 /* 32bit absolute address */
18#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
19#define R_PPC_ADDR16 3 /* 16bit absolute address */
20#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
21#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
22#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
23#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
24#define R_PPC_ADDR14_BRTAKEN 8
25#define R_PPC_ADDR14_BRNTAKEN 9
26#define R_PPC_REL24 10 /* PC relative 26 bit */
27#define R_PPC_REL14 11 /* PC relative 16 bit */
28#define R_PPC_REL14_BRTAKEN 12
29#define R_PPC_REL14_BRNTAKEN 13
30#define R_PPC_GOT16 14
31#define R_PPC_GOT16_LO 15
32#define R_PPC_GOT16_HI 16
33#define R_PPC_GOT16_HA 17
34#define R_PPC_PLTREL24 18
35#define R_PPC_COPY 19
36#define R_PPC_GLOB_DAT 20
37#define R_PPC_JMP_SLOT 21
38#define R_PPC_RELATIVE 22
39#define R_PPC_LOCAL24PC 23
40#define R_PPC_UADDR32 24
41#define R_PPC_UADDR16 25
42#define R_PPC_REL32 26
43#define R_PPC_PLT32 27
44#define R_PPC_PLTREL32 28
45#define R_PPC_PLT16_LO 29
46#define R_PPC_PLT16_HI 30
47#define R_PPC_PLT16_HA 31
48#define R_PPC_SDAREL16 32
49#define R_PPC_SECTOFF 33
50#define R_PPC_SECTOFF_LO 34
51#define R_PPC_SECTOFF_HI 35
52#define R_PPC_SECTOFF_HA 36
53
54/* PowerPC relocations defined for the TLS access ABI. */
55#define R_PPC_TLS 67 /* none (sym+add)@tls */
56#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
57#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
58#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
59#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
60#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
61#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
62#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
63#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
64#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
65#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
66#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
67#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
68#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
69#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
70#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
71#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
72#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
73#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
74#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
75#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
76#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
77#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
78#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
79#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
80#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
81#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
82#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
83
a99eb2ef 84/* keep this the last entry. */
1da177e4
LT		 85#define R_PPC_NUM 95
86
87/*
88 * ELF register definitions..
89 *
90 * This program is free software; you can redistribute it and/or
91 * modify it under the terms of the GNU General Public License
92 * as published by the Free Software Foundation; either version
93 * 2 of the License, or (at your option) any later version.
94 */
1da177e4
LT		 95
96#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
97#define ELF_NFPREG 33 /* includes fpscr */
1da177e4
LT		 98
99typedef unsigned long elf_greg_t64;
100typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
101
102typedef unsigned int elf_greg_t32;
103typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
5f149cf0 104typedef elf_gregset_t32 compat_elf_gregset_t;
1da177e4
LT		 105
106/*
a99eb2ef 107 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
1da177e4 108 */
a99eb2ef
BB		 109#ifdef __powerpc64__
110# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
111# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
112# define ELF_GREG_TYPE elf_greg_t64
113#else
114# define ELF_NEVRREG 34 /* includes acc (as 2) */
115# define ELF_NVRREG 33 /* includes vscr */
116# define ELF_GREG_TYPE elf_greg_t32
117# define ELF_ARCH EM_PPC
118# define ELF_CLASS ELFCLASS32
119# define ELF_DATA ELFDATA2MSB
120#endif /* __powerpc64__ */
121
1da177e4
LT		 122#ifndef ELF_ARCH
123# define ELF_ARCH EM_PPC64
124# define ELF_CLASS ELFCLASS64
125# define ELF_DATA ELFDATA2MSB
126 typedef elf_greg_t64 elf_greg_t;
127 typedef elf_gregset_t64 elf_gregset_t;
1da177e4
LT		 128#else
129 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
130 typedef elf_greg_t32 elf_greg_t;
131 typedef elf_gregset_t32 elf_gregset_t;
a99eb2ef 132#endif /* ELF_ARCH */
1da177e4 133
a99eb2ef 134/* Floating point registers */
1da177e4
LT		 135typedef double elf_fpreg_t;
136typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
137
138/* Altivec registers */
139/*
140 * The entries with indexes 0-31 contain the corresponding vector registers.
141 * The entry with index 32 contains the vscr as the last word (offset 12)
142 * within the quadword. This allows the vscr to be stored as either a
143 * quadword (since it must be copied via a vector register to/from storage)
a99eb2ef
BB		 144 * or as a word.
145 *
146 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
1da177e4
LT		 147 * word (offset 0) within the quadword.
148 *
149 * This definition of the VMX state is compatible with the current PPC32
150 * ptrace interface. This allows signal handling and ptrace to use the same
151 * structures. This also simplifies the implementation of a bi-arch
152 * (combined (32- and 64-bit) gdb.
153 *
154 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
155 * vrsave along with vscr and so only uses 33 vectors for the register set
156 */
157typedef __vector128 elf_vrreg_t;
158typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
a99eb2ef 159#ifdef __powerpc64__
1da177e4 160typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
a99eb2ef 161#endif
1da177e4 162
dd02ec3a 163#ifdef __KERNEL__
1da177e4
LT		 164/*
165 * This is used to ensure we don't load something for the wrong architecture.
166 */
167#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
01e31dba 168#define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC)
1da177e4
LT		 169
170#define USE_ELF_CORE_DUMP
81970387 171#define CORE_DUMP_USE_REGSET
637a6ff6 172#define ELF_EXEC_PAGESIZE PAGE_SIZE
1da177e4
LT		 173
174/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
175 use of this is to invoke "./ld.so someprog" to test out a new version of
176 the loader. We need to make sure that it is out of the way of the program
177 that it will "exec", and that there is sufficient room for the brk. */
178
7e60d1b4 179#define ELF_ET_DYN_BASE (0x20000000)
1da177e4 180
5f149cf0
RM		 181/*
182 * Our registers are always unsigned longs, whether we're a 32 bit
183 * process or 64 bit, on either a 64 bit or 32 bit kernel.
184 *
185 * This macro relies on elf_regs[i] having the right type to truncate to,
186 * either u32 or u64. It defines the body of the elf_core_copy_regs
187 * function, either the native one with elf_gregset_t elf_regs or
188 * the 32-bit one with elf_gregset_t32 elf_regs.
189 */
190#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
191 int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
192 (size_t)ELF_NGREG); \
193 for (i = 0; i < nregs; i++) \
194 elf_regs[i] = ((unsigned long *) regs)[i]; \
195 memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
196
197/* Common routine for both 32-bit and 64-bit native processes */
a99eb2ef 198static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
5f149cf0 199 struct pt_regs *regs)
1da177e4 200{
5f149cf0 201 PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
1da177e4 202}
a99eb2ef 203#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
1da177e4
LT		 204
205static inline int dump_task_regs(struct task_struct *tsk,
206 elf_gregset_t *elf_regs)
207{
208 struct pt_regs *regs = tsk->thread.regs;
209 if (regs)
a99eb2ef 210 ppc_elf_core_copy_regs(*elf_regs, regs);
1da177e4
LT		 211
212 return 1;
213}
214#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
215
216extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
217#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
218
1f7d6668
MN		 219typedef elf_vrregset_t elf_fpxregset_t;
220
221#ifdef CONFIG_ALTIVEC
222extern int dump_task_altivec(struct task_struct *, elf_vrregset_t *vrregs);
223#define ELF_CORE_COPY_XFPREGS(tsk, regs) dump_task_altivec(tsk, regs)
224#define ELF_CORE_XFPREG_TYPE NT_PPC_VMX
225#endif
226
a99eb2ef 227#endif /* __KERNEL__ */
1da177e4 228
a99eb2ef 229/* ELF_HWCAP yields a mask that user programs can use to figure out what
1da177e4
LT		 230 instruction set this cpu supports. This could be done in userspace,
231 but it's not easy, and we've already done it here. */
a99eb2ef 232# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
1da177e4
LT		 233
234/* This yields a string that ld.so will use to load implementation
235 specific libraries for optimization. This is more specific in
80f15dc7 236 intent than poking at uname or /proc/cpuinfo. */
1da177e4 237
80f15dc7 238#define ELF_PLATFORM (cur_cpu_spec->platform)
1da177e4 239
80f15dc7
PM		 240#ifdef __powerpc64__
241# define ELF_PLAT_INIT(_r, load_addr) do { \
242 _r->gpr[2] = load_addr; \
243} while (0)
244#endif /* __powerpc64__ */
1da177e4 245
1da177e4 246#ifdef __KERNEL__
a99eb2ef
BB		 247
248#ifdef __powerpc64__
249# define SET_PERSONALITY(ex, ibcs2) \
1da177e4
LT		 250do { \
251 unsigned long new_flags = 0; \
252 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
253 new_flags = _TIF_32BIT; \
254 if ((current_thread_info()->flags & _TIF_32BIT) \
255 != new_flags) \
256 set_thread_flag(TIF_ABI_PENDING); \
257 else \
258 clear_thread_flag(TIF_ABI_PENDING); \
ce10d979 259 if (personality(current->personality) != PER_LINUX32) \
1da177e4
LT		 260 set_personality(PER_LINUX); \
261} while (0)
1da177e4
LT		 262/*
263 * An executable for which elf_read_implies_exec() returns TRUE will
a2f95a5a
AB		 264 * have the READ_IMPLIES_EXEC personality flag set automatically. This
265 * is only required to work around bugs in old 32bit toolchains. Since
266 * the 64bit ABI has never had these issues dont enable the workaround
267 * even if we have an executable stack.
1da177e4 268 */
a99eb2ef 269# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
a2f95a5a 270 (exec_stk != EXSTACK_DISABLE_X) : 0)
a99eb2ef
BB		 271#else
272# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
273#endif /* __powerpc64__ */
1da177e4 274
a99eb2ef 275#endif /* __KERNEL__ */
1da177e4 276
1da177e4
LT		 277extern int dcache_bsize;
278extern int icache_bsize;
279extern int ucache_bsize;
280
a7f290da
BH		 281/* vDSO has arch_setup_additional_pages */
282#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
1da177e4 283struct linux_binprm;
a7f290da
BH		 284extern int arch_setup_additional_pages(struct linux_binprm *bprm,
285 int executable_stack);
a99eb2ef 286#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
1da177e4
LT		 287
288/*
289 * The requirements here are:
290 * - keep the final alignment of sp (sp & 0xf)
291 * - make sure the 32-bit value at the first 16 byte aligned position of
292 * AUXV is greater than 16 for glibc compatibility.
293 * AT_IGNOREPPC is used for that.
294 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
295 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
4f9a58d7 296 * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
1da177e4
LT		 297 */
298#define ARCH_DLINFO \
299do { \
300 /* Handle glibc compatibility. */ \
301 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
302 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
303 /* Cache size items */ \
304 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
305 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
306 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
a5bba930 307 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base) \
a99eb2ef 308} while (0)
1da177e4
LT		 309
310/* PowerPC64 relocations defined by the ABIs */
311#define R_PPC64_NONE R_PPC_NONE
312#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
313#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
314#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
315#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
316#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
317#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
318#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
319#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
320#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
321#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
322#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
323#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
324#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
325#define R_PPC64_GOT16 R_PPC_GOT16
326#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
327#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
328#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
329
330#define R_PPC64_COPY R_PPC_COPY
331#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
332#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
333#define R_PPC64_RELATIVE R_PPC_RELATIVE
334
335#define R_PPC64_UADDR32 R_PPC_UADDR32
336#define R_PPC64_UADDR16 R_PPC_UADDR16
337#define R_PPC64_REL32 R_PPC_REL32
338#define R_PPC64_PLT32 R_PPC_PLT32
339#define R_PPC64_PLTREL32 R_PPC_PLTREL32
340#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
341#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
342#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
343
344#define R_PPC64_SECTOFF R_PPC_SECTOFF
345#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
346#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
347#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
348#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
349#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
350#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
351#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
352#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
353#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
354#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
355#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
356#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
357#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
358#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
359#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
360#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
361#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
362#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
363#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
364#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
365#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
366#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
367
368#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
369#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
370#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
371#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
372#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
373#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
374#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
375#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
376#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
377#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
378#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
379
380/* PowerPC64 relocations defined for the TLS access ABI. */
381#define R_PPC64_TLS 67 /* none (sym+add)@tls */
382#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
383#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
384#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
385#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
386#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
387#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
388#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
389#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
390#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
391#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
392#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
393#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
394#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
395#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
396#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
397#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
398#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
399#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
400#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
401#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
402#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
403#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
404#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
405#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
406#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
407#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
408#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
409#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
410#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
411#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
412#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
413#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
414#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
415#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
416#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
417#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
418#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
419#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
420#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
421
422/* Keep this the last entry. */
423#define R_PPC64_NUM 107
424
e055595d 425#ifdef CONFIG_SPU_BASE
bf1ab978
DGM		 426/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
427#define NT_SPU 1
428
bf1ab978 429#define ARCH_HAVE_EXTRA_ELF_NOTES
e5501492
ME		 430
431#endif /* CONFIG_SPU_BASE */
bf1ab978 432
a99eb2ef 433#endif /* _ASM_POWERPC_ELF_H */
kernel source for telekom puls (alcatel/mediatek)