[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-powerpc / cacheflush.h

/*
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */
#ifndef _ASM_POWERPC_CACHEFLUSH_H
#define _ASM_POWERPC_CACHEFLUSH_H

#ifdef __KERNEL__

#include <linux/mm.h>
#include <asm/cputable.h>

/*
 * No cache flushing is required when address mappings are changed,
 * because the caches on PowerPCs are physically addressed.
 */
#define flush_cache_all()			do { } while (0)
#define flush_cache_mm(mm)			do { } while (0)
#define flush_cache_dup_mm(mm)			do { } while (0)
#define flush_cache_range(vma, start, end)	do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
#define flush_icache_page(vma, page)		do { } while (0)
#define flush_cache_vmap(start, end)		do { } while (0)
#define flush_cache_vunmap(start, end)		do { } while (0)

extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping)		do { } while (0)
#define flush_dcache_mmap_unlock(mapping)	do { } while (0)

extern void __flush_icache_range(unsigned long, unsigned long);
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
	if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
		__flush_icache_range(start, stop);
}

extern void flush_icache_user_range(struct vm_area_struct *vma,
				    struct page *page, unsigned long addr,
				    int len);
extern void __flush_dcache_icache(void *page_va);
extern void flush_dcache_icache_page(struct page *page);
#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
extern void __flush_dcache_icache_phys(unsigned long physaddr);
#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */

extern void flush_dcache_range(unsigned long start, unsigned long stop);
#ifdef CONFIG_PPC32
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC64
extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
#endif

#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
	do { \
		memcpy(dst, src, len); \
		flush_icache_user_range(vma, page, vaddr, len); \
	} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy(dst, src, len)


#ifdef CONFIG_DEBUG_PAGEALLOC
/* internal debugging function */
void kernel_map_pages(struct page *page, int numpages, int enable);
#endif

#endif /* __KERNEL__ */

#endif /* _ASM_POWERPC_CACHEFLUSH_H */
Commit	Line	Data
26ef5c09 DG	1	/*
	2	* This program is free software; you can redistribute it and/or
	3	* modify it under the terms of the GNU General Public License
	4	* as published by the Free Software Foundation; either version
	5	* 2 of the License, or (at your option) any later version.
	6	*/
	7	#ifndef _ASM_POWERPC_CACHEFLUSH_H
	8	#define _ASM_POWERPC_CACHEFLUSH_H
	9
	10	#ifdef __KERNEL__
1da177e4 LT	11
	12	#include <linux/mm.h>
	13	#include <asm/cputable.h>
	14
	15	/*
26ef5c09 DG	16	* No cache flushing is required when address mappings are changed,
26ef5c09 DG	17	* because the caches on PowerPCs are physically addressed.
1da177e4 LT	18	*/
	19	#define flush_cache_all() do { } while (0)
	20	#define flush_cache_mm(mm) do { } while (0)
ec8c0446	21	#define flush_cache_dup_mm(mm) do { } while (0)
1da177e4 LT	22	#define flush_cache_range(vma, start, end) do { } while (0)
	23	#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
	24	#define flush_icache_page(vma, page) do { } while (0)
	25	#define flush_cache_vmap(start, end) do { } while (0)
	26	#define flush_cache_vunmap(start, end) do { } while (0)
	27
	28	extern void flush_dcache_page(struct page *page);
	29	#define flush_dcache_mmap_lock(mapping) do { } while (0)
	30	#define flush_dcache_mmap_unlock(mapping) do { } while (0)
	31
	32	extern void __flush_icache_range(unsigned long, unsigned long);
26ef5c09 DG	33	static inline void flush_icache_range(unsigned long start, unsigned long stop)
	34	{
	35	if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
	36	__flush_icache_range(start, stop);
	37	}
	38
1da177e4 LT	39	extern void flush_icache_user_range(struct vm_area_struct *vma,
	40	struct page *page, unsigned long addr,
	41	int len);
26ef5c09 DG	42	extern void __flush_dcache_icache(void *page_va);
	43	extern void flush_dcache_icache_page(struct page *page);
	44	#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
	45	extern void __flush_dcache_icache_phys(unsigned long physaddr);
	46	#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
1da177e4 LT	47
1da177e4 LT	48	extern void flush_dcache_range(unsigned long start, unsigned long stop);
26ef5c09 DG	49	#ifdef CONFIG_PPC32
	50	extern void clean_dcache_range(unsigned long start, unsigned long stop);
	51	extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
	52	#endif /* CONFIG_PPC32 */
	53	#ifdef CONFIG_PPC64
1da177e4	54	extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
26ef5c09 DG	55	extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
26ef5c09 DG	56	#endif
1da177e4 LT	57
1da177e4 LT	58	#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
26ef5c09 DG	59	do { \
	60	memcpy(dst, src, len); \
	61	flush_icache_user_range(vma, page, vaddr, len); \
	62	} while (0)
1da177e4 LT	63	#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	64	memcpy(dst, src, len)
	65
1da177e4	66
88df6e90 BH	67
	68	#ifdef CONFIG_DEBUG_PAGEALLOC
	69	/* internal debugging function */
	70	void kernel_map_pages(struct page *page, int numpages, int enable);
	71	#endif
	72
26ef5c09	73	#endif /* __KERNEL__ */
1da177e4	74
26ef5c09	75	#endif /* _ASM_POWERPC_CACHEFLUSH_H */