projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* ********************************************************************* |
| 2 | * SB1250 Board Support Package | |
| 42a3b4f2 | 3 | * |
| 1da177e4 | 4 | * SCD Constants and Macros File: sb1250_scd.h |
| 42a3b4f2 | 5 | * |
| 1da177e4 LT |
6 | * This module contains constants and macros useful for |
| 7 | * manipulating the System Control and Debug module on the 1250. | |
| 42a3b4f2 | 8 | * |
| 1da177e4 | 9 | * SB1250 specification level: User's manual 1/02/02 |
| 42a3b4f2 | 10 | * |
| 42a3b4f2 | 11 | ********************************************************************* |
| 1da177e4 LT |
12 | * |
| 13 | * Copyright 2000,2001,2002,2003 | |
| 14 | * Broadcom Corporation. All rights reserved. | |
| 42a3b4f2 RB |
15 | * |
| 16 | * This program is free software; you can redistribute it and/or | |
| 17 | * modify it under the terms of the GNU General Public License as | |
| 18 | * published by the Free Software Foundation; either version 2 of | |
| 1da177e4 LT |
19 | * the License, or (at your option) any later version. |
| 20 | * | |
| 21 | * This program is distributed in the hope that it will be useful, | |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 24 | * GNU General Public License for more details. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License | |
| 27 | * along with this program; if not, write to the Free Software | |
| 42a3b4f2 | 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 1da177e4 LT |
29 | * MA 02111-1307 USA |
| 30 | ********************************************************************* */ | |
| 31 | ||
| 32 | #ifndef _SB1250_SCD_H | |
| 33 | #define _SB1250_SCD_H | |
| 34 | ||
| 35 | #include "sb1250_defs.h" | |
| 36 | ||
| 37 | /* ********************************************************************* | |
| 38 | * System control/debug registers | |
| 39 | ********************************************************************* */ | |
| 40 | ||
| 41 | /* | |
| 42 | * System Revision Register (Table 4-1) | |
| 43 | */ | |
| 44 | ||
| 45 | #define M_SYS_RESERVED _SB_MAKEMASK(8,0) | |
| 46 | ||
| 47 | #define S_SYS_REVISION _SB_MAKE64(8) | |
| 48 | #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) | |
| 49 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) | |
| 50 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) | |
| 51 | ||
| 4cbf2bea AI |
52 | #define K_SYS_REVISION_BCM1250_PASS1 0x01 |
| 53 | ||
| 54 | #define K_SYS_REVISION_BCM1250_PASS2 0x03 | |
| 55 | #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ | |
| 56 | #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ | |
| 57 | #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ | |
| 58 | #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ | |
| 59 | #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ | |
| 60 | #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ | |
| 61 | #define K_SYS_REVISION_BCM1250_A9 0x08 | |
| 62 | #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 | |
| 63 | ||
| 64 | #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 | |
| 65 | #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 | |
| 66 | #define K_SYS_REVISION_BCM1250_B1 0x10 | |
| 67 | #define K_SYS_REVISION_BCM1250_B2 0x11 | |
| 68 | ||
| 69 | #define K_SYS_REVISION_BCM1250_C0 0x20 | |
| 70 | #define K_SYS_REVISION_BCM1250_C1 0x21 | |
| 71 | #define K_SYS_REVISION_BCM1250_C2 0x22 | |
| 72 | #define K_SYS_REVISION_BCM1250_C3 0x23 | |
| 1da177e4 | 73 | |
| 4cbf2bea | 74 | #if SIBYTE_HDR_FEATURE_CHIP(1250) |
| 1da177e4 LT |
75 | /* XXX: discourage people from using these constants. */ |
| 76 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 | |
| 77 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 | |
| 78 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 | |
| 79 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 | |
| 4cbf2bea | 80 | #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 |
| 1da177e4 LT |
81 | #endif /* 1250 */ |
| 82 | ||
| 4cbf2bea AI |
83 | #define K_SYS_REVISION_BCM112x_A1 0x20 |
| 84 | #define K_SYS_REVISION_BCM112x_A2 0x21 | |
| 85 | #define K_SYS_REVISION_BCM112x_A3 0x22 | |
| 86 | #define K_SYS_REVISION_BCM112x_A4 0x23 | |
| 87 | ||
| 88 | #define K_SYS_REVISION_BCM1480_S0 0x01 | |
| 89 | #define K_SYS_REVISION_BCM1480_A1 0x02 | |
| 90 | #define K_SYS_REVISION_BCM1480_A2 0x03 | |
| 91 | #define K_SYS_REVISION_BCM1480_A3 0x04 | |
| 92 | #define K_SYS_REVISION_BCM1480_B0 0x11 | |
| 93 | ||
| 94 | /*Cache size - 23:20 of revision register*/ | |
| 95 | #define S_SYS_L2C_SIZE _SB_MAKE64(20) | |
| 96 | #define M_SYS_L2C_SIZE _SB_MAKEMASK(4,S_SYS_L2C_SIZE) | |
| 97 | #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x,S_SYS_L2C_SIZE) | |
| 98 | #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x,S_SYS_L2C_SIZE,M_SYS_L2C_SIZE) | |
| 99 | ||
| 100 | #define K_SYS_L2C_SIZE_1MB 0 | |
| 101 | #define K_SYS_L2C_SIZE_512KB 5 | |
| 102 | #define K_SYS_L2C_SIZE_256KB 2 | |
| 103 | #define K_SYS_L2C_SIZE_128KB 1 | |
| 104 | ||
| 105 | #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB | |
| 106 | #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB | |
| 107 | #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB | |
| 108 | ||
| 109 | ||
| 110 | /* Number of CPU cores, bits 27:24 of revision register*/ | |
| 111 | #define S_SYS_NUM_CPUS _SB_MAKE64(24) | |
| 112 | #define M_SYS_NUM_CPUS _SB_MAKEMASK(4,S_SYS_NUM_CPUS) | |
| 113 | #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x,S_SYS_NUM_CPUS) | |
| 114 | #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x,S_SYS_NUM_CPUS,M_SYS_NUM_CPUS) | |
| 115 | ||
| 1da177e4 LT |
116 | |
| 117 | /* XXX: discourage people from using these constants. */ | |
| 118 | #define S_SYS_PART _SB_MAKE64(16) | |
| 119 | #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) | |
| 120 | #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) | |
| 121 | #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) | |
| 122 | ||
| 123 | /* XXX: discourage people from using these constants. */ | |
| 124 | #define K_SYS_PART_SB1250 0x1250 | |
| 125 | #define K_SYS_PART_BCM1120 0x1121 | |
| 126 | #define K_SYS_PART_BCM1125 0x1123 | |
| 127 | #define K_SYS_PART_BCM1125H 0x1124 | |
| 4cbf2bea AI |
128 | #define K_SYS_PART_BCM1122 0x1113 |
| 129 | ||
| 1da177e4 LT |
130 | |
| 131 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ | |
| 132 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) | |
| 133 | #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) | |
| 134 | #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) | |
| 135 | #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) | |
| 136 | ||
| 137 | #define K_SYS_SOC_TYPE_BCM1250 0x0 | |
| 138 | #define K_SYS_SOC_TYPE_BCM1120 0x1 | |
| 139 | #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ | |
| 140 | #define K_SYS_SOC_TYPE_BCM1125 0x3 | |
| 141 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 | |
| 142 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ | |
| 4cbf2bea AI |
143 | #define K_SYS_SOC_TYPE_BCM1x80 0x6 |
| 144 | #define K_SYS_SOC_TYPE_BCM1x55 0x7 | |
| 1da177e4 LT |
145 | |
| 146 | /* | |
| 147 | * Calculate correct SOC type given a copy of system revision register. | |
| 148 | * | |
| 149 | * (For the assembler version, sysrev and dest may be the same register. | |
| 150 | * Also, it clobbers AT.) | |
| 151 | */ | |
| 36396f3c | 152 | #ifdef __ASSEMBLY__ |
| 1da177e4 LT |
153 | #define SYS_SOC_TYPE(dest, sysrev) \ |
| 154 | .set push ; \ | |
| 155 | .set reorder ; \ | |
| 156 | dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ | |
| 157 | andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ | |
| 158 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ | |
| 159 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ | |
| 160 | b 992f ; \ | |
| 161 | 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ | |
| 162 | 992: \ | |
| 163 | .set pop | |
| 164 | #else | |
| 165 | #define SYS_SOC_TYPE(sysrev) \ | |
| 166 | ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ | |
| 167 | || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ | |
| 168 | ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) | |
| 169 | #endif | |
| 170 | ||
| 171 | #define S_SYS_WID _SB_MAKE64(32) | |
| 172 | #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) | |
| 173 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) | |
| 174 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) | |
| 175 | ||
| 4cbf2bea AI |
176 | /* |
| 177 | * System Manufacturing Register | |
| 178 | * Register: SCD_SYSTEM_MANUF | |
| 179 | */ | |
| 42a3b4f2 | 180 | |
| 4cbf2bea | 181 | #if SIBYTE_HDR_FEATURE_1250_112x |
| 1da177e4 LT |
182 | /* Wafer ID: bits 31:0 */ |
| 183 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) | |
| 184 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) | |
| 185 | #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) | |
| 186 | #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) | |
| 42a3b4f2 | 187 | |
| 1da177e4 LT |
188 | #define S_SYS_BIN _SB_MAKE64(32) |
| 189 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) | |
| 4cbf2bea AI |
190 | #define V_SYS_BIN(x) _SB_MAKEVALUE(x,S_SYS_BIN) |
| 191 | #define G_SYS_BIN(x) _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) | |
| 42a3b4f2 | 192 | |
| 1da177e4 LT |
193 | /* Wafer ID: bits 39:36 */ |
| 194 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) | |
| 195 | #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) | |
| 196 | #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) | |
| 197 | #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) | |
| 42a3b4f2 | 198 | |
| 1da177e4 LT |
199 | /* Wafer ID: bits 39:0 */ |
| 200 | #define S_SYS_WAFERID_300 _SB_MAKE64(0) | |
| 201 | #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) | |
| 202 | #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) | |
| 203 | #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) | |
| 42a3b4f2 | 204 | |
| 1da177e4 LT |
205 | #define S_SYS_XPOS _SB_MAKE64(40) |
| 206 | #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) | |
| 207 | #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) | |
| 208 | #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) | |
| 42a3b4f2 | 209 | |
| 1da177e4 LT |
210 | #define S_SYS_YPOS _SB_MAKE64(46) |
| 211 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) | |
| 212 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) | |
| 213 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) | |
| 4cbf2bea | 214 | #endif |
| 42a3b4f2 | 215 | |
| 1da177e4 LT |
216 | /* |
| 217 | * System Config Register (Table 4-2) | |
| 218 | * Register: SCD_SYSTEM_CFG | |
| 219 | */ | |
| 220 | ||
| 4cbf2bea | 221 | #if SIBYTE_HDR_FEATURE_1250_112x |
| 1da177e4 LT |
222 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) |
| 223 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) | |
| 224 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) | |
| 225 | #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) | |
| 226 | ||
| 227 | #define S_SYS_PLL_DIV _SB_MAKE64(7) | |
| 228 | #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) | |
| 229 | #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) | |
| 230 | #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) | |
| 231 | ||
| 232 | #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) | |
| 233 | #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) | |
| 234 | #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) | |
| 235 | #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) | |
| 236 | #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) | |
| 237 | ||
| 238 | #define S_SYS_BOOT_MODE _SB_MAKE64(17) | |
| 239 | #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) | |
| 240 | #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) | |
| 241 | #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) | |
| 242 | #define K_SYS_BOOT_MODE_ROM32 0 | |
| 243 | #define K_SYS_BOOT_MODE_ROM8 1 | |
| 244 | #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 | |
| 245 | #define K_SYS_BOOT_MODE_SMBUS_BIG 3 | |
| 246 | ||
| 247 | #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) | |
| 248 | #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) | |
| 249 | #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) | |
| 250 | #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) | |
| 251 | #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) | |
| 252 | #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) | |
| 253 | #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) | |
| 254 | ||
| 255 | #define S_SYS_CONFIG 26 | |
| 256 | #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) | |
| 257 | #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) | |
| 258 | #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) | |
| 259 | ||
| 260 | /* The following bits are writeable by JTAG only. */ | |
| 261 | ||
| 262 | #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) | |
| 263 | #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) | |
| 264 | ||
| 265 | #define S_SYS_CLKCOUNT 34 | |
| 266 | #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) | |
| 267 | #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) | |
| 268 | #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) | |
| 269 | ||
| 270 | #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) | |
| 271 | ||
| 272 | #define S_SYS_PLL_IREF 43 | |
| 273 | #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) | |
| 274 | ||
| 275 | #define S_SYS_PLL_VCO 45 | |
| 276 | #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) | |
| 277 | ||
| 278 | #define S_SYS_PLL_VREG 47 | |
| 279 | #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) | |
| 280 | ||
| 281 | #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) | |
| 282 | #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) | |
| 283 | #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) | |
| 284 | #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) | |
| 285 | #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) | |
| 286 | ||
| 287 | /* End of bits writable by JTAG only. */ | |
| 288 | ||
| 289 | #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) | |
| 290 | #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) | |
| 291 | ||
| 292 | #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) | |
| 293 | #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) | |
| 294 | ||
| 295 | #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) | |
| 296 | #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) | |
| 297 | #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) | |
| 298 | ||
| 299 | #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) | |
| 300 | #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) | |
| 301 | ||
| 302 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 303 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) | |
| 304 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 305 | ||
| 4cbf2bea AI |
306 | #endif |
| 307 | ||
| 1da177e4 LT |
308 | |
| 309 | /* | |
| 310 | * Mailbox Registers (Table 4-3) | |
| 311 | * Registers: SCD_MBOX_CPU_x | |
| 312 | */ | |
| 313 | ||
| 314 | #define S_MBOX_INT_3 0 | |
| 315 | #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) | |
| 316 | #define S_MBOX_INT_2 16 | |
| 317 | #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) | |
| 318 | #define S_MBOX_INT_1 32 | |
| 319 | #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) | |
| 320 | #define S_MBOX_INT_0 48 | |
| 321 | #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) | |
| 322 | ||
| 323 | /* | |
| 324 | * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) | |
| 325 | * Registers: SCD_WDOG_INIT_CNT_x | |
| 326 | */ | |
| 327 | ||
| 328 | #define V_SCD_WDOG_FREQ 1000000 | |
| 329 | ||
| 330 | #define S_SCD_WDOG_INIT 0 | |
| 331 | #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) | |
| 332 | ||
| 333 | #define S_SCD_WDOG_CNT 0 | |
| 334 | #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) | |
| 335 | ||
| 336 | #define S_SCD_WDOG_ENABLE 0 | |
| 337 | #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) | |
| 338 | ||
| 339 | #define S_SCD_WDOG_RESET_TYPE 2 | |
| 340 | #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) | |
| 341 | #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) | |
| 342 | #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) | |
| 343 | ||
| 344 | #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ | |
| 345 | #define K_SCD_WDOG_RESET_SOFT 1 | |
| 346 | #define K_SCD_WDOG_RESET_CPU0 3 | |
| 347 | #define K_SCD_WDOG_RESET_CPU1 5 | |
| 348 | #define K_SCD_WDOG_RESET_BOTH_CPUS 7 | |
| 349 | ||
| 350 | /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ | |
| 351 | #if SIBYTE_HDR_FEATURE(1250, PASS3) | |
| 352 | #define S_SCD_WDOG_HAS_RESET 8 | |
| 353 | #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) | |
| 354 | #endif | |
| 355 | ||
| 356 | ||
| 357 | /* | |
| 358 | * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) | |
| 359 | */ | |
| 360 | ||
| 361 | #define V_SCD_TIMER_FREQ 1000000 | |
| a77f1242 | 362 | #define V_SCD_TIMER_WIDTH 23 |
| 1da177e4 LT |
363 | |
| 364 | #define S_SCD_TIMER_INIT 0 | |
| a77f1242 | 365 | #define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT) |
| 1da177e4 LT |
366 | #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) |
| 367 | #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) | |
| 368 | ||
| 369 | #define S_SCD_TIMER_CNT 0 | |
| a77f1242 | 370 | #define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT) |
| 1da177e4 LT |
371 | #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) |
| 372 | #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) | |
| 373 | ||
| 374 | #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) | |
| 375 | #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) | |
| 376 | #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE | |
| 377 | ||
| 378 | /* | |
| 379 | * System Performance Counters | |
| 380 | */ | |
| 381 | ||
| 4cbf2bea | 382 | #if SIBYTE_HDR_FEATURE_1250_112x |
| 1da177e4 LT |
383 | #define S_SPC_CFG_SRC0 0 |
| 384 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) | |
| 385 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) | |
| 386 | #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) | |
| 387 | ||
| 388 | #define S_SPC_CFG_SRC1 8 | |
| 389 | #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) | |
| 390 | #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) | |
| 391 | #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) | |
| 392 | ||
| 393 | #define S_SPC_CFG_SRC2 16 | |
| 394 | #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) | |
| 395 | #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) | |
| 396 | #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) | |
| 397 | ||
| 398 | #define S_SPC_CFG_SRC3 24 | |
| 399 | #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) | |
| 400 | #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) | |
| 401 | #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) | |
| 402 | ||
| 403 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) | |
| 404 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) | |
| 4cbf2bea | 405 | #endif |
| 1da177e4 LT |
406 | |
| 407 | ||
| 408 | /* | |
| 409 | * Bus Watcher | |
| 410 | */ | |
| 411 | ||
| 412 | #define S_SCD_BERR_TID 8 | |
| 413 | #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) | |
| 414 | #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) | |
| 415 | #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) | |
| 416 | ||
| 417 | #define S_SCD_BERR_RID 18 | |
| 418 | #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) | |
| 419 | #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) | |
| 420 | #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) | |
| 421 | ||
| 422 | #define S_SCD_BERR_DCODE 22 | |
| 423 | #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) | |
| 424 | #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) | |
| 425 | #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) | |
| 426 | ||
| 427 | #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) | |
| 428 | ||
| 429 | ||
| 430 | #define S_SCD_L2ECC_CORR_D 0 | |
| 431 | #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) | |
| 432 | #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) | |
| 433 | #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) | |
| 434 | ||
| 435 | #define S_SCD_L2ECC_BAD_D 8 | |
| 436 | #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) | |
| 437 | #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) | |
| 438 | #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) | |
| 439 | ||
| 440 | #define S_SCD_L2ECC_CORR_T 16 | |
| 441 | #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) | |
| 442 | #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) | |
| 443 | #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) | |
| 444 | ||
| 445 | #define S_SCD_L2ECC_BAD_T 24 | |
| 446 | #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) | |
| 447 | #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) | |
| 448 | #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) | |
| 449 | ||
| 450 | #define S_SCD_MEM_ECC_CORR 0 | |
| 451 | #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) | |
| 452 | #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) | |
| 453 | #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) | |
| 454 | ||
| 455 | #define S_SCD_MEM_ECC_BAD 8 | |
| 456 | #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) | |
| 457 | #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) | |
| 458 | #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) | |
| 459 | ||
| 460 | #define S_SCD_MEM_BUSERR 16 | |
| 461 | #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) | |
| 462 | #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) | |
| 463 | #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) | |
| 464 | ||
| 465 | ||
| 466 | /* | |
| 467 | * Address Trap Registers | |
| 468 | */ | |
| 469 | ||
| 4cbf2bea | 470 | #if SIBYTE_HDR_FEATURE_1250_112x |
| 1da177e4 LT |
471 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) |
| 472 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) | |
| 473 | ||
| 474 | #define S_ATRAP_CFG_CNT 0 | |
| 475 | #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) | |
| 476 | #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) | |
| 477 | #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) | |
| 478 | ||
| 479 | #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) | |
| 480 | #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) | |
| 481 | #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) | |
| 482 | #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) | |
| 483 | #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) | |
| 484 | ||
| 485 | #define S_ATRAP_CFG_AGENTID 8 | |
| 486 | #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) | |
| 487 | #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) | |
| 488 | #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) | |
| 489 | ||
| 490 | #define K_BUS_AGENT_CPU0 0 | |
| 491 | #define K_BUS_AGENT_CPU1 1 | |
| 492 | #define K_BUS_AGENT_IOB0 2 | |
| 493 | #define K_BUS_AGENT_IOB1 3 | |
| 494 | #define K_BUS_AGENT_SCD 4 | |
| 1da177e4 LT |
495 | #define K_BUS_AGENT_L2C 6 |
| 496 | #define K_BUS_AGENT_MC 7 | |
| 497 | ||
| 498 | #define S_ATRAP_CFG_CATTR 12 | |
| 499 | #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) | |
| 500 | #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) | |
| 501 | #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) | |
| 502 | ||
| 503 | #define K_ATRAP_CFG_CATTR_IGNORE 0 | |
| 504 | #define K_ATRAP_CFG_CATTR_UNC 1 | |
| 505 | #define K_ATRAP_CFG_CATTR_CACHEABLE 2 | |
| 506 | #define K_ATRAP_CFG_CATTR_NONCOH 3 | |
| 507 | #define K_ATRAP_CFG_CATTR_COHERENT 4 | |
| 508 | #define K_ATRAP_CFG_CATTR_NOTUNC 5 | |
| 509 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 | |
| 510 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 | |
| 511 | ||
| 4cbf2bea AI |
512 | #endif /* 1250/112x */ |
| 513 | ||
| 1da177e4 LT |
514 | /* |
| 515 | * Trace Buffer Config register | |
| 516 | */ | |
| 517 | ||
| 4cbf2bea AI |
518 | #if SIBYTE_HDR_FEATURE_1250_112x |
| 519 | ||
| 1da177e4 LT |
520 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) |
| 521 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | |
| 522 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | |
| 523 | #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) | |
| 524 | #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) | |
| 525 | #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) | |
| 526 | #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) | |
| 527 | #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) | |
| 528 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 529 | #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) | |
| 530 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 531 | ||
| 532 | #define S_SCD_TRACE_CFG_CUR_ADDR 10 | |
| 533 | #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) | |
| 534 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) | |
| 535 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) | |
| 536 | ||
| 4cbf2bea AI |
537 | #endif /* 1250/112x */ |
| 538 | ||
| 1da177e4 LT |
539 | /* |
| 540 | * Trace Event registers | |
| 541 | */ | |
| 542 | ||
| 543 | #define S_SCD_TREVT_ADDR_MATCH 0 | |
| 544 | #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) | |
| 545 | #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) | |
| 546 | #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) | |
| 547 | ||
| 548 | #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) | |
| 549 | #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) | |
| 550 | #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) | |
| 551 | #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) | |
| 552 | #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) | |
| 553 | #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) | |
| 554 | #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) | |
| 555 | ||
| 556 | #define S_SCD_TREVT_REQID 12 | |
| 557 | #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) | |
| 558 | #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) | |
| 559 | #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) | |
| 560 | ||
| 561 | #define S_SCD_TREVT_RESPID 16 | |
| 562 | #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) | |
| 563 | #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) | |
| 564 | #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) | |
| 565 | ||
| 566 | #define S_SCD_TREVT_DATAID 20 | |
| 567 | #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) | |
| 568 | #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) | |
| 569 | #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) | |
| 570 | ||
| 571 | #define S_SCD_TREVT_COUNT 24 | |
| 572 | #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) | |
| 573 | #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) | |
| 574 | #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) | |
| 575 | ||
| 576 | /* | |
| 577 | * Trace Sequence registers | |
| 578 | */ | |
| 579 | ||
| 580 | #define S_SCD_TRSEQ_EVENT4 0 | |
| 581 | #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) | |
| 582 | #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) | |
| 583 | #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) | |
| 584 | ||
| 585 | #define S_SCD_TRSEQ_EVENT3 4 | |
| 586 | #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) | |
| 587 | #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) | |
| 588 | #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) | |
| 589 | ||
| 590 | #define S_SCD_TRSEQ_EVENT2 8 | |
| 591 | #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) | |
| 592 | #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) | |
| 593 | #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) | |
| 594 | ||
| 595 | #define S_SCD_TRSEQ_EVENT1 12 | |
| 596 | #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) | |
| 597 | #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) | |
| 598 | #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) | |
| 599 | ||
| 600 | #define K_SCD_TRSEQ_E0 0 | |
| 601 | #define K_SCD_TRSEQ_E1 1 | |
| 602 | #define K_SCD_TRSEQ_E2 2 | |
| 603 | #define K_SCD_TRSEQ_E3 3 | |
| 604 | #define K_SCD_TRSEQ_E0_E1 4 | |
| 605 | #define K_SCD_TRSEQ_E1_E2 5 | |
| 606 | #define K_SCD_TRSEQ_E2_E3 6 | |
| 607 | #define K_SCD_TRSEQ_E0_E1_E2 7 | |
| 608 | #define K_SCD_TRSEQ_E0_E1_E2_E3 8 | |
| 609 | #define K_SCD_TRSEQ_E0E1 9 | |
| 610 | #define K_SCD_TRSEQ_E0E1E2 10 | |
| 611 | #define K_SCD_TRSEQ_E0E1E2E3 11 | |
| 612 | #define K_SCD_TRSEQ_E0E1_E2 12 | |
| 613 | #define K_SCD_TRSEQ_E0E1_E2E3 13 | |
| 614 | #define K_SCD_TRSEQ_E0E1_E2_E3 14 | |
| 615 | #define K_SCD_TRSEQ_IGNORED 15 | |
| 616 | ||
| 617 | #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ | |
| 618 | V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ | |
| 619 | V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ | |
| 620 | V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) | |
| 621 | ||
| 622 | #define S_SCD_TRSEQ_FUNCTION 16 | |
| 623 | #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) | |
| 624 | #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) | |
| 625 | #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) | |
| 626 | ||
| 627 | #define K_SCD_TRSEQ_FUNC_NOP 0 | |
| 628 | #define K_SCD_TRSEQ_FUNC_START 1 | |
| 629 | #define K_SCD_TRSEQ_FUNC_STOP 2 | |
| 630 | #define K_SCD_TRSEQ_FUNC_FREEZE 3 | |
| 631 | ||
| 632 | #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) | |
| 633 | #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) | |
| 634 | #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) | |
| 635 | #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) | |
| 636 | ||
| 637 | #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) | |
| 638 | #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) | |
| 639 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) | |
| 640 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) | |
| 641 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) | |
| 4cbf2bea AI |
642 | #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) |
| 643 | #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) | |
| 1da177e4 LT |
644 | |
| 645 | #endif |