[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-mips / gic.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 *
 * GIC Register Definitions
 *
 */
#ifndef _ASM_GICREGS_H
#define _ASM_GICREGS_H

#undef	GICISBYTELITTLEENDIAN
#define GICISWORDLITTLEENDIAN

/* Constants */
#define GIC_POL_POS			1
#define GIC_POL_NEG			0
#define GIC_TRIG_EDGE			1
#define GIC_TRIG_LEVEL			0

#define GIC_NUM_INTRS			32

#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr)		(*(volatile unsigned int *) (addr))
#define REG(base, offs)		REG32((unsigned int)(base) + offs##_##OFS)
#define REGP(base, phys)	REG32((unsigned int)(base) + (phys))

/* Accessors */
#define GIC_REG(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ADDR(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset)

#define GIC_ABS_REG(segment, offset) \
       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ABS_ADDR(segment, offset) \
       (_gic_base + segment##_##SECTION_OFS + offset)

#ifdef GICISBYTELITTLEENDIAN
#define GICREAD(reg, data)	(data) = (reg), (data) = le32_to_cpu(data)
#define GICWRITE(reg, data)	(reg) = cpu_to_le32(data)
#define GICBIS(reg, bits)			\
	({unsigned int data;			\
		GICREAD(reg, data);		\
		data |= bits;			\
		GICWRITE(reg, data);		\
	})

#else
#define GICREAD(reg, data)	(data) = (reg)
#define GICWRITE(reg, data)	(reg) = (data)
#define GICBIS(reg, bits)	(reg) |= (bits)
#endif


/* GIC Address Space */
#define SHARED_SECTION_OFS		0x0000
#define SHARED_SECTION_SIZE		0x8000
#define VPE_LOCAL_SECTION_OFS		0x8000
#define VPE_LOCAL_SECTION_SIZE		0x4000
#define VPE_OTHER_SECTION_OFS		0xc000
#define VPE_OTHER_SECTION_SIZE		0x4000
#define USM_VISIBLE_SECTION_OFS		0x10000
#define USM_VISIBLE_SECTION_SIZE	0x10000

/* Register Map for Shared Section */
#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)

#define	GIC_SH_CONFIG_OFS		0x0000

/* Shared Global Counter */
#define GIC_SH_COUNTER_31_00_OFS	0x0010
#define GIC_SH_COUNTER_63_32_OFS	0x0014

/* Interrupt Polarity */
#define GIC_SH_POL_31_0_OFS		0x0100
#define GIC_SH_POL_63_32_OFS		0x0104
#define GIC_SH_POL_95_64_OFS		0x0108
#define GIC_SH_POL_127_96_OFS		0x010c
#define GIC_SH_POL_159_128_OFS		0x0110
#define GIC_SH_POL_191_160_OFS		0x0114
#define GIC_SH_POL_223_192_OFS		0x0118
#define GIC_SH_POL_255_224_OFS		0x011c

/* Edge/Level Triggering */
#define GIC_SH_TRIG_31_0_OFS		0x0180
#define GIC_SH_TRIG_63_32_OFS		0x0184
#define GIC_SH_TRIG_95_64_OFS		0x0188
#define GIC_SH_TRIG_127_96_OFS		0x018c
#define GIC_SH_TRIG_159_128_OFS		0x0190
#define GIC_SH_TRIG_191_160_OFS		0x0194
#define GIC_SH_TRIG_223_192_OFS		0x0198
#define GIC_SH_TRIG_255_224_OFS		0x019c

/* Dual Edge Triggering */
#define GIC_SH_DUAL_31_0_OFS		0x0200
#define GIC_SH_DUAL_63_32_OFS		0x0204
#define GIC_SH_DUAL_95_64_OFS		0x0208
#define GIC_SH_DUAL_127_96_OFS		0x020c
#define GIC_SH_DUAL_159_128_OFS		0x0210
#define GIC_SH_DUAL_191_160_OFS		0x0214
#define GIC_SH_DUAL_223_192_OFS		0x0218
#define GIC_SH_DUAL_255_224_OFS		0x021c

/* Set/Clear corresponding bit in Edge Detect Register */
#define GIC_SH_WEDGE_OFS		0x0280

/* Reset Mask - Disables Interrupt */
#define GIC_SH_RMASK_31_0_OFS		0x0300
#define GIC_SH_RMASK_63_32_OFS		0x0304
#define GIC_SH_RMASK_95_64_OFS		0x0308
#define GIC_SH_RMASK_127_96_OFS		0x030c
#define GIC_SH_RMASK_159_128_OFS	0x0310
#define GIC_SH_RMASK_191_160_OFS	0x0314
#define GIC_SH_RMASK_223_192_OFS	0x0318
#define GIC_SH_RMASK_255_224_OFS	0x031c

/* Set Mask (WO) - Enables Interrupt */
#define GIC_SH_SMASK_31_0_OFS		0x0380
#define GIC_SH_SMASK_63_32_OFS		0x0384
#define GIC_SH_SMASK_95_64_OFS		0x0388
#define GIC_SH_SMASK_127_96_OFS		0x038c
#define GIC_SH_SMASK_159_128_OFS	0x0390
#define GIC_SH_SMASK_191_160_OFS	0x0394
#define GIC_SH_SMASK_223_192_OFS	0x0398
#define GIC_SH_SMASK_255_224_OFS	0x039c

/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
#define GIC_SH_MASK_31_0_OFS		0x0400
#define GIC_SH_MASK_63_32_OFS		0x0404
#define GIC_SH_MASK_95_64_OFS		0x0408
#define GIC_SH_MASK_127_96_OFS		0x040c
#define GIC_SH_MASK_159_128_OFS		0x0410
#define GIC_SH_MASK_191_160_OFS		0x0414
#define GIC_SH_MASK_223_192_OFS		0x0418
#define GIC_SH_MASK_255_224_OFS		0x041c

/* Pending Global Interrupts (RO) */
#define GIC_SH_PEND_31_0_OFS		0x0480
#define GIC_SH_PEND_63_32_OFS		0x0484
#define GIC_SH_PEND_95_64_OFS		0x0488
#define GIC_SH_PEND_127_96_OFS		0x048c
#define GIC_SH_PEND_159_128_OFS		0x0490
#define GIC_SH_PEND_191_160_OFS		0x0494
#define GIC_SH_PEND_223_192_OFS		0x0498
#define GIC_SH_PEND_255_224_OFS		0x049c

#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS	0x0500

/* Maps Interrupt X to a Pin */
#define GIC_SH_MAP_TO_PIN(intr) \
	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))

#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS	0x2000

/* Maps Interrupt X to a VPE */
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))

/* Polarity : Reset Value is always 0 */
#define GIC_SH_SET_POLARITY_OFS		0x0100
#define GIC_SET_POLARITY(intr, pol) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))

/* Triggering : Reset Value is always 0 */
#define GIC_SH_SET_TRIGGER_OFS		0x0180
#define GIC_SET_TRIGGER(intr, trig) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))

/* Mask manipulation */
#define GIC_SH_SMASK_OFS		0x0380
#define GIC_SET_INTR_MASK(intr, val) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))

#define GIC_SH_RMASK_OFS		0x0300
#define GIC_CLR_INTR_MASK(intr, val) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))

/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS			0x0000
#define GIC_VPE_PEND_OFS		0x0004
#define GIC_VPE_MASK_OFS		0x0008
#define GIC_VPE_RMASK_OFS		0x000c
#define GIC_VPE_SMASK_OFS		0x0010
#define GIC_VPE_WD_MAP_OFS		0x0040
#define GIC_VPE_COMPARE_MAP_OFS		0x0044
#define GIC_VPE_TIMER_MAP_OFS		0x0048
#define GIC_VPE_PERFCTR_MAP_OFS		0x0050
#define GIC_VPE_SWINT0_MAP_OFS		0x0054
#define GIC_VPE_SWINT1_MAP_OFS		0x0058
#define GIC_VPE_OTHER_ADDR_OFS		0x0080
#define GIC_VPE_WD_CONFIG0_OFS		0x0090
#define GIC_VPE_WD_COUNT0_OFS		0x0094
#define GIC_VPE_WD_INITIAL0_OFS		0x0098
#define GIC_VPE_COMPARE_LO_OFS		0x00a0
#define GIC_VPE_COMPARE_HI		0x00a4

#define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100
#define GIC_VPE_EIC_SS(intr) \
	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))

#define GIC_VPE_EIC_VEC_BASE		0x0800
#define GIC_VPE_EIC_VEC(intr) \
	(GIC_VPE_EIC_VEC_BASE + (4 * intr))

#define GIC_VPE_TENABLE_NMI_OFS		0x1000
#define GIC_VPE_TENABLE_YQ_OFS		0x1004
#define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
#define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084

/* User Mode Visible Section Register Map */
#define GIC_UMV_SH_COUNTER_31_00_OFS	0x0000
#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004

#else /* CONFIG_CPU_BIG_ENDIAN */

#define	GIC_SH_CONFIG_OFS		0x0000

/* Shared Global Counter */
#define GIC_SH_COUNTER_31_00_OFS	0x0014
#define GIC_SH_COUNTER_63_32_OFS	0x0010

/* Interrupt Polarity */
#define GIC_SH_POL_31_0_OFS		0x0104
#define GIC_SH_POL_63_32_OFS		0x0100
#define GIC_SH_POL_95_64_OFS		0x010c
#define GIC_SH_POL_127_96_OFS		0x0108
#define GIC_SH_POL_159_128_OFS		0x0114
#define GIC_SH_POL_191_160_OFS		0x0110
#define GIC_SH_POL_223_192_OFS		0x011c
#define GIC_SH_POL_255_224_OFS		0x0118

/* Edge/Level Triggering */
#define GIC_SH_TRIG_31_0_OFS		0x0184
#define GIC_SH_TRIG_63_32_OFS		0x0180
#define GIC_SH_TRIG_95_64_OFS		0x018c
#define GIC_SH_TRIG_127_96_OFS		0x0188
#define GIC_SH_TRIG_159_128_OFS		0x0194
#define GIC_SH_TRIG_191_160_OFS		0x0190
#define GIC_SH_TRIG_223_192_OFS		0x019c
#define GIC_SH_TRIG_255_224_OFS		0x0198

/* Dual Edge Triggering */
#define GIC_SH_DUAL_31_0_OFS		0x0204
#define GIC_SH_DUAL_63_32_OFS		0x0200
#define GIC_SH_DUAL_95_64_OFS		0x020c
#define GIC_SH_DUAL_127_96_OFS		0x0208
#define GIC_SH_DUAL_159_128_OFS		0x0214
#define GIC_SH_DUAL_191_160_OFS		0x0210
#define GIC_SH_DUAL_223_192_OFS		0x021c
#define GIC_SH_DUAL_255_224_OFS		0x0218

/* Set/Clear corresponding bit in Edge Detect Register */
#define GIC_SH_WEDGE_OFS		0x0280

/* Reset Mask - Disables Interrupt */
#define GIC_SH_RMASK_31_0_OFS		0x0304
#define GIC_SH_RMASK_63_32_OFS		0x0300
#define GIC_SH_RMASK_95_64_OFS		0x030c
#define GIC_SH_RMASK_127_96_OFS		0x0308
#define GIC_SH_RMASK_159_128_OFS	0x0314
#define GIC_SH_RMASK_191_160_OFS	0x0310
#define GIC_SH_RMASK_223_192_OFS	0x031c
#define GIC_SH_RMASK_255_224_OFS	0x0318

/* Set Mask (WO) - Enables Interrupt */
#define GIC_SH_SMASK_31_0_OFS		0x0384
#define GIC_SH_SMASK_63_32_OFS		0x0380
#define GIC_SH_SMASK_95_64_OFS		0x038c
#define GIC_SH_SMASK_127_96_OFS		0x0388
#define GIC_SH_SMASK_159_128_OFS	0x0394
#define GIC_SH_SMASK_191_160_OFS	0x0390
#define GIC_SH_SMASK_223_192_OFS	0x039c
#define GIC_SH_SMASK_255_224_OFS	0x0398

/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
#define GIC_SH_MASK_31_0_OFS		0x0404
#define GIC_SH_MASK_63_32_OFS		0x0400
#define GIC_SH_MASK_95_64_OFS		0x040c
#define GIC_SH_MASK_127_96_OFS		0x0408
#define GIC_SH_MASK_159_128_OFS		0x0414
#define GIC_SH_MASK_191_160_OFS		0x0410
#define GIC_SH_MASK_223_192_OFS		0x041c
#define GIC_SH_MASK_255_224_OFS		0x0418

/* Pending Global Interrupts (RO) */
#define GIC_SH_PEND_31_0_OFS		0x0484
#define GIC_SH_PEND_63_32_OFS		0x0480
#define GIC_SH_PEND_95_64_OFS		0x048c
#define GIC_SH_PEND_127_96_OFS		0x0488
#define GIC_SH_PEND_159_128_OFS		0x0494
#define GIC_SH_PEND_191_160_OFS		0x0490
#define GIC_SH_PEND_223_192_OFS		0x049c
#define GIC_SH_PEND_255_224_OFS		0x0498

#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS	0x0500

/* Maps Interrupt X to a Pin */
#define GIC_SH_MAP_TO_PIN(intr) \
	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))

#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS	0x2004

/*
 * Maps Interrupt X to a VPE.  This is more complex than the LE case, as
 * odd and even registers need to be transposed.  It does work - trust me!
 */
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
	(((((vpe) / 32) ^ 1) - 1) * 4))
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))

/* Polarity */
#define GIC_SH_SET_POLARITY_OFS		0x0100
#define GIC_SET_POLARITY(intr, pol) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))

/* Triggering */
#define GIC_SH_SET_TRIGGER_OFS		0x0180
#define GIC_SET_TRIGGER(intr, trig) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))

/* Mask manipulation */
#define GIC_SH_SMASK_OFS		0x0380
#define GIC_SET_INTR_MASK(intr, val) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))

#define GIC_SH_RMASK_OFS		0x0300
#define GIC_CLR_INTR_MASK(intr, val) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))

/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS			0x0000
#define GIC_VPE_PEND_OFS		0x0004
#define GIC_VPE_MASK_OFS		0x0008
#define GIC_VPE_RMASK_OFS		0x000c
#define GIC_VPE_SMASK_OFS		0x0010
#define GIC_VPE_WD_MAP_OFS		0x0040
#define GIC_VPE_COMPARE_MAP_OFS		0x0044
#define GIC_VPE_TIMER_MAP_OFS		0x0048
#define GIC_VPE_PERFCTR_MAP_OFS		0x0050
#define GIC_VPE_SWINT0_MAP_OFS		0x0054
#define GIC_VPE_SWINT1_MAP_OFS		0x0058
#define GIC_VPE_OTHER_ADDR_OFS		0x0080
#define GIC_VPE_WD_CONFIG0_OFS		0x0090
#define GIC_VPE_WD_COUNT0_OFS		0x0094
#define GIC_VPE_WD_INITIAL0_OFS		0x0098
#define GIC_VPE_COMPARE_LO_OFS		0x00a4
#define GIC_VPE_COMPARE_HI_OFS		0x00a0

#define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100
#define GIC_VPE_EIC_SS(intr) \
	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))

#define GIC_VPE_EIC_VEC_BASE		0x0800
#define GIC_VPE_EIC_VEC(intr) \
	(GIC_VPE_EIC_VEC_BASE + (4 * intr))

#define GIC_VPE_TENABLE_NMI_OFS		0x1000
#define GIC_VPE_TENABLE_YQ_OFS		0x1004
#define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
#define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084

/* User Mode Visible Section Register Map */
#define GIC_UMV_SH_COUNTER_31_00_OFS	0x0004
#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0000

#endif /* !LE */

/* Masks */
#define GIC_SH_CONFIG_COUNTSTOP_SHF	28
#define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)

#define GIC_SH_CONFIG_COUNTBITS_SHF	24
#define GIC_SH_CONFIG_COUNTBITS_MSK	(MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)

#define GIC_SH_CONFIG_NUMINTRS_SHF	16
#define GIC_SH_CONFIG_NUMINTRS_MSK	(MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)

#define GIC_SH_CONFIG_NUMVPES_SHF	0
#define GIC_SH_CONFIG_NUMVPES_MSK	(MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)

#define GIC_SH_WEDGE_SET(intr)		(intr | (0x1 << 31))
#define GIC_SH_WEDGE_CLR(intr)		(intr & ~(0x1 << 31))

#define GIC_MAP_TO_PIN_SHF		31
#define GIC_MAP_TO_PIN_MSK		(MSK(1) << GIC_MAP_TO_PIN_SHF)
#define GIC_MAP_TO_NMI_SHF		30
#define GIC_MAP_TO_NMI_MSK		(MSK(1) << GIC_MAP_TO_NMI_SHF)
#define GIC_MAP_TO_YQ_SHF		29
#define GIC_MAP_TO_YQ_MSK		(MSK(1) << GIC_MAP_TO_YQ_SHF)
#define GIC_MAP_SHF			0
#define GIC_MAP_MSK			(MSK(6) << GIC_MAP_SHF)

/* GIC_VPE_CTL Masks */
#define GIC_VPE_CTL_PERFCNT_RTBL_SHF	2
#define GIC_VPE_CTL_PERFCNT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
#define GIC_VPE_CTL_TIMER_RTBL_SHF	1
#define GIC_VPE_CTL_TIMER_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
#define GIC_VPE_CTL_EIC_MODE_SHF	0
#define GIC_VPE_CTL_EIC_MODE_MSK	(MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)

/* GIC_VPE_PEND Masks */
#define GIC_VPE_PEND_WD_SHF		0
#define GIC_VPE_PEND_WD_MSK		(MSK(1) << GIC_VPE_PEND_WD_SHF)
#define GIC_VPE_PEND_CMP_SHF		1
#define GIC_VPE_PEND_CMP_MSK		(MSK(1) << GIC_VPE_PEND_CMP_SHF)
#define GIC_VPE_PEND_TIMER_SHF		2
#define GIC_VPE_PEND_TIMER_MSK		(MSK(1) << GIC_VPE_PEND_TIMER_SHF)
#define GIC_VPE_PEND_PERFCOUNT_SHF	3
#define GIC_VPE_PEND_PERFCOUNT_MSK	(MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
#define GIC_VPE_PEND_SWINT0_SHF		4
#define GIC_VPE_PEND_SWINT0_MSK		(MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
#define GIC_VPE_PEND_SWINT1_SHF		5
#define GIC_VPE_PEND_SWINT1_MSK		(MSK(1) << GIC_VPE_PEND_SWINT1_SHF)

/* GIC_VPE_RMASK Masks */
#define GIC_VPE_RMASK_WD_SHF		0
#define GIC_VPE_RMASK_WD_MSK		(MSK(1) << GIC_VPE_RMASK_WD_SHF)
#define GIC_VPE_RMASK_CMP_SHF		1
#define GIC_VPE_RMASK_CMP_MSK		(MSK(1) << GIC_VPE_RMASK_CMP_SHF)
#define GIC_VPE_RMASK_TIMER_SHF		2
#define GIC_VPE_RMASK_TIMER_MSK		(MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
#define GIC_VPE_RMASK_PERFCNT_SHF	3
#define GIC_VPE_RMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
#define GIC_VPE_RMASK_SWINT0_SHF	4
#define GIC_VPE_RMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
#define GIC_VPE_RMASK_SWINT1_SHF	5
#define GIC_VPE_RMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)

/* GIC_VPE_SMASK Masks */
#define GIC_VPE_SMASK_WD_SHF		0
#define GIC_VPE_SMASK_WD_MSK		(MSK(1) << GIC_VPE_SMASK_WD_SHF)
#define GIC_VPE_SMASK_CMP_SHF		1
#define GIC_VPE_SMASK_CMP_MSK		(MSK(1) << GIC_VPE_SMASK_CMP_SHF)
#define GIC_VPE_SMASK_TIMER_SHF		2
#define GIC_VPE_SMASK_TIMER_MSK		(MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
#define GIC_VPE_SMASK_PERFCNT_SHF	3
#define GIC_VPE_SMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
#define GIC_VPE_SMASK_SWINT0_SHF	4
#define GIC_VPE_SMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
#define GIC_VPE_SMASK_SWINT1_SHF	5
#define GIC_VPE_SMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)

/*
 * Set the Mapping of Interrupt X to a VPE.
 */
#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
		 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))

struct gic_pcpu_mask {
       DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
};

struct gic_pending_regs {
       DECLARE_BITMAP(pending, GIC_NUM_INTRS);
};

struct gic_intrmask_regs {
       DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
};

/*
 * Interrupt Meta-data specification. The ipiflag helps
 * in building ipi_map.
 */
struct gic_intr_map {
	unsigned int intrnum; 	/* Ext Intr Num 	*/
	unsigned int cpunum;	/* Directed to this CPU */
	unsigned int pin;	/* Directed to this Pin */
	unsigned int polarity;	/* Polarity : +/-	*/
	unsigned int trigtype;	/* Trigger  : Edge/Levl */
	unsigned int ipiflag;	/* Is used for IPI ?	*/
};

extern void gic_init(unsigned long gic_base_addr,
	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
	unsigned int intrmap_size, unsigned int irqbase);

extern unsigned int gic_get_int(void);
extern void gic_send_ipi(unsigned int intr);

#endif /* _ASM_GICREGS_H */
Commit	Line	Data
39b8d525 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2000, 07 MIPS Technologies, Inc.
	7	*
	8	* GIC Register Definitions
	9	*
	10	*/
	11	#ifndef _ASM_GICREGS_H
	12	#define _ASM_GICREGS_H
	13
	14	#undef GICISBYTELITTLEENDIAN
	15	#define GICISWORDLITTLEENDIAN
	16
	17	/* Constants */
	18	#define GIC_POL_POS 1
	19	#define GIC_POL_NEG 0
	20	#define GIC_TRIG_EDGE 1
	21	#define GIC_TRIG_LEVEL 0
	22
	23	#define GIC_NUM_INTRS 32
	24
	25	#define MSK(n) ((1 << (n)) - 1)
	26	#define REG32(addr) ((volatile unsigned int ) (addr))
	27	#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS)
	28	#define REGP(base, phys) REG32((unsigned int)(base) + (phys))
	29
	30	/* Accessors */
	31	#define GIC_REG(segment, offset) \
	32	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
	33	#define GIC_REG_ADDR(segment, offset) \
	34	REG32(_gic_base + segment##_##SECTION_OFS + offset)
	35
	36	#define GIC_ABS_REG(segment, offset) \
	37	(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
	38	#define GIC_REG_ABS_ADDR(segment, offset) \
	39	(_gic_base + segment##_##SECTION_OFS + offset)
	40
	41	#ifdef GICISBYTELITTLEENDIAN
	42	#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data)
	43	#define GICWRITE(reg, data) (reg) = cpu_to_le32(data)
	44	#define GICBIS(reg, bits) \
	45	({unsigned int data; \
	46	GICREAD(reg, data); \
	47	data \|= bits; \
	48	GICWRITE(reg, data); \
	49	})
	50
	51	#else
	52	#define GICREAD(reg, data) (data) = (reg)
	53	#define GICWRITE(reg, data) (reg) = (data)
	54	#define GICBIS(reg, bits) (reg) \|= (bits)
	55	#endif
	56
	57
	58	/* GIC Address Space */
	59	#define SHARED_SECTION_OFS 0x0000
	60	#define SHARED_SECTION_SIZE 0x8000
	61	#define VPE_LOCAL_SECTION_OFS 0x8000
	62	#define VPE_LOCAL_SECTION_SIZE 0x4000
	63	#define VPE_OTHER_SECTION_OFS 0xc000
	64	#define VPE_OTHER_SECTION_SIZE 0x4000
65	#define USM_VISIBLE_SECTION_OFS 0x10000
66	#define USM_VISIBLE_SECTION_SIZE 0x10000
67
68	/* Register Map for Shared Section */
69	#if defined(CONFIG_CPU_LITTLE_ENDIAN) \|\| defined(GICISWORDLITTLEENDIAN)
70
71	#define GIC_SH_CONFIG_OFS 0x0000
72
73	/* Shared Global Counter */
74	#define GIC_SH_COUNTER_31_00_OFS 0x0010
75	#define GIC_SH_COUNTER_63_32_OFS 0x0014
76
77	/* Interrupt Polarity */
78	#define GIC_SH_POL_31_0_OFS 0x0100
79	#define GIC_SH_POL_63_32_OFS 0x0104
80	#define GIC_SH_POL_95_64_OFS 0x0108
81	#define GIC_SH_POL_127_96_OFS 0x010c
82	#define GIC_SH_POL_159_128_OFS 0x0110
83	#define GIC_SH_POL_191_160_OFS 0x0114
84	#define GIC_SH_POL_223_192_OFS 0x0118
85	#define GIC_SH_POL_255_224_OFS 0x011c
86
87	/* Edge/Level Triggering */
88	#define GIC_SH_TRIG_31_0_OFS 0x0180
89	#define GIC_SH_TRIG_63_32_OFS 0x0184
90	#define GIC_SH_TRIG_95_64_OFS 0x0188
91	#define GIC_SH_TRIG_127_96_OFS 0x018c
92	#define GIC_SH_TRIG_159_128_OFS 0x0190
93	#define GIC_SH_TRIG_191_160_OFS 0x0194
94	#define GIC_SH_TRIG_223_192_OFS 0x0198
95	#define GIC_SH_TRIG_255_224_OFS 0x019c
96
97	/* Dual Edge Triggering */
98	#define GIC_SH_DUAL_31_0_OFS 0x0200
99	#define GIC_SH_DUAL_63_32_OFS 0x0204
100	#define GIC_SH_DUAL_95_64_OFS 0x0208
101	#define GIC_SH_DUAL_127_96_OFS 0x020c
102	#define GIC_SH_DUAL_159_128_OFS 0x0210
103	#define GIC_SH_DUAL_191_160_OFS 0x0214
104	#define GIC_SH_DUAL_223_192_OFS 0x0218
105	#define GIC_SH_DUAL_255_224_OFS 0x021c
106
107	/* Set/Clear corresponding bit in Edge Detect Register */
108	#define GIC_SH_WEDGE_OFS 0x0280
109
110	/* Reset Mask - Disables Interrupt */
111	#define GIC_SH_RMASK_31_0_OFS 0x0300
112	#define GIC_SH_RMASK_63_32_OFS 0x0304
113	#define GIC_SH_RMASK_95_64_OFS 0x0308
114	#define GIC_SH_RMASK_127_96_OFS 0x030c
115	#define GIC_SH_RMASK_159_128_OFS 0x0310
116	#define GIC_SH_RMASK_191_160_OFS 0x0314
117	#define GIC_SH_RMASK_223_192_OFS 0x0318
118	#define GIC_SH_RMASK_255_224_OFS 0x031c
119
120	/* Set Mask (WO) - Enables Interrupt */
121	#define GIC_SH_SMASK_31_0_OFS 0x0380
122	#define GIC_SH_SMASK_63_32_OFS 0x0384
123	#define GIC_SH_SMASK_95_64_OFS 0x0388
124	#define GIC_SH_SMASK_127_96_OFS 0x038c
125	#define GIC_SH_SMASK_159_128_OFS 0x0390
126	#define GIC_SH_SMASK_191_160_OFS 0x0394
127	#define GIC_SH_SMASK_223_192_OFS 0x0398
128	#define GIC_SH_SMASK_255_224_OFS 0x039c
129
130	/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
131	#define GIC_SH_MASK_31_0_OFS 0x0400
132	#define GIC_SH_MASK_63_32_OFS 0x0404
133	#define GIC_SH_MASK_95_64_OFS 0x0408
134	#define GIC_SH_MASK_127_96_OFS 0x040c
135	#define GIC_SH_MASK_159_128_OFS 0x0410
136	#define GIC_SH_MASK_191_160_OFS 0x0414
137	#define GIC_SH_MASK_223_192_OFS 0x0418
138	#define GIC_SH_MASK_255_224_OFS 0x041c
139
140	/* Pending Global Interrupts (RO) */
141	#define GIC_SH_PEND_31_0_OFS 0x0480
142	#define GIC_SH_PEND_63_32_OFS 0x0484
143	#define GIC_SH_PEND_95_64_OFS 0x0488
144	#define GIC_SH_PEND_127_96_OFS 0x048c
145	#define GIC_SH_PEND_159_128_OFS 0x0490
146	#define GIC_SH_PEND_191_160_OFS 0x0494
147	#define GIC_SH_PEND_223_192_OFS 0x0498
148	#define GIC_SH_PEND_255_224_OFS 0x049c
149
150	#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
151
152	/* Maps Interrupt X to a Pin */
153	#define GIC_SH_MAP_TO_PIN(intr) \
154	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
155
156	#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
157
158	/* Maps Interrupt X to a VPE */
159	#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
160	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
161	#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
162
163	/* Polarity : Reset Value is always 0 */
164	#define GIC_SH_SET_POLARITY_OFS 0x0100
165	#define GIC_SET_POLARITY(intr, pol) \
166	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
167
168	/* Triggering : Reset Value is always 0 */
169	#define GIC_SH_SET_TRIGGER_OFS 0x0180
170	#define GIC_SET_TRIGGER(intr, trig) \
171	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
172
173	/* Mask manipulation */
174	#define GIC_SH_SMASK_OFS 0x0380
175	#define GIC_SET_INTR_MASK(intr, val) \
176	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
177
178	#define GIC_SH_RMASK_OFS 0x0300
179	#define GIC_CLR_INTR_MASK(intr, val) \
180	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
181
182	/* Register Map for Local Section */
183	#define GIC_VPE_CTL_OFS 0x0000
184	#define GIC_VPE_PEND_OFS 0x0004
185	#define GIC_VPE_MASK_OFS 0x0008
186	#define GIC_VPE_RMASK_OFS 0x000c
187	#define GIC_VPE_SMASK_OFS 0x0010
188	#define GIC_VPE_WD_MAP_OFS 0x0040
189	#define GIC_VPE_COMPARE_MAP_OFS 0x0044
190	#define GIC_VPE_TIMER_MAP_OFS 0x0048
191	#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
192	#define GIC_VPE_SWINT0_MAP_OFS 0x0054
193	#define GIC_VPE_SWINT1_MAP_OFS 0x0058
194	#define GIC_VPE_OTHER_ADDR_OFS 0x0080
195	#define GIC_VPE_WD_CONFIG0_OFS 0x0090
196	#define GIC_VPE_WD_COUNT0_OFS 0x0094
197	#define GIC_VPE_WD_INITIAL0_OFS 0x0098
198	#define GIC_VPE_COMPARE_LO_OFS 0x00a0
199	#define GIC_VPE_COMPARE_HI 0x00a4
200
201	#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
202	#define GIC_VPE_EIC_SS(intr) \
203	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
204
205	#define GIC_VPE_EIC_VEC_BASE 0x0800
206	#define GIC_VPE_EIC_VEC(intr) \
207	(GIC_VPE_EIC_VEC_BASE + (4 * intr))
208
209	#define GIC_VPE_TENABLE_NMI_OFS 0x1000
210	#define GIC_VPE_TENABLE_YQ_OFS 0x1004
211	#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
212	#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
213
214	/* User Mode Visible Section Register Map */
215	#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
216	#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
217
218	#else /* CONFIG_CPU_BIG_ENDIAN */
219
220	#define GIC_SH_CONFIG_OFS 0x0000
221
222	/* Shared Global Counter */
223	#define GIC_SH_COUNTER_31_00_OFS 0x0014
224	#define GIC_SH_COUNTER_63_32_OFS 0x0010
225
226	/* Interrupt Polarity */
227	#define GIC_SH_POL_31_0_OFS 0x0104
228	#define GIC_SH_POL_63_32_OFS 0x0100
229	#define GIC_SH_POL_95_64_OFS 0x010c
230	#define GIC_SH_POL_127_96_OFS 0x0108
231	#define GIC_SH_POL_159_128_OFS 0x0114
232	#define GIC_SH_POL_191_160_OFS 0x0110
233	#define GIC_SH_POL_223_192_OFS 0x011c
234	#define GIC_SH_POL_255_224_OFS 0x0118
235
236	/* Edge/Level Triggering */
237	#define GIC_SH_TRIG_31_0_OFS 0x0184
238	#define GIC_SH_TRIG_63_32_OFS 0x0180
239	#define GIC_SH_TRIG_95_64_OFS 0x018c
240	#define GIC_SH_TRIG_127_96_OFS 0x0188
241	#define GIC_SH_TRIG_159_128_OFS 0x0194
242	#define GIC_SH_TRIG_191_160_OFS 0x0190
243	#define GIC_SH_TRIG_223_192_OFS 0x019c
244	#define GIC_SH_TRIG_255_224_OFS 0x0198
245
246	/* Dual Edge Triggering */
247	#define GIC_SH_DUAL_31_0_OFS 0x0204
248	#define GIC_SH_DUAL_63_32_OFS 0x0200
249	#define GIC_SH_DUAL_95_64_OFS 0x020c
250	#define GIC_SH_DUAL_127_96_OFS 0x0208
251	#define GIC_SH_DUAL_159_128_OFS 0x0214
252	#define GIC_SH_DUAL_191_160_OFS 0x0210
253	#define GIC_SH_DUAL_223_192_OFS 0x021c
254	#define GIC_SH_DUAL_255_224_OFS 0x0218
255
256	/* Set/Clear corresponding bit in Edge Detect Register */
257	#define GIC_SH_WEDGE_OFS 0x0280
258
259	/* Reset Mask - Disables Interrupt */
260	#define GIC_SH_RMASK_31_0_OFS 0x0304
261	#define GIC_SH_RMASK_63_32_OFS 0x0300
262	#define GIC_SH_RMASK_95_64_OFS 0x030c
263	#define GIC_SH_RMASK_127_96_OFS 0x0308
264	#define GIC_SH_RMASK_159_128_OFS 0x0314
265	#define GIC_SH_RMASK_191_160_OFS 0x0310
266	#define GIC_SH_RMASK_223_192_OFS 0x031c
267	#define GIC_SH_RMASK_255_224_OFS 0x0318
268
269	/* Set Mask (WO) - Enables Interrupt */
270	#define GIC_SH_SMASK_31_0_OFS 0x0384
271	#define GIC_SH_SMASK_63_32_OFS 0x0380
272	#define GIC_SH_SMASK_95_64_OFS 0x038c
273	#define GIC_SH_SMASK_127_96_OFS 0x0388
274	#define GIC_SH_SMASK_159_128_OFS 0x0394
275	#define GIC_SH_SMASK_191_160_OFS 0x0390
276	#define GIC_SH_SMASK_223_192_OFS 0x039c
277	#define GIC_SH_SMASK_255_224_OFS 0x0398
278
279	/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
280	#define GIC_SH_MASK_31_0_OFS 0x0404
281	#define GIC_SH_MASK_63_32_OFS 0x0400
282	#define GIC_SH_MASK_95_64_OFS 0x040c
283	#define GIC_SH_MASK_127_96_OFS 0x0408
284	#define GIC_SH_MASK_159_128_OFS 0x0414
285	#define GIC_SH_MASK_191_160_OFS 0x0410
286	#define GIC_SH_MASK_223_192_OFS 0x041c
287	#define GIC_SH_MASK_255_224_OFS 0x0418
288
289	/* Pending Global Interrupts (RO) */
290	#define GIC_SH_PEND_31_0_OFS 0x0484
291	#define GIC_SH_PEND_63_32_OFS 0x0480
292	#define GIC_SH_PEND_95_64_OFS 0x048c
293	#define GIC_SH_PEND_127_96_OFS 0x0488
294	#define GIC_SH_PEND_159_128_OFS 0x0494
295	#define GIC_SH_PEND_191_160_OFS 0x0490
296	#define GIC_SH_PEND_223_192_OFS 0x049c
297	#define GIC_SH_PEND_255_224_OFS 0x0498
298
299	#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
300
301	/* Maps Interrupt X to a Pin */
302	#define GIC_SH_MAP_TO_PIN(intr) \
303	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
304
305	#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
306
307	/*
308	* Maps Interrupt X to a VPE. This is more complex than the LE case, as
309	* odd and even registers need to be transposed. It does work - trust me!
310	*/
311	#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
312	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
313	(((((vpe) / 32) ^ 1) - 1) * 4))
314	#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
315
316	/* Polarity */
317	#define GIC_SH_SET_POLARITY_OFS 0x0100
318	#define GIC_SET_POLARITY(intr, pol) \
319	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
320
321	/* Triggering */
322	#define GIC_SH_SET_TRIGGER_OFS 0x0180
323	#define GIC_SET_TRIGGER(intr, trig) \
324	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
325
326	/* Mask manipulation */
327	#define GIC_SH_SMASK_OFS 0x0380
328	#define GIC_SET_INTR_MASK(intr, val) \
329	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
330
331	#define GIC_SH_RMASK_OFS 0x0300
332	#define GIC_CLR_INTR_MASK(intr, val) \
9d5437a1	333	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
39b8d525 RB	334
	335	/* Register Map for Local Section */
	336	#define GIC_VPE_CTL_OFS 0x0000
	337	#define GIC_VPE_PEND_OFS 0x0004
	338	#define GIC_VPE_MASK_OFS 0x0008
	339	#define GIC_VPE_RMASK_OFS 0x000c
	340	#define GIC_VPE_SMASK_OFS 0x0010
	341	#define GIC_VPE_WD_MAP_OFS 0x0040
	342	#define GIC_VPE_COMPARE_MAP_OFS 0x0044
	343	#define GIC_VPE_TIMER_MAP_OFS 0x0048
	344	#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
	345	#define GIC_VPE_SWINT0_MAP_OFS 0x0054
	346	#define GIC_VPE_SWINT1_MAP_OFS 0x0058
	347	#define GIC_VPE_OTHER_ADDR_OFS 0x0080
	348	#define GIC_VPE_WD_CONFIG0_OFS 0x0090
	349	#define GIC_VPE_WD_COUNT0_OFS 0x0094
	350	#define GIC_VPE_WD_INITIAL0_OFS 0x0098
	351	#define GIC_VPE_COMPARE_LO_OFS 0x00a4
	352	#define GIC_VPE_COMPARE_HI_OFS 0x00a0
	353
	354	#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
	355	#define GIC_VPE_EIC_SS(intr) \
	356	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
	357
	358	#define GIC_VPE_EIC_VEC_BASE 0x0800
	359	#define GIC_VPE_EIC_VEC(intr) \
	360	(GIC_VPE_EIC_VEC_BASE + (4 * intr))
	361
	362	#define GIC_VPE_TENABLE_NMI_OFS 0x1000
	363	#define GIC_VPE_TENABLE_YQ_OFS 0x1004
	364	#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
	365	#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
	366
	367	/* User Mode Visible Section Register Map */
	368	#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
	369	#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
	370
	371	#endif /* !LE */
	372
	373	/* Masks */
	374	#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
	375	#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
	376
	377	#define GIC_SH_CONFIG_COUNTBITS_SHF 24
	378	#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
	379
	380	#define GIC_SH_CONFIG_NUMINTRS_SHF 16
	381	#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
	382
	383	#define GIC_SH_CONFIG_NUMVPES_SHF 0
	384	#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
	385
	386	#define GIC_SH_WEDGE_SET(intr) (intr \| (0x1 << 31))
	387	#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
	388
	389	#define GIC_MAP_TO_PIN_SHF 31
	390	#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
	391	#define GIC_MAP_TO_NMI_SHF 30
	392	#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
	393	#define GIC_MAP_TO_YQ_SHF 29
	394	#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
	395	#define GIC_MAP_SHF 0
	396	#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
	397
398	/* GIC_VPE_CTL Masks */
399	#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
400	#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
401	#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
402	#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
403	#define GIC_VPE_CTL_EIC_MODE_SHF 0
404	#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
405
406	/* GIC_VPE_PEND Masks */
407	#define GIC_VPE_PEND_WD_SHF 0
408	#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
409	#define GIC_VPE_PEND_CMP_SHF 1
410	#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
411	#define GIC_VPE_PEND_TIMER_SHF 2
412	#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
413	#define GIC_VPE_PEND_PERFCOUNT_SHF 3
414	#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
415	#define GIC_VPE_PEND_SWINT0_SHF 4
416	#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
417	#define GIC_VPE_PEND_SWINT1_SHF 5
418	#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
419
420	/* GIC_VPE_RMASK Masks */
421	#define GIC_VPE_RMASK_WD_SHF 0
422	#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
423	#define GIC_VPE_RMASK_CMP_SHF 1
424	#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
425	#define GIC_VPE_RMASK_TIMER_SHF 2
426	#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
427	#define GIC_VPE_RMASK_PERFCNT_SHF 3
428	#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
429	#define GIC_VPE_RMASK_SWINT0_SHF 4
430	#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
431	#define GIC_VPE_RMASK_SWINT1_SHF 5
432	#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
433
434	/* GIC_VPE_SMASK Masks */
435	#define GIC_VPE_SMASK_WD_SHF 0
436	#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
437	#define GIC_VPE_SMASK_CMP_SHF 1
438	#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
439	#define GIC_VPE_SMASK_TIMER_SHF 2
440	#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
441	#define GIC_VPE_SMASK_PERFCNT_SHF 3
442	#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
443	#define GIC_VPE_SMASK_SWINT0_SHF 4
444	#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
445	#define GIC_VPE_SMASK_SWINT1_SHF 5
446	#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
447
448	/*
449	* Set the Mapping of Interrupt X to a VPE.
450	*/
451	#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
452	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
453	GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
454
455	struct gic_pcpu_mask {
456	DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
457	};
458
459	struct gic_pending_regs {
460	DECLARE_BITMAP(pending, GIC_NUM_INTRS);
461	};
462
463	struct gic_intrmask_regs {
464	DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
465	};
466
467	/*
468	* Interrupt Meta-data specification. The ipiflag helps
469	* in building ipi_map.
470	*/
471	struct gic_intr_map {
472	unsigned int intrnum; /* Ext Intr Num */
473	unsigned int cpunum; /* Directed to this CPU */
474	unsigned int pin; /* Directed to this Pin */
475	unsigned int polarity; /* Polarity : +/- */
476	unsigned int trigtype; /* Trigger : Edge/Levl */
477	unsigned int ipiflag; /* Is used for IPI ? */
478	};
479
480	extern void gic_init(unsigned long gic_base_addr,
481	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
482	unsigned int intrmap_size, unsigned int irqbase);
483
484	extern unsigned int gic_get_int(void);
485	extern void gic_send_ipi(unsigned int intr);
486
487	#endif /* _ASM_GICREGS_H */