[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-m32r / cache.h

#ifndef _ASM_M32R_CACHE_H
#define _ASM_M32R_CACHE_H

/* L1 cache line size */
#define L1_CACHE_SHIFT		4
#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#endif  /* _ASM_M32R_CACHE_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_M32R_CACHE_H
	2	#define _ASM_M32R_CACHE_H
	3
1da177e4 LT	4	/* L1 cache line size */
	5	#define L1_CACHE_SHIFT 4
	6	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
	7
1da177e4	8	#endif /* _ASM_M32R_CACHE_H */