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Rework ptep_set_access_flags and fix sun4c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-ia64 / pgtable.h
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1da177e4
LT		 1#ifndef _ASM_IA64_PGTABLE_H
2#define _ASM_IA64_PGTABLE_H
3
4/*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h>.
10 *
ad597bd5 11 * Copyright (C) 1998-2005 Hewlett-Packard Co
1da177e4
LT		 12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 */
14
1da177e4
LT		 15
16#include <asm/mman.h>
17#include <asm/page.h>
18#include <asm/processor.h>
19#include <asm/system.h>
20#include <asm/types.h>
21
22#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
23
24/*
25 * First, define the various bits in a PTE. Note that the PTE format
26 * matches the VHPT short format, the firt doubleword of the VHPD long
27 * format, and the first doubleword of the TLB insertion format.
28 */
29#define _PAGE_P_BIT 0
30#define _PAGE_A_BIT 5
31#define _PAGE_D_BIT 6
32
33#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
34#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
35#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
36#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
37#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
38#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
39#define _PAGE_MA_MASK (0x7 << 2)
40#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
41#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
42#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
43#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
44#define _PAGE_PL_MASK (3 << 7)
45#define _PAGE_AR_R (0 << 9) /* read only */
46#define _PAGE_AR_RX (1 << 9) /* read & execute */
47#define _PAGE_AR_RW (2 << 9) /* read & write */
48#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
49#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
50#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
51#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
52#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
53#define _PAGE_AR_MASK (7 << 9)
54#define _PAGE_AR_SHIFT 9
55#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
56#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
57#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
58#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
59#define _PAGE_PROTNONE (__IA64_UL(1) << 63)
60
61/* Valid only for a PTE with the present bit cleared: */
62#define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
63
64#define _PFN_MASK _PAGE_PPN_MASK
65/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
66#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
67
68#define _PAGE_SIZE_4K 12
69#define _PAGE_SIZE_8K 13
70#define _PAGE_SIZE_16K 14
71#define _PAGE_SIZE_64K 16
72#define _PAGE_SIZE_256K 18
73#define _PAGE_SIZE_1M 20
74#define _PAGE_SIZE_4M 22
75#define _PAGE_SIZE_16M 24
76#define _PAGE_SIZE_64M 26
77#define _PAGE_SIZE_256M 28
78#define _PAGE_SIZE_1G 30
79#define _PAGE_SIZE_4G 32
80
81#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
82#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
83#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
84
85/*
837cd0bd 86 * How many pointers will a page table level hold expressed in shift
1da177e4 87 */
837cd0bd 88#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
1da177e4
LT		 89
90/*
837cd0bd
RH		 91 * Definitions for fourth level:
92 */
93#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
94
95/*
96 * Definitions for third level:
1da177e4 97 *
837cd0bd 98 * PMD_SHIFT determines the size of the area a third-level page table
1da177e4
LT		 99 * can map.
100 */
837cd0bd 101#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
1da177e4
LT		 102#define PMD_SIZE (1UL << PMD_SHIFT)
103#define PMD_MASK (~(PMD_SIZE-1))
837cd0bd 104#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
1da177e4 105
837cd0bd 106#ifdef CONFIG_PGTABLE_4
1da177e4 107/*
837cd0bd
RH		 108 * Definitions for second level:
109 *
110 * PUD_SHIFT determines the size of the area a second-level page table
111 * can map.
1da177e4 112 */
837cd0bd
RH		 113#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
114#define PUD_SIZE (1UL << PUD_SHIFT)
115#define PUD_MASK (~(PUD_SIZE-1))
116#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
117#endif
118
119/*
120 * Definitions for first level:
121 *
122 * PGDIR_SHIFT determines what a first-level page table entry can map.
123 */
124#ifdef CONFIG_PGTABLE_4
125#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
126#else
127#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
128#endif
129#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
130#define PGDIR_MASK (~(PGDIR_SIZE-1))
131#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
132#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
133#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
134#define FIRST_USER_ADDRESS 0
1da177e4
LT		 135
136/*
137 * All the normal masks have the "page accessed" bits on, as any time
138 * they are used, the page is accessed. They are cleared only by the
139 * page-out routines.
140 */
141#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
142#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
143#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
144#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
145#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
146#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
147#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
148#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
149
150# ifndef __ASSEMBLY__
151
8c65b4a6 152#include <linux/sched.h> /* for mm_struct */
1da177e4
LT		 153#include <asm/bitops.h>
154#include <asm/cacheflush.h>
155#include <asm/mmu_context.h>
156#include <asm/processor.h>
157
158/*
159 * Next come the mappings that determine how mmap() protection bits
160 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
161 * _P version gets used for a private shared memory segment, the _S
162 * version gets used for a shared memory segment with MAP_SHARED on.
163 * In a private shared memory segment, we do a copy-on-write if a task
164 * attempts to write to the page.
165 */
166 /* xwr */
167#define __P000 PAGE_NONE
168#define __P001 PAGE_READONLY
169#define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
170#define __P011 PAGE_READONLY /* ditto */
171#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
172#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
173#define __P110 PAGE_COPY_EXEC
174#define __P111 PAGE_COPY_EXEC
175
176#define __S000 PAGE_NONE
177#define __S001 PAGE_READONLY
178#define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
179#define __S011 PAGE_SHARED
180#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
181#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
182#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
183#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
184
185#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
837cd0bd
RH		 186#ifdef CONFIG_PGTABLE_4
187#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
188#endif
1da177e4
LT		 189#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
190#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
191
192
193/*
194 * Some definitions to translate between mem_map, PTEs, and page addresses:
195 */
196
197
198/* Quick test to see if ADDR is a (potentially) valid physical address. */
199static inline long
200ia64_phys_addr_valid (unsigned long addr)
201{
202 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
203}
204
205/*
206 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
207 * memory. For the return value to be meaningful, ADDR must be >=
208 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
209 * require a hash-, or multi-level tree-lookup or something of that
210 * sort) but it guarantees to return TRUE only if accessing the page
211 * at that address does not cause an error. Note that there may be
212 * addresses for which kern_addr_valid() returns FALSE even though an
213 * access would not cause an error (e.g., this is typically true for
214 * memory mapped I/O regions.
215 *
216 * XXX Need to implement this for IA-64.
217 */
218#define kern_addr_valid(addr) (1)
219
220
221/*
222 * Now come the defines and routines to manage and access the three-level
223 * page table.
224 */
225
226/*
227 * On some architectures, special things need to be done when setting
228 * the PTE in a page table. Nothing special needs to be on IA-64.
229 */
230#define set_pte(ptep, pteval) (*(ptep) = (pteval))
231#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
232
0a41e250 233#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
1da177e4 234#ifdef CONFIG_VIRTUAL_MEM_MAP
0a41e250 235# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
1da177e4
LT		 236# define VMALLOC_END vmalloc_end
237 extern unsigned long vmalloc_end;
238#else
0a41e250 239# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
1da177e4
LT		 240#endif
241
242/* fs/proc/kcore.c */
0a41e250
PC		 243#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
244#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
1da177e4 245
837cd0bd
RH		 246#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
247#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */
248
1da177e4
LT		 249/*
250 * Conversion functions: convert page frame number (pfn) and a protection value to a page
251 * table entry (pte).
252 */
253#define pfn_pte(pfn, pgprot) \
254({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
255
256/* Extract pfn from pte. */
257#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
258
259#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
260
261/* This takes a physical page address that is used by the remapping functions */
262#define mk_pte_phys(physpage, pgprot) \
263({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
264
265#define pte_modify(_pte, newprot) \
266 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
267
1da177e4
LT		 268#define pte_none(pte) (!pte_val(pte))
269#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
270#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
271/* pte_page() returns the "struct page *" corresponding to the PTE: */
272#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
273
274#define pmd_none(pmd) (!pmd_val(pmd))
275#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
276#define pmd_present(pmd) (pmd_val(pmd) != 0UL)
277#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
46a82b2d 278#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
1da177e4
LT		 279#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
280
281#define pud_none(pud) (!pud_val(pud))
282#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
283#define pud_present(pud) (pud_val(pud) != 0UL)
284#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
46a82b2d
DM		 285#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
286#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET))
1da177e4 287
837cd0bd
RH		 288#ifdef CONFIG_PGTABLE_4
289#define pgd_none(pgd) (!pgd_val(pgd))
290#define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
291#define pgd_present(pgd) (pgd_val(pgd) != 0UL)
292#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
46a82b2d
DM		 293#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
294#define pgd_page(pgd) virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
837cd0bd
RH		 295#endif
296
1da177e4
LT		 297/*
298 * The following have defined behavior only work if pte_present() is true.
299 */
300#define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3)
301#define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
302#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
303#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
304#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
305#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
306#define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
307/*
308 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
309 * access rights:
310 */
311#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
312#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
313#define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX))
314#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
315#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
316#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
317#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
8f860591 318#define pte_mkhuge(pte) (__pte(pte_val(pte)))
1da177e4
LT		 319
320/*
32e62c63
BH		 321 * Make page protection values cacheable, uncacheable, or write-
322 * combining. Note that "protection" is really a misnomer here as the
323 * protection value contains the memory attribute bits, dirty bits, and
324 * various other bits as well.
1da177e4 325 */
32e62c63 326#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
1da177e4 327#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
1da177e4
LT		 328#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
329
32e62c63
BH		 330struct file;
331extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
332 unsigned long size, pgprot_t vma_prot);
333#define __HAVE_PHYS_MEM_ACCESS_PROT
334
1da177e4
LT		 335static inline unsigned long
336pgd_index (unsigned long address)
337{
338 unsigned long region = address >> 61;
339 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
340
341 return (region << (PAGE_SHIFT - 6)) | l1index;
342}
343
344/* The offset in the 1-level directory is given by the 3 region bits
345 (61..63) and the level-1 bits. */
346static inline pgd_t*
347pgd_offset (struct mm_struct *mm, unsigned long address)
348{
349 return mm->pgd + pgd_index(address);
350}
351
352/* In the kernel's mapped region we completely ignore the region number
353 (since we know it's in region number 5). */
354#define pgd_offset_k(addr) \
355 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
356
357/* Look up a pgd entry in the gate area. On IA-64, the gate-area
358 resides in the kernel-mapped segment, hence we use pgd_offset_k()
359 here. */
360#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
361
837cd0bd 362#ifdef CONFIG_PGTABLE_4
1da177e4 363/* Find an entry in the second-level page table.. */
837cd0bd 364#define pud_offset(dir,addr) \
46a82b2d 365 ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
837cd0bd
RH		 366#endif
367
368/* Find an entry in the third-level page table.. */
1da177e4 369#define pmd_offset(dir,addr) \
46a82b2d 370 ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
1da177e4
LT		 371
372/*
373 * Find an entry in the third-level page table. This looks more complicated than it
374 * should be because some platforms place page tables in high memory.
375 */
376#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
46a82b2d 377#define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
1da177e4
LT		 378#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
379#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
380#define pte_unmap(pte) do { } while (0)
381#define pte_unmap_nested(pte) do { } while (0)
382
383/* atomic versions of the some PTE manipulations: */
384
385static inline int
386ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
387{
388#ifdef CONFIG_SMP
389 if (!pte_young(*ptep))
390 return 0;
391 return test_and_clear_bit(_PAGE_A_BIT, ptep);
392#else
393 pte_t pte = *ptep;
394 if (!pte_young(pte))
395 return 0;
396 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
397 return 1;
398#endif
399}
400
401static inline int
402ptep_test_and_clear_dirty (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
403{
404#ifdef CONFIG_SMP
405 if (!pte_dirty(*ptep))
406 return 0;
407 return test_and_clear_bit(_PAGE_D_BIT, ptep);
408#else
409 pte_t pte = *ptep;
410 if (!pte_dirty(pte))
411 return 0;
412 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
413 return 1;
414#endif
415}
416
417static inline pte_t
418ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
419{
420#ifdef CONFIG_SMP
421 return __pte(xchg((long *) ptep, 0));
422#else
423 pte_t pte = *ptep;
424 pte_clear(mm, addr, ptep);
425 return pte;
426#endif
427}
428
429static inline void
430ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
431{
432#ifdef CONFIG_SMP
433 unsigned long new, old;
434
435 do {
436 old = pte_val(*ptep);
437 new = pte_val(pte_wrprotect(__pte (old)));
438 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
439#else
440 pte_t old_pte = *ptep;
441 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
442#endif
443}
444
445static inline int
446pte_same (pte_t a, pte_t b)
447{
448 return pte_val(a) == pte_val(b);
449}
450
451#define update_mmu_cache(vma, address, pte) do { } while (0)
452
453extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
454extern void paging_init (void);
455
456/*
457 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
458 * bits in the swap-type field of the swap pte. It would be nice to
459 * enforce that, but we can't easily include <linux/swap.h> here.
460 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
461 *
462 * Format of swap pte:
463 * bit 0 : present bit (must be zero)
464 * bit 1 : _PAGE_FILE (must be zero)
465 * bits 2- 8: swap-type
466 * bits 9-62: swap offset
467 * bit 63 : _PAGE_PROTNONE bit
468 *
469 * Format of file pte:
470 * bit 0 : present bit (must be zero)
471 * bit 1 : _PAGE_FILE (must be one)
472 * bits 2-62: file_offset/PAGE_SIZE
473 * bit 63 : _PAGE_PROTNONE bit
474 */
475#define __swp_type(entry) (((entry).val >> 2) & 0x7f)
476#define __swp_offset(entry) (((entry).val << 1) >> 10)
477#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
478#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
479#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
480
481#define PTE_FILE_MAX_BITS 61
482#define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
483#define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
484
1da177e4
LT		 485#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
486 remap_pfn_range(vma, vaddr, pfn, size, prot)
487
1da177e4
LT		 488/*
489 * ZERO_PAGE is a global shared page that is always zero: used
490 * for zero-mapped memory areas etc..
491 */
492extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
493extern struct page *zero_page_memmap_ptr;
494#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
495
496/* We provide our own get_unmapped_area to cope with VA holes for userland */
497#define HAVE_ARCH_UNMAPPED_AREA
498
499#ifdef CONFIG_HUGETLB_PAGE
500#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
501#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
502#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
1da177e4
LT		 503#endif
504
505/*
506 * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
507 * information. However, we use this routine to take care of any (delayed) i-cache
508 * flushing that may be necessary.
509 */
510extern void lazy_mmu_prot_update (pte_t pte);
511
512#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
513/*
514 * Update PTEP with ENTRY, which is guaranteed to be a less
515 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
516 * WRITABLE bits turned on, when the value at PTEP did not. The
517 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
518 *
519 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
520 * having to worry about races. On SMP machines, there are only two
521 * cases where this is true:
522 *
523 * (1) *PTEP has the PRESENT bit turned OFF
524 * (2) ENTRY has the DIRTY bit turned ON
525 *
526 * On ia64, we could implement this routine with a cmpxchg()-loop
527 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
528 * However, like on x86, we can get a more streamlined version by
529 * observing that it is OK to drop ACCESSED bit updates when
530 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
531 * result in an extra Access-bit fault, which would then turn on the
532 * ACCESSED bit in the low-level fault handler (iaccess_bit or
533 * daccess_bit in ivt.S).
534 */
535#ifdef CONFIG_SMP
8dab5241
BH		 536# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
537({ \
538 int __changed = !pte_same(*(__ptep), __entry); \
539 if (__changed && __safely_writable) { \
540 set_pte(__ptep, __entry); \
541 flush_tlb_page(__vma, __addr); \
542 } \
543 __changed; \
544})
1da177e4 545#else
8dab5241
BH		 546# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
547({ \
548 int __changed = !pte_same(*(__ptep), __entry); \
549 if (__changed) \
550 ptep_establish(__vma, __addr, __ptep, __entry); \
551 __changed; \
552})
1da177e4
LT		 553#endif
554
555# ifdef CONFIG_VIRTUAL_MEM_MAP
556 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
557# define __HAVE_ARCH_MEMMAP_INIT
558 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
559 unsigned long start_pfn);
560# endif /* CONFIG_VIRTUAL_MEM_MAP */
561# endif /* !__ASSEMBLY__ */
562
563/*
564 * Identity-mapped regions use a large page size. We'll call such large pages
565 * "granules". If you can think of a better name that's unambiguous, let me
566 * know...
567 */
568#if defined(CONFIG_IA64_GRANULE_64MB)
569# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
570#elif defined(CONFIG_IA64_GRANULE_16MB)
571# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
572#endif
573#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
574/*
575 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
576 */
577#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
578#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
579
580/*
581 * No page table caches to initialise
582 */
583#define pgtable_cache_init() do { } while (0)
584
585/* These tell get_user_pages() that the first gate page is accessible from user-level. */
586#define FIXADDR_USER_START GATE_ADDR
ad597bd5
DMT		 587#ifdef HAVE_BUGGY_SEGREL
588# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
589#else
590# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
591#endif
1da177e4
LT		 592
593#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
594#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
595#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
596#define __HAVE_ARCH_PTEP_SET_WRPROTECT
597#define __HAVE_ARCH_PTE_SAME
598#define __HAVE_ARCH_PGD_OFFSET_GATE
599#define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
600
837cd0bd 601#ifndef CONFIG_PGTABLE_4
1da177e4 602#include <asm-generic/pgtable-nopud.h>
837cd0bd 603#endif
1da177e4
LT		 604#include <asm-generic/pgtable.h>
605
606#endif /* _ASM_IA64_PGTABLE_H */
kernel source for telekom puls (alcatel/mediatek)