projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | #ifndef __ASM_MPSPEC_H |
| 2 | #define __ASM_MPSPEC_H | |
| 3 | ||
| 4 | #include <linux/cpumask.h> | |
| 5 | #include <asm/mpspec_def.h> | |
| 6 | #include <mach_mpspec.h> | |
| 7 | ||
| 8 | extern int mp_bus_id_to_type [MAX_MP_BUSSES]; | |
| 9 | extern int mp_bus_id_to_node [MAX_MP_BUSSES]; | |
| 10 | extern int mp_bus_id_to_local [MAX_MP_BUSSES]; | |
| 11 | extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; | |
| 12 | extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; | |
| 13 | ||
| 14 | extern unsigned int boot_cpu_physical_apicid; | |
| 15 | extern int smp_found_config; | |
| 16 | extern void find_smp_config (void); | |
| 17 | extern void get_smp_config (void); | |
| 18 | extern int nr_ioapics; | |
| 19 | extern int apic_version [MAX_APICS]; | |
| 20 | extern int mp_bus_id_to_type [MAX_MP_BUSSES]; | |
| 21 | extern int mp_irq_entries; | |
| 22 | extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; | |
| 23 | extern int mpc_default_type; | |
| 24 | extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; | |
| 25 | extern unsigned long mp_lapic_addr; | |
| 26 | extern int pic_mode; | |
| 27 | extern int using_apic_timer; | |
| 28 | ||
| 888ba6c6 | 29 | #ifdef CONFIG_ACPI |
| 1da177e4 LT |
30 | extern void mp_register_lapic (u8 id, u8 enabled); |
| 31 | extern void mp_register_lapic_address (u64 address); | |
| 32 | extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base); | |
| 33 | extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); | |
| 34 | extern void mp_config_acpi_legacy_irqs (void); | |
| 35 | extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low); | |
| 888ba6c6 | 36 | #endif /* CONFIG_ACPI */ |
| 1da177e4 LT |
37 | |
| 38 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
| 39 | ||
| 40 | struct physid_mask | |
| 41 | { | |
| 42 | unsigned long mask[PHYSID_ARRAY_SIZE]; | |
| 43 | }; | |
| 44 | ||
| 45 | typedef struct physid_mask physid_mask_t; | |
| 46 | ||
| 47 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
| 48 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
| 49 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
| 50 | #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask) | |
| 51 | ||
| 52 | #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
| 53 | #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
| 54 | #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS) | |
| 55 | #define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS) | |
| 56 | #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS) | |
| 57 | #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS) | |
| 58 | #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS) | |
| 59 | #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) | |
| 60 | #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) | |
| 61 | #define physids_coerce(map) ((map).mask[0]) | |
| 62 | ||
| 63 | #define physids_promote(physids) \ | |
| 64 | ({ \ | |
| 65 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
| 66 | __physid_mask.mask[0] = physids; \ | |
| 67 | __physid_mask; \ | |
| 68 | }) | |
| 69 | ||
| 70 | #define physid_mask_of_physid(physid) \ | |
| 71 | ({ \ | |
| 72 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
| 73 | physid_set(physid, __physid_mask); \ | |
| 74 | __physid_mask; \ | |
| 75 | }) | |
| 76 | ||
| 77 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
| 78 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
| 79 | ||
| 80 | extern physid_mask_t phys_cpu_present_map; | |
| 81 | ||
| 82 | #endif | |
| 83 |