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1da177e4 LT |
1 | #ifndef __ARCH_DESC_H |
2 | #define __ARCH_DESC_H | |
3 | ||
4 | #include <asm/ldt.h> | |
5 | #include <asm/segment.h> | |
6 | ||
1da177e4 LT |
7 | #ifndef __ASSEMBLY__ |
8 | ||
9 | #include <linux/preempt.h> | |
10 | #include <linux/smp.h> | |
11 | #include <linux/percpu.h> | |
12 | ||
13 | #include <asm/mmu.h> | |
14 | ||
15 | extern struct desc_struct cpu_gdt_table[GDT_ENTRIES]; | |
251e6912 | 16 | |
1da177e4 LT |
17 | struct Xgt_desc_struct { |
18 | unsigned short size; | |
19 | unsigned long address __attribute__((packed)); | |
20 | unsigned short pad; | |
21 | } __attribute__ ((packed)); | |
22 | ||
2b932f6c JB |
23 | extern struct Xgt_desc_struct idt_descr; |
24 | DECLARE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr); | |
2a57ff1a | 25 | extern struct Xgt_desc_struct early_gdt_descr; |
1da177e4 | 26 | |
7c4cb60e ZA |
27 | static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) |
28 | { | |
2b932f6c | 29 | return (struct desc_struct *)per_cpu(cpu_gdt_descr, cpu).address; |
7c4cb60e ZA |
30 | } |
31 | ||
522e93e3 RR |
32 | extern struct desc_struct idt_table[]; |
33 | extern void set_intr_gate(unsigned int irq, void * addr); | |
34 | ||
35 | static inline void pack_descriptor(__u32 *a, __u32 *b, | |
36 | unsigned long base, unsigned long limit, unsigned char type, unsigned char flags) | |
37 | { | |
38 | *a = ((base & 0xffff) << 16) | (limit & 0xffff); | |
39 | *b = (base & 0xff000000) | ((base & 0xff0000) >> 16) | | |
2817716a | 40 | (limit & 0x000f0000) | ((type & 0xff) << 8) | ((flags & 0xf) << 20); |
522e93e3 RR |
41 | } |
42 | ||
43 | static inline void pack_gate(__u32 *a, __u32 *b, | |
44 | unsigned long base, unsigned short seg, unsigned char type, unsigned char flags) | |
45 | { | |
46 | *a = (seg << 16) | (base & 0xffff); | |
47 | *b = (base & 0xffff0000) | ((type & 0xff) << 8) | (flags & 0xff); | |
48 | } | |
49 | ||
50 | #define DESCTYPE_LDT 0x82 /* present, system, DPL-0, LDT */ | |
51 | #define DESCTYPE_TSS 0x89 /* present, system, DPL-0, 32-bit TSS */ | |
52 | #define DESCTYPE_TASK 0x85 /* present, system, DPL-0, task gate */ | |
53 | #define DESCTYPE_INT 0x8e /* present, system, DPL-0, interrupt gate */ | |
54 | #define DESCTYPE_TRAP 0x8f /* present, system, DPL-0, trap gate */ | |
55 | #define DESCTYPE_DPL3 0x60 /* DPL-3 */ | |
56 | #define DESCTYPE_S 0x10 /* !system */ | |
57 | ||
d3561b7f RR |
58 | #ifdef CONFIG_PARAVIRT |
59 | #include <asm/paravirt.h> | |
60 | #else | |
2f2984eb | 61 | #define load_TR_desc() __asm__ __volatile__("ltr %w0"::"q" (GDT_ENTRY_TSS*8)) |
1da177e4 | 62 | |
4d37e7e3 ZA |
63 | #define load_gdt(dtr) __asm__ __volatile("lgdt %0"::"m" (*dtr)) |
64 | #define load_idt(dtr) __asm__ __volatile("lidt %0"::"m" (*dtr)) | |
522e93e3 RR |
65 | #define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr)) |
66 | #define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt)) | |
4d37e7e3 ZA |
67 | |
68 | #define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr)) | |
69 | #define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr)) | |
522e93e3 RR |
70 | #define store_tr(tr) __asm__ ("str %0":"=m" (tr)) |
71 | #define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt)) | |
4d37e7e3 | 72 | |
522e93e3 RR |
73 | #if TLS_SIZE != 24 |
74 | # error update this code. | |
75 | #endif | |
1da177e4 | 76 | |
522e93e3 | 77 | static inline void load_TLS(struct thread_struct *t, unsigned int cpu) |
1da177e4 | 78 | { |
522e93e3 RR |
79 | #define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i] |
80 | C(0); C(1); C(2); | |
81 | #undef C | |
1da177e4 LT |
82 | } |
83 | ||
522e93e3 RR |
84 | #define write_ldt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b) |
85 | #define write_gdt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b) | |
86 | #define write_idt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b) | |
87 | ||
139ec7c4 | 88 | static inline void write_dt_entry(void *dt, int entry, __u32 entry_a, __u32 entry_b) |
1da177e4 | 89 | { |
139ec7c4 RR |
90 | __u32 *lp = (__u32 *)((char *)dt + entry*8); |
91 | *lp = entry_a; | |
92 | *(lp+1) = entry_b; | |
1da177e4 LT |
93 | } |
94 | ||
d3561b7f RR |
95 | #define set_ldt native_set_ldt |
96 | #endif /* CONFIG_PARAVIRT */ | |
97 | ||
98 | static inline fastcall void native_set_ldt(const void *addr, | |
99 | unsigned int entries) | |
522e93e3 | 100 | { |
e5e3a042 JF |
101 | if (likely(entries == 0)) |
102 | __asm__ __volatile__("lldt %w0"::"q" (0)); | |
103 | else { | |
104 | unsigned cpu = smp_processor_id(); | |
105 | __u32 a, b; | |
106 | ||
107 | pack_descriptor(&a, &b, (unsigned long)addr, | |
108 | entries * sizeof(struct desc_struct) - 1, | |
109 | DESCTYPE_LDT, 0); | |
110 | write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, a, b); | |
111 | __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); | |
112 | } | |
522e93e3 RR |
113 | } |
114 | ||
139ec7c4 RR |
115 | static inline void _set_gate(int gate, unsigned int type, void *addr, unsigned short seg) |
116 | { | |
117 | __u32 a, b; | |
118 | pack_gate(&a, &b, (unsigned long)addr, seg, type, 0); | |
119 | write_idt_entry(idt_table, gate, a, b); | |
120 | } | |
121 | ||
122 | static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, const void *addr) | |
123 | { | |
124 | __u32 a, b; | |
125 | pack_descriptor(&a, &b, (unsigned long)addr, | |
126 | offsetof(struct tss_struct, __cacheline_filler) - 1, | |
127 | DESCTYPE_TSS, 0); | |
128 | write_gdt_entry(get_cpu_gdt_table(cpu), entry, a, b); | |
129 | } | |
130 | ||
131 | ||
522e93e3 RR |
132 | #define set_tss_desc(cpu,addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) |
133 | ||
1da177e4 LT |
134 | #define LDT_entry_a(info) \ |
135 | ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff)) | |
136 | ||
137 | #define LDT_entry_b(info) \ | |
138 | (((info)->base_addr & 0xff000000) | \ | |
139 | (((info)->base_addr & 0x00ff0000) >> 16) | \ | |
140 | ((info)->limit & 0xf0000) | \ | |
141 | (((info)->read_exec_only ^ 1) << 9) | \ | |
142 | ((info)->contents << 10) | \ | |
143 | (((info)->seg_not_present ^ 1) << 15) | \ | |
144 | ((info)->seg_32bit << 22) | \ | |
145 | ((info)->limit_in_pages << 23) | \ | |
146 | ((info)->useable << 20) | \ | |
147 | 0x7000) | |
148 | ||
149 | #define LDT_empty(info) (\ | |
150 | (info)->base_addr == 0 && \ | |
151 | (info)->limit == 0 && \ | |
152 | (info)->contents == 0 && \ | |
153 | (info)->read_exec_only == 1 && \ | |
154 | (info)->seg_32bit == 0 && \ | |
155 | (info)->limit_in_pages == 0 && \ | |
156 | (info)->seg_not_present == 1 && \ | |
157 | (info)->useable == 0 ) | |
158 | ||
1da177e4 LT |
159 | static inline void clear_LDT(void) |
160 | { | |
e5e3a042 | 161 | set_ldt(NULL, 0); |
1da177e4 LT |
162 | } |
163 | ||
164 | /* | |
165 | * load one particular LDT into the current CPU | |
166 | */ | |
e5e3a042 | 167 | static inline void load_LDT_nolock(mm_context_t *pc) |
1da177e4 | 168 | { |
e5e3a042 | 169 | set_ldt(pc->ldt, pc->size); |
1da177e4 LT |
170 | } |
171 | ||
172 | static inline void load_LDT(mm_context_t *pc) | |
173 | { | |
e5e3a042 JF |
174 | preempt_disable(); |
175 | load_LDT_nolock(pc); | |
176 | preempt_enable(); | |
1da177e4 LT |
177 | } |
178 | ||
179 | static inline unsigned long get_desc_base(unsigned long *desc) | |
180 | { | |
181 | unsigned long base; | |
182 | base = ((desc[0] >> 16) & 0x0000ffff) | | |
183 | ((desc[1] << 16) & 0x00ff0000) | | |
184 | (desc[1] & 0xff000000); | |
185 | return base; | |
186 | } | |
187 | ||
be44d2aa SS |
188 | #else /* __ASSEMBLY__ */ |
189 | ||
190 | /* | |
191 | * GET_DESC_BASE reads the descriptor base of the specified segment. | |
192 | * | |
193 | * Args: | |
194 | * idx - descriptor index | |
195 | * gdt - GDT pointer | |
196 | * base - 32bit register to which the base will be written | |
197 | * lo_w - lo word of the "base" register | |
198 | * lo_b - lo byte of the "base" register | |
199 | * hi_b - hi byte of the low word of the "base" register | |
200 | * | |
201 | * Example: | |
202 | * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah) | |
203 | * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax. | |
204 | */ | |
205 | #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \ | |
206 | movb idx*8+4(gdt), lo_b; \ | |
207 | movb idx*8+7(gdt), hi_b; \ | |
208 | shll $16, base; \ | |
209 | movw idx*8+2(gdt), lo_w; | |
210 | ||
1da177e4 LT |
211 | #endif /* !__ASSEMBLY__ */ |
212 | ||
213 | #endif |