[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-generic / io.h

/* Generic I/O port emulation, based on MN10300 code
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
#ifndef __ASM_GENERIC_IO_H
#define __ASM_GENERIC_IO_H

#include <asm/page.h> /* I/O is all done through memory accesses */
#include <linux/types.h>

#ifdef CONFIG_GENERIC_IOMAP
#include <asm-generic/iomap.h>
#endif

#include <asm-generic/pci_iomap.h>

#ifndef mmiowb
#define mmiowb() do {} while (0)
#endif

/*****************************************************************************/
/*
 * readX/writeX() are used to access memory mapped devices. On some
 * architectures the memory mapped IO stuff needs to be accessed
 * differently. On the simple architectures, we just read/write the
 * memory location directly.
 */
#ifndef __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	return *(const volatile u8 __force *) addr;
}
#endif

#ifndef __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	return *(const volatile u16 __force *) addr;
}
#endif

#ifndef __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	return *(const volatile u32 __force *) addr;
}
#endif

#define readb __raw_readb

#define readw readw
static inline u16 readw(const volatile void __iomem *addr)
{
	return __le16_to_cpu(__raw_readw(addr));
}

#define readl readl
static inline u32 readl(const volatile void __iomem *addr)
{
	return __le32_to_cpu(__raw_readl(addr));
}

#ifndef __raw_writeb
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
{
	*(volatile u8 __force *) addr = b;
}
#endif

#ifndef __raw_writew
static inline void __raw_writew(u16 b, volatile void __iomem *addr)
{
	*(volatile u16 __force *) addr = b;
}
#endif

#ifndef __raw_writel
static inline void __raw_writel(u32 b, volatile void __iomem *addr)
{
	*(volatile u32 __force *) addr = b;
}
#endif

#define writeb __raw_writeb
#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)

#ifdef CONFIG_64BIT
#ifndef __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	return *(const volatile u64 __force *) addr;
}
#endif

#define readq readq
static inline u64 readq(const volatile void __iomem *addr)
{
	return __le64_to_cpu(__raw_readq(addr));
}

#ifndef __raw_writeq
static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
{
	*(volatile u64 __force *) addr = b;
}
#endif

#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
#endif /* CONFIG_64BIT */

#ifndef PCI_IOBASE
#define PCI_IOBASE ((void __iomem *) 0)
#endif

/*****************************************************************************/
/*
 * traditional input/output functions
 */

static inline u8 inb(unsigned long addr)
{
	return readb(addr + PCI_IOBASE);
}

static inline u16 inw(unsigned long addr)
{
	return readw(addr + PCI_IOBASE);
}

static inline u32 inl(unsigned long addr)
{
	return readl(addr + PCI_IOBASE);
}

static inline void outb(u8 b, unsigned long addr)
{
	writeb(b, addr + PCI_IOBASE);
}

static inline void outw(u16 b, unsigned long addr)
{
	writew(b, addr + PCI_IOBASE);
}

static inline void outl(u32 b, unsigned long addr)
{
	writel(b, addr + PCI_IOBASE);
}

#define inb_p(addr)	inb(addr)
#define inw_p(addr)	inw(addr)
#define inl_p(addr)	inl(addr)
#define outb_p(x, addr)	outb((x), (addr))
#define outw_p(x, addr)	outw((x), (addr))
#define outl_p(x, addr)	outl((x), (addr))

#ifndef insb
static inline void insb(unsigned long addr, void *buffer, int count)
{
	if (count) {
		u8 *buf = buffer;
		do {
			u8 x = __raw_readb(addr + PCI_IOBASE);
			*buf++ = x;
		} while (--count);
	}
}
#endif

#ifndef insw
static inline void insw(unsigned long addr, void *buffer, int count)
{
	if (count) {
		u16 *buf = buffer;
		do {
			u16 x = __raw_readw(addr + PCI_IOBASE);
			*buf++ = x;
		} while (--count);
	}
}
#endif

#ifndef insl
static inline void insl(unsigned long addr, void *buffer, int count)
{
	if (count) {
		u32 *buf = buffer;
		do {
			u32 x = __raw_readl(addr + PCI_IOBASE);
			*buf++ = x;
		} while (--count);
	}
}
#endif

#ifndef outsb
static inline void outsb(unsigned long addr, const void *buffer, int count)
{
	if (count) {
		const u8 *buf = buffer;
		do {
			__raw_writeb(*buf++, addr + PCI_IOBASE);
		} while (--count);
	}
}
#endif

#ifndef outsw
static inline void outsw(unsigned long addr, const void *buffer, int count)
{
	if (count) {
		const u16 *buf = buffer;
		do {
			__raw_writew(*buf++, addr + PCI_IOBASE);
		} while (--count);
	}
}
#endif

#ifndef outsl
static inline void outsl(unsigned long addr, const void *buffer, int count)
{
	if (count) {
		const u32 *buf = buffer;
		do {
			__raw_writel(*buf++, addr + PCI_IOBASE);
		} while (--count);
	}
}
#endif

#ifndef CONFIG_GENERIC_IOMAP
#define ioread8(addr)		readb(addr)
#define ioread16(addr)		readw(addr)
#define ioread16be(addr)	__be16_to_cpu(__raw_readw(addr))
#define ioread32(addr)		readl(addr)
#define ioread32be(addr)	__be32_to_cpu(__raw_readl(addr))

#define iowrite8(v, addr)	writeb((v), (addr))
#define iowrite16(v, addr)	writew((v), (addr))
#define iowrite16be(v, addr)	__raw_writew(__cpu_to_be16(v), addr)
#define iowrite32(v, addr)	writel((v), (addr))
#define iowrite32be(v, addr)	__raw_writel(__cpu_to_be32(v), addr)

#define ioread8_rep(p, dst, count) \
	insb((unsigned long) (p), (dst), (count))
#define ioread16_rep(p, dst, count) \
	insw((unsigned long) (p), (dst), (count))
#define ioread32_rep(p, dst, count) \
	insl((unsigned long) (p), (dst), (count))

#define iowrite8_rep(p, src, count) \
	outsb((unsigned long) (p), (src), (count))
#define iowrite16_rep(p, src, count) \
	outsw((unsigned long) (p), (src), (count))
#define iowrite32_rep(p, src, count) \
	outsl((unsigned long) (p), (src), (count))
#endif /* CONFIG_GENERIC_IOMAP */

#ifndef IO_SPACE_LIMIT
#define IO_SPACE_LIMIT 0xffff
#endif

#ifdef __KERNEL__

#include <linux/vmalloc.h>
#define __io_virt(x) ((void __force *) (x))

#ifndef CONFIG_GENERIC_IOMAP
struct pci_dev;
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);

#ifndef pci_iounmap
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
{
}
#endif
#endif /* CONFIG_GENERIC_IOMAP */

/*
 * Change virtual addresses to physical addresses and vv.
 * These are pretty trivial
 */
#ifndef virt_to_phys
static inline unsigned long virt_to_phys(volatile void *address)
{
	return __pa((unsigned long)address);
}

static inline void *phys_to_virt(unsigned long address)
{
	return __va(address);
}
#endif

/*
 * Change "struct page" to physical address.
 *
 * This implementation is for the no-MMU case only... if you have an MMU
 * you'll need to provide your own definitions.
 */
#ifndef CONFIG_MMU
static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
{
	return (void __iomem*) (unsigned long)offset;
}

#define __ioremap(offset, size, flags)	ioremap(offset, size)

#ifndef ioremap_nocache
#define ioremap_nocache ioremap
#endif

#ifndef ioremap_wc
#define ioremap_wc ioremap_nocache
#endif

static inline void iounmap(void __iomem *addr)
{
}
#endif /* CONFIG_MMU */

#ifdef CONFIG_HAS_IOPORT
#ifndef CONFIG_GENERIC_IOMAP
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
	return (void __iomem *) port;
}

static inline void ioport_unmap(void __iomem *p)
{
}
#else /* CONFIG_GENERIC_IOMAP */
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *p);
#endif /* CONFIG_GENERIC_IOMAP */
#endif /* CONFIG_HAS_IOPORT */

#define xlate_dev_kmem_ptr(p)	p
#define xlate_dev_mem_ptr(p)	__va(p)

#ifdef CONFIG_VIRT_TO_BUS
#ifndef virt_to_bus
static inline unsigned long virt_to_bus(volatile void *address)
{
	return ((unsigned long) address);
}

static inline void *bus_to_virt(unsigned long address)
{
	return (void *) address;
}
#endif
#endif

#ifndef memset_io
#define memset_io(a, b, c)	memset(__io_virt(a), (b), (c))
#endif

#ifndef memcpy_fromio
#define memcpy_fromio(a, b, c)	memcpy((a), __io_virt(b), (c))
#endif
#ifndef memcpy_toio
#define memcpy_toio(a, b, c)	memcpy(__io_virt(a), (b), (c))
#endif

#endif /* __KERNEL__ */

#endif /* __ASM_GENERIC_IO_H */
Commit	Line	Data
3f7e212d AB	1	/* Generic I/O port emulation, based on MN10300 code
	2	*
	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
	4	* Written by David Howells (dhowells@redhat.com)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public Licence
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the Licence, or (at your option) any later version.
	10	*/
	11	#ifndef __ASM_GENERIC_IO_H
	12	#define __ASM_GENERIC_IO_H
	13
	14	#include <asm/page.h> /* I/O is all done through memory accesses */
3f7e212d AB	15	#include <linux/types.h>
	16
	17	#ifdef CONFIG_GENERIC_IOMAP
	18	#include <asm-generic/iomap.h>
	19	#endif
	20
66eab4df MT	21	#include <asm-generic/pci_iomap.h>
66eab4df MT	22
35dbc0e0	23	#ifndef mmiowb
3f7e212d	24	#define mmiowb() do {} while (0)
35dbc0e0	25	#endif
3f7e212d AB	26
	27	/*****************************************************************************/
	28	/*
	29	* readX/writeX() are used to access memory mapped devices. On some
	30	* architectures the memory mapped IO stuff needs to be accessed
	31	* differently. On the simple architectures, we just read/write the
	32	* memory location directly.
	33	*/
35dbc0e0	34	#ifndef __raw_readb
3f7e212d AB	35	static inline u8 __raw_readb(const volatile void __iomem *addr)
	36	{
	37	return (const volatile u8 __force ) addr;
	38	}
35dbc0e0	39	#endif
3f7e212d	40
35dbc0e0	41	#ifndef __raw_readw
3f7e212d AB	42	static inline u16 __raw_readw(const volatile void __iomem *addr)
	43	{
	44	return (const volatile u16 __force ) addr;
	45	}
35dbc0e0	46	#endif
3f7e212d	47
35dbc0e0	48	#ifndef __raw_readl
3f7e212d AB	49	static inline u32 __raw_readl(const volatile void __iomem *addr)
	50	{
	51	return (const volatile u32 __force ) addr;
	52	}
35dbc0e0	53	#endif
3f7e212d AB	54
3f7e212d AB	55	#define readb __raw_readb
7292e7e0 HC	56
	57	#define readw readw
	58	static inline u16 readw(const volatile void __iomem *addr)
	59	{
	60	return __le16_to_cpu(__raw_readw(addr));
	61	}
	62
	63	#define readl readl
	64	static inline u32 readl(const volatile void __iomem *addr)
	65	{
	66	return __le32_to_cpu(__raw_readl(addr));
	67	}
3f7e212d	68
35dbc0e0	69	#ifndef __raw_writeb
3f7e212d AB	70	static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
	71	{
	72	(volatile u8 __force ) addr = b;
	73	}
35dbc0e0	74	#endif
3f7e212d	75
35dbc0e0	76	#ifndef __raw_writew
3f7e212d AB	77	static inline void __raw_writew(u16 b, volatile void __iomem *addr)
	78	{
	79	(volatile u16 __force ) addr = b;
	80	}
35dbc0e0	81	#endif
3f7e212d	82
35dbc0e0	83	#ifndef __raw_writel
3f7e212d AB	84	static inline void __raw_writel(u32 b, volatile void __iomem *addr)
	85	{
	86	(volatile u32 __force ) addr = b;
	87	}
35dbc0e0	88	#endif
3f7e212d AB	89
	90	#define writeb __raw_writeb
	91	#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
	92	#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
	93
	94	#ifdef CONFIG_64BIT
cd248341	95	#ifndef __raw_readq
3f7e212d AB	96	static inline u64 __raw_readq(const volatile void __iomem *addr)
	97	{
	98	return (const volatile u64 __force ) addr;
	99	}
cd248341 JG	100	#endif
cd248341 JG	101
7292e7e0 HC	102	#define readq readq
	103	static inline u64 readq(const volatile void __iomem *addr)
	104	{
	105	return __le64_to_cpu(__raw_readq(addr));
	106	}
3f7e212d	107
cd248341	108	#ifndef __raw_writeq
3f7e212d AB	109	static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
	110	{
	111	(volatile u64 __force ) addr = b;
	112	}
3f7e212d AB	113	#endif
3f7e212d AB	114
cd248341 JG	115	#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
	116	#endif /* CONFIG_64BIT */
	117
7dc59bdd G	118	#ifndef PCI_IOBASE
	119	#define PCI_IOBASE ((void __iomem *) 0)
	120	#endif
	121
3f7e212d AB	122	/*****************************************************************************/
	123	/*
	124	* traditional input/output functions
	125	*/
	126
	127	static inline u8 inb(unsigned long addr)
	128	{
7dc59bdd	129	return readb(addr + PCI_IOBASE);
3f7e212d AB	130	}
	131
	132	static inline u16 inw(unsigned long addr)
	133	{
7dc59bdd	134	return readw(addr + PCI_IOBASE);
3f7e212d AB	135	}
	136
	137	static inline u32 inl(unsigned long addr)
	138	{
7dc59bdd	139	return readl(addr + PCI_IOBASE);
3f7e212d AB	140	}
	141
	142	static inline void outb(u8 b, unsigned long addr)
	143	{
7dc59bdd	144	writeb(b, addr + PCI_IOBASE);
3f7e212d AB	145	}
	146
	147	static inline void outw(u16 b, unsigned long addr)
	148	{
7dc59bdd	149	writew(b, addr + PCI_IOBASE);
3f7e212d AB	150	}
	151
	152	static inline void outl(u32 b, unsigned long addr)
	153	{
7dc59bdd	154	writel(b, addr + PCI_IOBASE);
3f7e212d AB	155	}
	156
	157	#define inb_p(addr) inb(addr)
	158	#define inw_p(addr) inw(addr)
	159	#define inl_p(addr) inl(addr)
	160	#define outb_p(x, addr) outb((x), (addr))
	161	#define outw_p(x, addr) outw((x), (addr))
	162	#define outl_p(x, addr) outl((x), (addr))
	163
35dbc0e0	164	#ifndef insb
3f7e212d AB	165	static inline void insb(unsigned long addr, void *buffer, int count)
	166	{
	167	if (count) {
	168	u8 *buf = buffer;
	169	do {
41739ee3	170	u8 x = __raw_readb(addr + PCI_IOBASE);
3f7e212d AB	171	*buf++ = x;
	172	} while (--count);
	173	}
	174	}
35dbc0e0	175	#endif
3f7e212d	176
35dbc0e0	177	#ifndef insw
3f7e212d AB	178	static inline void insw(unsigned long addr, void *buffer, int count)
	179	{
	180	if (count) {
	181	u16 *buf = buffer;
	182	do {
41739ee3	183	u16 x = __raw_readw(addr + PCI_IOBASE);
3f7e212d AB	184	*buf++ = x;
	185	} while (--count);
	186	}
	187	}
35dbc0e0	188	#endif
3f7e212d	189
35dbc0e0	190	#ifndef insl
3f7e212d AB	191	static inline void insl(unsigned long addr, void *buffer, int count)
	192	{
	193	if (count) {
	194	u32 *buf = buffer;
	195	do {
41739ee3	196	u32 x = __raw_readl(addr + PCI_IOBASE);
3f7e212d AB	197	*buf++ = x;
	198	} while (--count);
	199	}
	200	}
35dbc0e0	201	#endif
3f7e212d	202
35dbc0e0	203	#ifndef outsb
3f7e212d AB	204	static inline void outsb(unsigned long addr, const void *buffer, int count)
	205	{
	206	if (count) {
	207	const u8 *buf = buffer;
	208	do {
41739ee3	209	__raw_writeb(*buf++, addr + PCI_IOBASE);
3f7e212d AB	210	} while (--count);
	211	}
	212	}
35dbc0e0	213	#endif
3f7e212d	214
35dbc0e0	215	#ifndef outsw
3f7e212d AB	216	static inline void outsw(unsigned long addr, const void *buffer, int count)
	217	{
	218	if (count) {
	219	const u16 *buf = buffer;
	220	do {
41739ee3	221	__raw_writew(*buf++, addr + PCI_IOBASE);
3f7e212d AB	222	} while (--count);
	223	}
	224	}
35dbc0e0	225	#endif
3f7e212d	226
35dbc0e0	227	#ifndef outsl
3f7e212d AB	228	static inline void outsl(unsigned long addr, const void *buffer, int count)
	229	{
	230	if (count) {
	231	const u32 *buf = buffer;
	232	do {
41739ee3	233	__raw_writel(*buf++, addr + PCI_IOBASE);
3f7e212d AB	234	} while (--count);
	235	}
	236	}
35dbc0e0	237	#endif
3f7e212d AB	238
	239	#ifndef CONFIG_GENERIC_IOMAP
	240	#define ioread8(addr) readb(addr)
	241	#define ioread16(addr) readw(addr)
711e5b45	242	#define ioread16be(addr) __be16_to_cpu(__raw_readw(addr))
3f7e212d	243	#define ioread32(addr) readl(addr)
711e5b45	244	#define ioread32be(addr) __be32_to_cpu(__raw_readl(addr))
3f7e212d AB	245
	246	#define iowrite8(v, addr) writeb((v), (addr))
	247	#define iowrite16(v, addr) writew((v), (addr))
711e5b45	248	#define iowrite16be(v, addr) __raw_writew(__cpu_to_be16(v), addr)
3f7e212d	249	#define iowrite32(v, addr) writel((v), (addr))
711e5b45	250	#define iowrite32be(v, addr) __raw_writel(__cpu_to_be32(v), addr)
3f7e212d AB	251
	252	#define ioread8_rep(p, dst, count) \
	253	insb((unsigned long) (p), (dst), (count))
	254	#define ioread16_rep(p, dst, count) \
	255	insw((unsigned long) (p), (dst), (count))
	256	#define ioread32_rep(p, dst, count) \
	257	insl((unsigned long) (p), (dst), (count))
	258
	259	#define iowrite8_rep(p, src, count) \
	260	outsb((unsigned long) (p), (src), (count))
	261	#define iowrite16_rep(p, src, count) \
	262	outsw((unsigned long) (p), (src), (count))
	263	#define iowrite32_rep(p, src, count) \
	264	outsl((unsigned long) (p), (src), (count))
	265	#endif /* CONFIG_GENERIC_IOMAP */
	266
7dc59bdd G	267	#ifndef IO_SPACE_LIMIT
	268	#define IO_SPACE_LIMIT 0xffff
	269	#endif
3f7e212d AB	270
	271	#ifdef __KERNEL__
	272
	273	#include <linux/vmalloc.h>
	274	#define __io_virt(x) ((void __force *) (x))
	275
	276	#ifndef CONFIG_GENERIC_IOMAP
3f7e212d	277	struct pci_dev;
cd248341 JG	278	extern void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long max);
	279
	280	#ifndef pci_iounmap
3f7e212d AB	281	static inline void pci_iounmap(struct pci_dev dev, void __iomem p)
	282	{
	283	}
cd248341	284	#endif
3f7e212d AB	285	#endif /* CONFIG_GENERIC_IOMAP */
	286
	287	/*
	288	* Change virtual addresses to physical addresses and vv.
	289	* These are pretty trivial
	290	*/
cd248341	291	#ifndef virt_to_phys
3f7e212d AB	292	static inline unsigned long virt_to_phys(volatile void *address)
	293	{
	294	return __pa((unsigned long)address);
	295	}
	296
	297	static inline void *phys_to_virt(unsigned long address)
	298	{
	299	return __va(address);
	300	}
cd248341	301	#endif
3f7e212d AB	302
	303	/*
	304	* Change "struct page" to physical address.
f1ecc698 JB	305	*
	306	* This implementation is for the no-MMU case only... if you have an MMU
	307	* you'll need to provide your own definitions.
3f7e212d	308	*/
f1ecc698	309	#ifndef CONFIG_MMU
3f7e212d AB	310	static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
	311	{
	312	return (void __iomem*) (unsigned long)offset;
	313	}
	314
	315	#define __ioremap(offset, size, flags) ioremap(offset, size)
	316
	317	#ifndef ioremap_nocache
	318	#define ioremap_nocache ioremap
	319	#endif
	320
	321	#ifndef ioremap_wc
	322	#define ioremap_wc ioremap_nocache
	323	#endif
	324
e66d3c49	325	static inline void iounmap(void __iomem *addr)
3f7e212d AB	326	{
3f7e212d AB	327	}
f1ecc698	328	#endif /* CONFIG_MMU */
3f7e212d	329
82ed223c	330	#ifdef CONFIG_HAS_IOPORT
3f7e212d AB	331	#ifndef CONFIG_GENERIC_IOMAP
	332	static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
	333	{
	334	return (void __iomem *) port;
	335	}
	336
	337	static inline void ioport_unmap(void __iomem *p)
	338	{
	339	}
	340	#else /* CONFIG_GENERIC_IOMAP */
	341	extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
	342	extern void ioport_unmap(void __iomem *p);
	343	#endif /* CONFIG_GENERIC_IOMAP */
82ed223c	344	#endif /* CONFIG_HAS_IOPORT */
3f7e212d AB	345
3f7e212d AB	346	#define xlate_dev_kmem_ptr(p) p
f1ecc698	347	#define xlate_dev_mem_ptr(p) __va(p)
3f7e212d	348
c93d0312	349	#ifdef CONFIG_VIRT_TO_BUS
3f7e212d AB	350	#ifndef virt_to_bus
	351	static inline unsigned long virt_to_bus(volatile void *address)
	352	{
	353	return ((unsigned long) address);
	354	}
	355
	356	static inline void *bus_to_virt(unsigned long address)
	357	{
	358	return (void *) address;
	359	}
	360	#endif
c93d0312	361	#endif
3f7e212d	362
cd248341	363	#ifndef memset_io
3f7e212d	364	#define memset_io(a, b, c) memset(__io_virt(a), (b), (c))
cd248341 JG	365	#endif
	366
	367	#ifndef memcpy_fromio
3f7e212d	368	#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c))
cd248341 JG	369	#endif
cd248341 JG	370	#ifndef memcpy_toio
3f7e212d	371	#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c))
cd248341	372	#endif
3f7e212d AB	373
	374	#endif /* __KERNEL__ */
	375
	376	#endif /* __ASM_GENERIC_IO_H */