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fmvj18x_cs: write interrupt ack bit for lan and modem to work simultaneously.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-cris / arch-v32 / hwregs / sser_defs.h
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MS		 1#ifndef __sser_defs_h
2#define __sser_defs_h
3
4/*
5 * This file is autogenerated from
6 * file: ../../inst/syncser/rtl/sser_regs.r
7 * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
8 * last modfied: Mon Apr 11 16:09:48 2005
9 *
10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
11 * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
12 * Any changes here will be lost.
13 *
14 * -*- buffer-read-only: t -*-
15 */
16/* Main access macros */
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85/* C-code for register scope sser */
86
87/* Register rw_cfg, scope sser, type rw */
88typedef struct {
89 unsigned int clk_div : 16;
90 unsigned int base_freq : 3;
91 unsigned int gate_clk : 1;
92 unsigned int clkgate_ctrl : 1;
93 unsigned int clkgate_in : 1;
94 unsigned int clk_dir : 1;
95 unsigned int clk_od_mode : 1;
96 unsigned int out_clk_pol : 1;
97 unsigned int out_clk_src : 2;
98 unsigned int clk_in_sel : 1;
99 unsigned int hold_pol : 1;
100 unsigned int prepare : 1;
101 unsigned int en : 1;
102 unsigned int dummy1 : 1;
103} reg_sser_rw_cfg;
104#define REG_RD_ADDR_sser_rw_cfg 0
105#define REG_WR_ADDR_sser_rw_cfg 0
106
107/* Register rw_frm_cfg, scope sser, type rw */
108typedef struct {
109 unsigned int wordrate : 10;
110 unsigned int rec_delay : 3;
111 unsigned int tr_delay : 3;
112 unsigned int early_wend : 1;
113 unsigned int level : 2;
114 unsigned int type : 1;
115 unsigned int clk_pol : 1;
116 unsigned int fr_in_rxclk : 1;
117 unsigned int clk_src : 1;
118 unsigned int out_off : 1;
119 unsigned int out_on : 1;
120 unsigned int frame_pin_dir : 1;
121 unsigned int frame_pin_use : 2;
122 unsigned int status_pin_dir : 1;
123 unsigned int status_pin_use : 2;
124 unsigned int dummy1 : 1;
125} reg_sser_rw_frm_cfg;
126#define REG_RD_ADDR_sser_rw_frm_cfg 4
127#define REG_WR_ADDR_sser_rw_frm_cfg 4
128
129/* Register rw_tr_cfg, scope sser, type rw */
130typedef struct {
131 unsigned int tr_en : 1;
132 unsigned int stop : 1;
133 unsigned int urun_stop : 1;
134 unsigned int eop_stop : 1;
135 unsigned int sample_size : 6;
136 unsigned int sh_dir : 1;
137 unsigned int clk_pol : 1;
138 unsigned int clk_src : 1;
139 unsigned int use_dma : 1;
140 unsigned int mode : 2;
141 unsigned int frm_src : 1;
142 unsigned int use60958 : 1;
143 unsigned int iec60958_ckdiv : 2;
144 unsigned int rate_ctrl : 1;
145 unsigned int use_md : 1;
146 unsigned int dual_i2s : 1;
147 unsigned int data_pin_use : 2;
148 unsigned int od_mode : 1;
149 unsigned int bulk_wspace : 2;
150 unsigned int dummy1 : 4;
151} reg_sser_rw_tr_cfg;
152#define REG_RD_ADDR_sser_rw_tr_cfg 8
153#define REG_WR_ADDR_sser_rw_tr_cfg 8
154
155/* Register rw_rec_cfg, scope sser, type rw */
156typedef struct {
157 unsigned int rec_en : 1;
158 unsigned int force_eop : 1;
159 unsigned int stop : 1;
160 unsigned int orun_stop : 1;
161 unsigned int eop_stop : 1;
162 unsigned int sample_size : 6;
163 unsigned int sh_dir : 1;
164 unsigned int clk_pol : 1;
165 unsigned int clk_src : 1;
166 unsigned int use_dma : 1;
167 unsigned int mode : 2;
168 unsigned int frm_src : 2;
169 unsigned int use60958 : 1;
170 unsigned int iec60958_ui_len : 5;
171 unsigned int slave2_en : 1;
172 unsigned int slave3_en : 1;
173 unsigned int fifo_thr : 2;
174 unsigned int dummy1 : 3;
175} reg_sser_rw_rec_cfg;
176#define REG_RD_ADDR_sser_rw_rec_cfg 12
177#define REG_WR_ADDR_sser_rw_rec_cfg 12
178
179/* Register rw_tr_data, scope sser, type rw */
180typedef struct {
181 unsigned int data : 16;
182 unsigned int md : 1;
183 unsigned int dummy1 : 15;
184} reg_sser_rw_tr_data;
185#define REG_RD_ADDR_sser_rw_tr_data 16
186#define REG_WR_ADDR_sser_rw_tr_data 16
187
188/* Register r_rec_data, scope sser, type r */
189typedef struct {
190 unsigned int data : 16;
191 unsigned int md : 1;
192 unsigned int ext_clk : 1;
193 unsigned int status_in : 1;
194 unsigned int frame_in : 1;
195 unsigned int din : 1;
196 unsigned int data_in : 1;
197 unsigned int clk_in : 1;
198 unsigned int dummy1 : 9;
199} reg_sser_r_rec_data;
200#define REG_RD_ADDR_sser_r_rec_data 20
201
202/* Register rw_extra, scope sser, type rw */
203typedef struct {
204 unsigned int clkoff_cycles : 20;
205 unsigned int clkoff_en : 1;
206 unsigned int clkon_en : 1;
207 unsigned int dout_delay : 5;
208 unsigned int dummy1 : 5;
209} reg_sser_rw_extra;
210#define REG_RD_ADDR_sser_rw_extra 24
211#define REG_WR_ADDR_sser_rw_extra 24
212
213/* Register rw_intr_mask, scope sser, type rw */
214typedef struct {
215 unsigned int trdy : 1;
216 unsigned int rdav : 1;
217 unsigned int tidle : 1;
218 unsigned int rstop : 1;
219 unsigned int urun : 1;
220 unsigned int orun : 1;
221 unsigned int md_rec : 1;
222 unsigned int md_sent : 1;
223 unsigned int r958err : 1;
224 unsigned int dummy1 : 23;
225} reg_sser_rw_intr_mask;
226#define REG_RD_ADDR_sser_rw_intr_mask 28
227#define REG_WR_ADDR_sser_rw_intr_mask 28
228
229/* Register rw_ack_intr, scope sser, type rw */
230typedef struct {
231 unsigned int trdy : 1;
232 unsigned int rdav : 1;
233 unsigned int tidle : 1;
234 unsigned int rstop : 1;
235 unsigned int urun : 1;
236 unsigned int orun : 1;
237 unsigned int md_rec : 1;
238 unsigned int md_sent : 1;
239 unsigned int r958err : 1;
240 unsigned int dummy1 : 23;
241} reg_sser_rw_ack_intr;
242#define REG_RD_ADDR_sser_rw_ack_intr 32
243#define REG_WR_ADDR_sser_rw_ack_intr 32
244
245/* Register r_intr, scope sser, type r */
246typedef struct {
247 unsigned int trdy : 1;
248 unsigned int rdav : 1;
249 unsigned int tidle : 1;
250 unsigned int rstop : 1;
251 unsigned int urun : 1;
252 unsigned int orun : 1;
253 unsigned int md_rec : 1;
254 unsigned int md_sent : 1;
255 unsigned int r958err : 1;
256 unsigned int dummy1 : 23;
257} reg_sser_r_intr;
258#define REG_RD_ADDR_sser_r_intr 36
259
260/* Register r_masked_intr, scope sser, type r */
261typedef struct {
262 unsigned int trdy : 1;
263 unsigned int rdav : 1;
264 unsigned int tidle : 1;
265 unsigned int rstop : 1;
266 unsigned int urun : 1;
267 unsigned int orun : 1;
268 unsigned int md_rec : 1;
269 unsigned int md_sent : 1;
270 unsigned int r958err : 1;
271 unsigned int dummy1 : 23;
272} reg_sser_r_masked_intr;
273#define REG_RD_ADDR_sser_r_masked_intr 40
274
275
276/* Constants */
277enum {
278 regk_sser_both = 0x00000002,
279 regk_sser_bulk = 0x00000001,
280 regk_sser_clk100 = 0x00000000,
281 regk_sser_clk_in = 0x00000000,
282 regk_sser_const0 = 0x00000003,
283 regk_sser_dout = 0x00000002,
284 regk_sser_edge = 0x00000000,
285 regk_sser_ext = 0x00000001,
286 regk_sser_ext_clk = 0x00000001,
287 regk_sser_f100 = 0x00000000,
288 regk_sser_f29_493 = 0x00000004,
289 regk_sser_f32 = 0x00000005,
290 regk_sser_f32_768 = 0x00000006,
291 regk_sser_frm = 0x00000003,
292 regk_sser_gio0 = 0x00000000,
293 regk_sser_gio1 = 0x00000001,
294 regk_sser_hispeed = 0x00000001,
295 regk_sser_hold = 0x00000002,
296 regk_sser_in = 0x00000000,
297 regk_sser_inf = 0x00000003,
298 regk_sser_intern = 0x00000000,
299 regk_sser_intern_clk = 0x00000001,
300 regk_sser_intern_tb = 0x00000000,
301 regk_sser_iso = 0x00000000,
302 regk_sser_level = 0x00000001,
303 regk_sser_lospeed = 0x00000000,
304 regk_sser_lsbfirst = 0x00000000,
305 regk_sser_msbfirst = 0x00000001,
306 regk_sser_neg = 0x00000001,
307 regk_sser_neg_lo = 0x00000000,
308 regk_sser_no = 0x00000000,
309 regk_sser_no_clk = 0x00000007,
310 regk_sser_nojitter = 0x00000002,
311 regk_sser_out = 0x00000001,
312 regk_sser_pos = 0x00000000,
313 regk_sser_pos_hi = 0x00000001,
314 regk_sser_rec = 0x00000000,
315 regk_sser_rw_cfg_default = 0x00000000,
316 regk_sser_rw_extra_default = 0x00000000,
317 regk_sser_rw_frm_cfg_default = 0x00000000,
318 regk_sser_rw_intr_mask_default = 0x00000000,
319 regk_sser_rw_rec_cfg_default = 0x00000000,
320 regk_sser_rw_tr_cfg_default = 0x01800000,
321 regk_sser_rw_tr_data_default = 0x00000000,
322 regk_sser_thr16 = 0x00000001,
323 regk_sser_thr32 = 0x00000002,
324 regk_sser_thr8 = 0x00000000,
325 regk_sser_tr = 0x00000001,
326 regk_sser_ts_out = 0x00000003,
327 regk_sser_tx_bulk = 0x00000002,
328 regk_sser_wiresave = 0x00000002,
329 regk_sser_yes = 0x00000001
330};
331#endif /* __sser_defs_h */
kernel source for telekom puls (alcatel/mediatek)