Commit | Line | Data |
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1da177e4 LT |
1 | #ifndef __ASM_ARM_SYSTEM_H |
2 | #define __ASM_ARM_SYSTEM_H | |
3 | ||
4 | #ifdef __KERNEL__ | |
5 | ||
398e692f | 6 | #include <asm/memory.h> |
1da177e4 LT |
7 | |
8 | #define CPU_ARCH_UNKNOWN 0 | |
9 | #define CPU_ARCH_ARMv3 1 | |
10 | #define CPU_ARCH_ARMv4 2 | |
11 | #define CPU_ARCH_ARMv4T 3 | |
12 | #define CPU_ARCH_ARMv5 4 | |
13 | #define CPU_ARCH_ARMv5T 5 | |
14 | #define CPU_ARCH_ARMv5TE 6 | |
15 | #define CPU_ARCH_ARMv5TEJ 7 | |
16 | #define CPU_ARCH_ARMv6 8 | |
17 | ||
18 | /* | |
19 | * CR1 bits (CP#15 CR1) | |
20 | */ | |
21 | #define CR_M (1 << 0) /* MMU enable */ | |
22 | #define CR_A (1 << 1) /* Alignment abort enable */ | |
23 | #define CR_C (1 << 2) /* Dcache enable */ | |
24 | #define CR_W (1 << 3) /* Write buffer enable */ | |
25 | #define CR_P (1 << 4) /* 32-bit exception handler */ | |
26 | #define CR_D (1 << 5) /* 32-bit data address range */ | |
27 | #define CR_L (1 << 6) /* Implementation defined */ | |
28 | #define CR_B (1 << 7) /* Big endian */ | |
29 | #define CR_S (1 << 8) /* System MMU protection */ | |
30 | #define CR_R (1 << 9) /* ROM MMU protection */ | |
31 | #define CR_F (1 << 10) /* Implementation defined */ | |
32 | #define CR_Z (1 << 11) /* Implementation defined */ | |
33 | #define CR_I (1 << 12) /* Icache enable */ | |
34 | #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ | |
35 | #define CR_RR (1 << 14) /* Round Robin cache replacement */ | |
36 | #define CR_L4 (1 << 15) /* LDR pc can set T bit */ | |
37 | #define CR_DT (1 << 16) | |
38 | #define CR_IT (1 << 18) | |
39 | #define CR_ST (1 << 19) | |
40 | #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ | |
41 | #define CR_U (1 << 22) /* Unaligned access operation */ | |
42 | #define CR_XP (1 << 23) /* Extended page tables */ | |
43 | #define CR_VE (1 << 24) /* Vectored interrupts */ | |
44 | ||
45 | #define CPUID_ID 0 | |
46 | #define CPUID_CACHETYPE 1 | |
47 | #define CPUID_TCM 2 | |
48 | #define CPUID_TLBTYPE 3 | |
49 | ||
f12d0d7c | 50 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
51 | #define read_cpuid(reg) \ |
52 | ({ \ | |
53 | unsigned int __val; \ | |
54 | asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ | |
55 | : "=r" (__val) \ | |
56 | : \ | |
57 | : "cc"); \ | |
58 | __val; \ | |
59 | }) | |
f12d0d7c HC |
60 | #else |
61 | #define read_cpuid(reg) (processor_id) | |
62 | #endif | |
1da177e4 LT |
63 | |
64 | /* | |
65 | * This is used to ensure the compiler did actually allocate the register we | |
66 | * asked it for some inline assembly sequences. Apparently we can't trust | |
67 | * the compiler from one version to another so a bit of paranoia won't hurt. | |
68 | * This string is meant to be concatenated with the inline asm string and | |
69 | * will cause compilation to stop on mismatch. | |
70 | * (for details, see gcc PR 15089) | |
71 | */ | |
72 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" | |
73 | ||
74 | #ifndef __ASSEMBLY__ | |
75 | ||
76 | #include <linux/linkage.h> | |
255d1f86 | 77 | #include <linux/irqflags.h> |
1da177e4 | 78 | |
7ab3f8d5 RK |
79 | #define __exception __attribute__((section(".exception.text"))) |
80 | ||
1da177e4 LT |
81 | struct thread_info; |
82 | struct task_struct; | |
83 | ||
84 | /* information about the system we're running on */ | |
85 | extern unsigned int system_rev; | |
86 | extern unsigned int system_serial_low; | |
87 | extern unsigned int system_serial_high; | |
88 | extern unsigned int mem_fclk_21285; | |
89 | ||
90 | struct pt_regs; | |
91 | ||
92 | void die(const char *msg, struct pt_regs *regs, int err) | |
93 | __attribute__((noreturn)); | |
94 | ||
cfb0810e RK |
95 | struct siginfo; |
96 | void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, | |
97 | unsigned long err, unsigned long trap); | |
1da177e4 LT |
98 | |
99 | void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, | |
100 | struct pt_regs *), | |
101 | int sig, const char *name); | |
102 | ||
1da177e4 LT |
103 | #define xchg(ptr,x) \ |
104 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
105 | ||
106 | #define tas(ptr) (xchg((ptr),1)) | |
107 | ||
108 | extern asmlinkage void __backtrace(void); | |
652a12ef | 109 | extern asmlinkage void c_backtrace(unsigned long fp, int pmode); |
5470dc65 RK |
110 | |
111 | struct mm_struct; | |
652a12ef RK |
112 | extern void show_pte(struct mm_struct *mm, unsigned long addr); |
113 | extern void __show_regs(struct pt_regs *); | |
1da177e4 LT |
114 | |
115 | extern int cpu_architecture(void); | |
36c5ed23 | 116 | extern void cpu_init(void); |
1da177e4 | 117 | |
74617fb6 RP |
118 | void arm_machine_restart(char mode); |
119 | extern void (*arm_pm_restart)(char str); | |
120 | ||
23bdf86a LB |
121 | /* |
122 | * Intel's XScale3 core supports some v6 features (supersections, L2) | |
123 | * but advertises itself as v5 as it does not support the v6 ISA. For | |
124 | * this reason, we need a way to explicitly test for this type of CPU. | |
125 | */ | |
126 | #ifndef CONFIG_CPU_XSC3 | |
127 | #define cpu_is_xsc3() 0 | |
128 | #else | |
129 | static inline int cpu_is_xsc3(void) | |
130 | { | |
131 | extern unsigned int processor_id; | |
132 | ||
133 | if ((processor_id & 0xffffe000) == 0x69056000) | |
134 | return 1; | |
135 | ||
136 | return 0; | |
137 | } | |
138 | #endif | |
139 | ||
5cedae9c DS |
140 | #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) |
141 | #define cpu_is_xscale() 0 | |
142 | #else | |
143 | #define cpu_is_xscale() 1 | |
144 | #endif | |
145 | ||
56660faf CM |
146 | #define UDBG_UNDEFINED (1 << 0) |
147 | #define UDBG_SYSCALL (1 << 1) | |
148 | #define UDBG_BADABORT (1 << 2) | |
149 | #define UDBG_SEGV (1 << 3) | |
150 | #define UDBG_BUS (1 << 4) | |
151 | ||
152 | extern unsigned int user_debug; | |
153 | ||
154 | #if __LINUX_ARM_ARCH__ >= 4 | |
155 | #define vectors_high() (cr_alignment & CR_V) | |
156 | #else | |
157 | #define vectors_high() (0) | |
158 | #endif | |
159 | ||
398e692f | 160 | #if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6 |
56660faf CM |
161 | #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
162 | : : "r" (0) : "memory") | |
163 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | |
164 | : : "r" (0) : "memory") | |
165 | #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ | |
166 | : : "r" (0) : "memory") | |
167 | #else | |
168 | #define isb() __asm__ __volatile__ ("" : : : "memory") | |
169 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | |
170 | : : "r" (0) : "memory") | |
171 | #define dmb() __asm__ __volatile__ ("" : : : "memory") | |
172 | #endif | |
9623b373 | 173 | |
398e692f LB |
174 | #ifndef CONFIG_SMP |
175 | #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | |
176 | #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | |
177 | #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | |
178 | #define smp_mb() barrier() | |
179 | #define smp_rmb() barrier() | |
180 | #define smp_wmb() barrier() | |
9623b373 | 181 | #else |
398e692f LB |
182 | #define mb() dmb() |
183 | #define rmb() dmb() | |
184 | #define wmb() dmb() | |
185 | #define smp_mb() dmb() | |
186 | #define smp_rmb() dmb() | |
187 | #define smp_wmb() dmb() | |
188 | #endif | |
189 | #define read_barrier_depends() do { } while(0) | |
190 | #define smp_read_barrier_depends() do { } while(0) | |
9623b373 CM |
191 | |
192 | #define set_mb(var, value) do { var = value; smp_mb(); } while (0) | |
56660faf CM |
193 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
194 | ||
255d1f86 RK |
195 | extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ |
196 | extern unsigned long cr_alignment; /* defined in entry-armv.S */ | |
197 | ||
efe90d27 RK |
198 | static inline unsigned int get_cr(void) |
199 | { | |
200 | unsigned int val; | |
201 | asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); | |
202 | return val; | |
203 | } | |
204 | ||
205 | static inline void set_cr(unsigned int val) | |
206 | { | |
207 | asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" | |
208 | : : "r" (val) : "cc"); | |
56660faf | 209 | isb(); |
efe90d27 RK |
210 | } |
211 | ||
255d1f86 RK |
212 | #ifndef CONFIG_SMP |
213 | extern void adjust_cr(unsigned long mask, unsigned long set); | |
214 | #endif | |
215 | ||
efe90d27 RK |
216 | #define CPACC_FULL(n) (3 << (n * 2)) |
217 | #define CPACC_SVC(n) (1 << (n * 2)) | |
218 | #define CPACC_DISABLE(n) (0 << (n * 2)) | |
219 | ||
220 | static inline unsigned int get_copro_access(void) | |
221 | { | |
222 | unsigned int val; | |
223 | asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" | |
224 | : "=r" (val) : : "cc"); | |
225 | return val; | |
226 | } | |
227 | ||
228 | static inline void set_copro_access(unsigned int val) | |
229 | { | |
230 | asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" | |
231 | : : "r" (val) : "cc"); | |
56660faf | 232 | isb(); |
efe90d27 | 233 | } |
1da177e4 | 234 | |
1da177e4 | 235 | /* |
4866cde0 NP |
236 | * switch_mm() may do a full cache flush over the context switch, |
237 | * so enable interrupts over the context switch to avoid high | |
238 | * latency. | |
1da177e4 | 239 | */ |
4866cde0 | 240 | #define __ARCH_WANT_INTERRUPTS_ON_CTXSW |
1da177e4 LT |
241 | |
242 | /* | |
243 | * switch_to(prev, next) should switch from task `prev' to `next' | |
244 | * `prev' will never be the same as `next'. schedule() itself | |
245 | * contains the memory barrier to tell GCC not to cache `current'. | |
246 | */ | |
247 | extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); | |
248 | ||
249 | #define switch_to(prev,next,last) \ | |
250 | do { \ | |
e7c1b32f | 251 | last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ |
1da177e4 LT |
252 | } while (0) |
253 | ||
4dc7a0bb IM |
254 | /* |
255 | * On SMP systems, when the scheduler does migration-cost autodetection, | |
256 | * it needs a way to flush as much of the CPU's caches as possible. | |
257 | * | |
258 | * TODO: fill this in! | |
259 | */ | |
260 | static inline void sched_cacheflush(void) | |
261 | { | |
262 | } | |
263 | ||
1da177e4 LT |
264 | #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) |
265 | /* | |
266 | * On the StrongARM, "swp" is terminally broken since it bypasses the | |
267 | * cache totally. This means that the cache becomes inconsistent, and, | |
268 | * since we use normal loads/stores as well, this is really bad. | |
269 | * Typically, this causes oopsen in filp_close, but could have other, | |
270 | * more disasterous effects. There are two work-arounds: | |
271 | * 1. Disable interrupts and emulate the atomic swap | |
272 | * 2. Clean the cache, perform atomic swap, flush the cache | |
273 | * | |
274 | * We choose (1) since its the "easiest" to achieve here and is not | |
275 | * dependent on the processor type. | |
053a7b5b RK |
276 | * |
277 | * NOTE that this solution won't work on an SMP system, so explcitly | |
278 | * forbid it here. | |
1da177e4 LT |
279 | */ |
280 | #define swp_is_buggy | |
281 | #endif | |
282 | ||
283 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | |
284 | { | |
285 | extern void __bad_xchg(volatile void *, int); | |
286 | unsigned long ret; | |
287 | #ifdef swp_is_buggy | |
288 | unsigned long flags; | |
289 | #endif | |
9560782f RK |
290 | #if __LINUX_ARM_ARCH__ >= 6 |
291 | unsigned int tmp; | |
292 | #endif | |
1da177e4 LT |
293 | |
294 | switch (size) { | |
9560782f RK |
295 | #if __LINUX_ARM_ARCH__ >= 6 |
296 | case 1: | |
297 | asm volatile("@ __xchg1\n" | |
298 | "1: ldrexb %0, [%3]\n" | |
299 | " strexb %1, %2, [%3]\n" | |
300 | " teq %1, #0\n" | |
301 | " bne 1b" | |
302 | : "=&r" (ret), "=&r" (tmp) | |
303 | : "r" (x), "r" (ptr) | |
304 | : "memory", "cc"); | |
305 | break; | |
306 | case 4: | |
307 | asm volatile("@ __xchg4\n" | |
308 | "1: ldrex %0, [%3]\n" | |
309 | " strex %1, %2, [%3]\n" | |
310 | " teq %1, #0\n" | |
311 | " bne 1b" | |
312 | : "=&r" (ret), "=&r" (tmp) | |
313 | : "r" (x), "r" (ptr) | |
314 | : "memory", "cc"); | |
315 | break; | |
316 | #elif defined(swp_is_buggy) | |
317 | #ifdef CONFIG_SMP | |
318 | #error SMP is not supported on this platform | |
319 | #endif | |
320 | case 1: | |
e7cc2c59 | 321 | raw_local_irq_save(flags); |
9560782f RK |
322 | ret = *(volatile unsigned char *)ptr; |
323 | *(volatile unsigned char *)ptr = x; | |
e7cc2c59 | 324 | raw_local_irq_restore(flags); |
9560782f RK |
325 | break; |
326 | ||
327 | case 4: | |
e7cc2c59 | 328 | raw_local_irq_save(flags); |
9560782f RK |
329 | ret = *(volatile unsigned long *)ptr; |
330 | *(volatile unsigned long *)ptr = x; | |
e7cc2c59 | 331 | raw_local_irq_restore(flags); |
9560782f | 332 | break; |
1da177e4 | 333 | #else |
9560782f RK |
334 | case 1: |
335 | asm volatile("@ __xchg1\n" | |
336 | " swpb %0, %1, [%2]" | |
337 | : "=&r" (ret) | |
338 | : "r" (x), "r" (ptr) | |
339 | : "memory", "cc"); | |
340 | break; | |
341 | case 4: | |
342 | asm volatile("@ __xchg4\n" | |
343 | " swp %0, %1, [%2]" | |
344 | : "=&r" (ret) | |
345 | : "r" (x), "r" (ptr) | |
346 | : "memory", "cc"); | |
347 | break; | |
1da177e4 | 348 | #endif |
9560782f RK |
349 | default: |
350 | __bad_xchg(ptr, size), ret = 0; | |
351 | break; | |
1da177e4 LT |
352 | } |
353 | ||
354 | return ret; | |
355 | } | |
356 | ||
dabaeff0 BD |
357 | extern void disable_hlt(void); |
358 | extern void enable_hlt(void); | |
359 | ||
1da177e4 LT |
360 | #endif /* __ASSEMBLY__ */ |
361 | ||
362 | #define arch_align_stack(x) (x) | |
363 | ||
364 | #endif /* __KERNEL__ */ | |
365 | ||
366 | #endif |