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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/arch-pxa/hardware.h | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_HARDWARE_H | |
14 | #define __ASM_ARCH_HARDWARE_H | |
15 | ||
16 | /* | |
17 | * We requires absolute addresses. | |
18 | */ | |
19 | #define PCIO_BASE 0 | |
20 | ||
21 | /* | |
22 | * Workarounds for at least 2 errata so far require this. | |
23 | * The mapping is set in mach-pxa/generic.c. | |
24 | */ | |
25 | #define UNCACHED_PHYS_0 0xff000000 | |
26 | #define UNCACHED_ADDR UNCACHED_PHYS_0 | |
27 | ||
28 | /* | |
29 | * Intel PXA2xx internal register mapping: | |
30 | * | |
31 | * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff | |
32 | * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff | |
33 | * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff | |
34 | * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff | |
35 | * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff | |
36 | * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff | |
37 | * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff | |
38 | * | |
39 | * Note that not all PXA2xx chips implement all those addresses, and the | |
40 | * kernel only maps the minimum needed range of this mapping. | |
41 | */ | |
42 | #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) | |
43 | #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) | |
44 | ||
45 | #ifndef __ASSEMBLY__ | |
46 | ||
63a4b52c | 47 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) |
1da177e4 LT |
48 | |
49 | /* With indexed regs we don't want to feed the index through io_p2v() | |
50 | especially if it is a variable, otherwise horrible code will result. */ | |
61c8c158 | 51 | # define __REG2(x,y) \ |
63a4b52c | 52 | (*(volatile u32 *)((u32)&__REG(x) + (y))) |
1da177e4 LT |
53 | |
54 | # define __PREG(x) (io_v2p((u32)&(x))) | |
55 | ||
56 | #else | |
57 | ||
58 | # define __REG(x) io_p2v(x) | |
59 | # define __PREG(x) io_v2p(x) | |
60 | ||
61 | #endif | |
62 | ||
63 | #ifndef __ASSEMBLY__ | |
64 | ||
b23170c0 RK |
65 | #define __cpu_is_pxa21x(id) \ |
66 | ({ \ | |
67 | unsigned int _id = (id) >> 4 & 0xf3f; \ | |
68 | _id == 0x212; \ | |
69 | }) | |
70 | ||
71 | #define __cpu_is_pxa25x(id) \ | |
72 | ({ \ | |
73 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
74 | _id == 0x2d0 || _id == 0x290; \ | |
75 | }) | |
76 | ||
77 | #define __cpu_is_pxa27x(id) \ | |
78 | ({ \ | |
79 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
80 | _id == 0x411; \ | |
81 | }) | |
82 | ||
cd272ab0 | 83 | #define __cpu_is_pxa300(id) \ |
84 | ({ \ | |
85 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
86 | _id == 0x688; \ | |
87 | }) | |
88 | ||
89 | #define __cpu_is_pxa310(id) \ | |
90 | ({ \ | |
91 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
92 | _id == 0x689; \ | |
93 | }) | |
94 | ||
95 | #define __cpu_is_pxa320(id) \ | |
96 | ({ \ | |
97 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
98 | _id == 0x603 || _id == 0x682; \ | |
99 | }) | |
100 | ||
b23170c0 RK |
101 | #define cpu_is_pxa21x() \ |
102 | ({ \ | |
103 | unsigned int id = read_cpuid(CPUID_ID); \ | |
104 | __cpu_is_pxa21x(id); \ | |
105 | }) | |
106 | ||
107 | #define cpu_is_pxa25x() \ | |
108 | ({ \ | |
109 | unsigned int id = read_cpuid(CPUID_ID); \ | |
110 | __cpu_is_pxa25x(id); \ | |
111 | }) | |
112 | ||
113 | #define cpu_is_pxa27x() \ | |
114 | ({ \ | |
115 | unsigned int id = read_cpuid(CPUID_ID); \ | |
116 | __cpu_is_pxa27x(id); \ | |
117 | }) | |
118 | ||
cd272ab0 | 119 | #define cpu_is_pxa300() \ |
120 | ({ \ | |
121 | unsigned int id = read_cpuid(CPUID_ID); \ | |
122 | __cpu_is_pxa300(id); \ | |
123 | }) | |
124 | ||
125 | #define cpu_is_pxa310() \ | |
126 | ({ \ | |
127 | unsigned int id = read_cpuid(CPUID_ID); \ | |
128 | __cpu_is_pxa310(id); \ | |
129 | }) | |
130 | ||
131 | #define cpu_is_pxa320() \ | |
132 | ({ \ | |
133 | unsigned int id = read_cpuid(CPUID_ID); \ | |
134 | __cpu_is_pxa320(id); \ | |
135 | }) | |
136 | ||
137 | /* | |
138 | * CPUID Core Generation Bit | |
139 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | |
140 | * == 0x3 for pxa300/pxa310/pxa320 | |
141 | */ | |
142 | #define __cpu_is_pxa2xx(id) \ | |
143 | ({ \ | |
144 | unsigned int _id = (id) >> 13 & 0x7; \ | |
145 | _id <= 0x2; \ | |
146 | }) | |
147 | ||
148 | #define __cpu_is_pxa3xx(id) \ | |
149 | ({ \ | |
150 | unsigned int _id = (id) >> 13 & 0x7; \ | |
151 | _id == 0x3; \ | |
152 | }) | |
153 | ||
154 | #define cpu_is_pxa2xx() \ | |
155 | ({ \ | |
156 | unsigned int id = read_cpuid(CPUID_ID); \ | |
157 | __cpu_is_pxa2xx(id); \ | |
158 | }) | |
159 | ||
160 | #define cpu_is_pxa3xx() \ | |
161 | ({ \ | |
162 | unsigned int id = read_cpuid(CPUID_ID); \ | |
163 | __cpu_is_pxa3xx(id); \ | |
164 | }) | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Handy routine to set GPIO alternate functions | |
168 | */ | |
3deac046 PZ |
169 | extern int pxa_gpio_mode( int gpio_mode ); |
170 | ||
171 | /* | |
172 | * Return GPIO level, nonzero means high, zero is low | |
173 | */ | |
174 | extern int pxa_gpio_get_value(unsigned gpio); | |
175 | ||
176 | /* | |
177 | * Set output GPIO level | |
178 | */ | |
179 | extern void pxa_gpio_set_value(unsigned gpio, int value); | |
1da177e4 LT |
180 | |
181 | /* | |
182 | * Routine to enable or disable CKEN | |
183 | */ | |
a7073b8b RK |
184 | static inline void __deprecated pxa_set_cken(int clock, int enable) |
185 | { | |
186 | extern void __pxa_set_cken(int clock, int enable); | |
187 | __pxa_set_cken(clock, enable); | |
188 | } | |
1da177e4 LT |
189 | |
190 | /* | |
191 | * return current memory and LCD clock frequency in units of 10kHz | |
192 | */ | |
193 | extern unsigned int get_memclk_frequency_10khz(void); | |
1da177e4 LT |
194 | |
195 | #endif | |
196 | ||
197 | #endif /* _ASM_ARCH_HARDWARE_H */ |