projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| c4713074 LB |
1 | /* |
| 2 | * include/asm-arm/arch-ixp23xx/ixdp2351.h | |
| 3 | * | |
| 4 | * Register and other defines for IXDP2351 | |
| 5 | * | |
| 6 | * Copyright (c) 2002-2004 Intel Corp. | |
| 7 | * Copytight (c) 2005 MontaVista Software, Inc. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify it | |
| 10 | * under the terms of the GNU General Public License as published by the | |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 12 | * option) any later version. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef __ASM_ARCH_IXDP2351_H | |
| 16 | #define __ASM_ARCH_IXDP2351_H | |
| 17 | ||
| 18 | /* | |
| 19 | * NP module memory map | |
| 20 | */ | |
| 21 | #define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE) | |
| 22 | #define IXDP2351_NP_PHYS_SIZE 0x00100000 | |
| 23 | #define IXDP2351_NP_VIRT_BASE 0xeff00000 | |
| 24 | ||
| 25 | #define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE) | |
| 26 | #define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16) | |
| 27 | ||
| 28 | #define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000) | |
| 29 | ||
| 30 | #define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg)) | |
| 31 | ||
| 32 | #define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00) | |
| 33 | #define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02) | |
| 34 | #define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04) | |
| 35 | ||
| 36 | /* | |
| 37 | * Base board module memory map | |
| 38 | */ | |
| 39 | ||
| 40 | #define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE) | |
| 41 | #define IXDP2351_BB_SIZE 0x01000000 | |
| 42 | #define IXDP2351_BB_BASE_VIRT (0xee000000) | |
| 43 | ||
| 44 | #define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset) | |
| 45 | ||
| 46 | #define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0) | |
| 47 | #define IXDP2351_NVRAM_SIZE (0x20000) | |
| 48 | ||
| 37985b44 | 49 | #define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000) |
| c4713074 LB |
50 | #define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0) |
| 51 | #define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000) | |
| 52 | #define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000) | |
| 53 | #define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000) | |
| 54 | #define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000) | |
| 55 | ||
| 56 | /* | |
| 57 | * On board CPLD registers | |
| 58 | */ | |
| 59 | #define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg)) | |
| 60 | ||
| 61 | #define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00) | |
| 62 | #define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04) | |
| 63 | ||
| 64 | #define IXDP2351_CPLD_RESET1_MAGIC 0x55AA | |
| 65 | #define IXDP2351_CPLD_RESET1_ENABLE 0x8000 | |
| 66 | ||
| 67 | #define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08) | |
| 68 | #define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10) | |
| 69 | #define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14) | |
| 70 | #define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18) | |
| 71 | #define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C) | |
| 72 | #define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */ | |
| 73 | #define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */ | |
| 74 | #define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */ | |
| 75 | #define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */ | |
| 76 | #define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28) | |
| 77 | #define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C) | |
| 78 | /* Interrupt bits are defined in irqs.h */ | |
| 79 | #define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30) | |
| 80 | #define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34) | |
| 81 | ||
| 82 | /* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */ | |
| 83 | /* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */ | |
| 84 | /* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */ | |
| 85 | /* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */ | |
| 86 | /* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */ | |
| 87 | ||
| 88 | ||
| 89 | #endif |