Commit | Line | Data |
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7f127d5e JS |
1 | ; Author: Frederik Noring <noring@nocrew.org> |
2 | ; | |
3 | ; This file is subject to the terms and conditions of the GNU General Public | |
4 | ; License. See the file COPYING in the main directory of this archive | |
5 | ; for more details. | |
6 | ||
7 | ; DSP56k loader | |
8 | ||
9 | ; Host Interface | |
10 | M_BCR EQU $FFFE ; Port A Bus Control Register | |
11 | M_PBC EQU $FFE0 ; Port B Control Register | |
12 | M_PBDDR EQU $FFE2 ; Port B Data Direction Register | |
13 | M_PBD EQU $FFE4 ; Port B Data Register | |
14 | M_PCC EQU $FFE1 ; Port C Control Register | |
15 | M_PCDDR EQU $FFE3 ; Port C Data Direction Register | |
16 | M_PCD EQU $FFE5 ; Port C Data Register | |
17 | ||
18 | M_HCR EQU $FFE8 ; Host Control Register | |
19 | M_HSR EQU $FFE9 ; Host Status Register | |
20 | M_HRX EQU $FFEB ; Host Receive Data Register | |
21 | M_HTX EQU $FFEB ; Host Transmit Data Register | |
22 | ||
23 | ; SSI, Synchronous Serial Interface | |
24 | M_RX EQU $FFEF ; Serial Receive Data Register | |
25 | M_TX EQU $FFEF ; Serial Transmit Data Register | |
26 | M_CRA EQU $FFEC ; SSI Control Register A | |
27 | M_CRB EQU $FFED ; SSI Control Register B | |
28 | M_SR EQU $FFEE ; SSI Status Register | |
29 | M_TSR EQU $FFEE ; SSI Time Slot Register | |
30 | ||
31 | ; Exception Processing | |
32 | M_IPR EQU $FFFF ; Interrupt Priority Register | |
33 | ||
34 | org P:$0 | |
35 | start jmp <$40 | |
36 | ||
37 | org P:$40 | |
38 | ; ; Zero 16384 DSP X and Y words | |
39 | ; clr A #0,r0 | |
40 | ; clr B #0,r4 | |
41 | ; do #64,<_block1 | |
42 | ; rep #256 | |
43 | ; move A,X:(r0)+ B,Y:(r4)+ | |
44 | ;_block1 ; Zero (32768-512) Program words | |
45 | ; clr A #512,r0 | |
46 | ; do #126,<_block2 | |
47 | ; rep #256 | |
48 | ; move A,P:(r0)+ | |
49 | ;_block2 | |
50 | ||
51 | ; Copy DSP program control | |
52 | move #real,r0 | |
53 | move #upload,r1 | |
842ffabb RM |
54 | do #upload_end-upload,_copy |
55 | movem P:(r0)+,x0 | |
56 | movem x0,P:(r1)+ | |
57 | _copy movep #4,X:<<M_HCR | |
58 | movep #$c00,X:<<M_IPR | |
7f127d5e JS |
59 | and #<$fe,mr |
60 | jmp upload | |
61 | ||
62 | real | |
63 | org P:$7ea9 | |
64 | upload | |
842ffabb RM |
65 | movep #1,X:<<M_PBC |
66 | movep #0,X:<<M_BCR | |
7f127d5e JS |
67 | |
68 | next jclr #0,X:<<M_HSR,* | |
69 | movep X:<<M_HRX,A | |
70 | move #>3,x0 | |
71 | cmp x0,A #>1,x0 | |
72 | jeq <$0 | |
73 | _get_address | |
74 | jclr #0,X:<<M_HSR,_get_address | |
75 | movep X:<<M_HRX,r0 | |
76 | _get_length | |
77 | jclr #0,X:<<M_HSR,_get_length | |
78 | movep X:<<M_HRX,y0 | |
79 | cmp x0,A #>2,x0 | |
80 | jeq load_X | |
81 | cmp x0,A | |
82 | jeq load_Y | |
83 | ||
842ffabb | 84 | load_P do y0,_load_P |
7f127d5e JS |
85 | jclr #0,X:<<M_HSR,* |
86 | movep X:<<M_HRX,P:(r0)+ | |
842ffabb RM |
87 | _load_P jmp next |
88 | load_X do y0,_load_X | |
7f127d5e JS |
89 | jclr #0,X:<<M_HSR,* |
90 | movep X:<<M_HRX,X:(r0)+ | |
842ffabb RM |
91 | _load_X jmp next |
92 | load_Y do y0,_load_Y | |
7f127d5e JS |
93 | jclr #0,X:<<M_HSR,* |
94 | movep X:<<M_HRX,Y:(r0)+ | |
842ffabb | 95 | _load_Y jmp next |
7f127d5e JS |
96 | |
97 | upload_end | |
98 | end |