drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / xen / events.c
CommitLineData
e46cdb66
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1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
25985edc 8 * chip. When an event is received, it is mapped to an irq and sent
e46cdb66
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9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
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20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
0ec53ecf 34#ifdef CONFIG_X86
38e20b07 35#include <asm/desc.h>
e46cdb66
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36#include <asm/ptrace.h>
37#include <asm/irq.h>
792dc4f6 38#include <asm/idle.h>
0794bfc7 39#include <asm/io_apic.h>
9846ff10 40#include <asm/xen/page.h>
42a1de56 41#include <asm/xen/pci.h>
0ec53ecf
SS
42#endif
43#include <asm/sync_bitops.h>
e46cdb66 44#include <asm/xen/hypercall.h>
8d1b8753 45#include <asm/xen/hypervisor.h>
e46cdb66 46
38e20b07
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47#include <xen/xen.h>
48#include <xen/hvm.h>
e04d0d07 49#include <xen/xen-ops.h>
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50#include <xen/events.h>
51#include <xen/interface/xen.h>
52#include <xen/interface/event_channel.h>
38e20b07
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53#include <xen/interface/hvm/hvm_op.h>
54#include <xen/interface/hvm/params.h>
0ec53ecf
SS
55#include <xen/interface/physdev.h>
56#include <xen/interface/sched.h>
57#include <asm/hw_irq.h>
e46cdb66 58
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59/*
60 * This lock protects updates to the following mapping and reference-count
61 * arrays. The lock does not need to be acquired to read the mapping tables.
62 */
77365948 63static DEFINE_MUTEX(irq_mapping_update_lock);
e46cdb66 64
6cb6537d
IC
65static LIST_HEAD(xen_irq_list_head);
66
e46cdb66 67/* IRQ <-> VIRQ mapping. */
204fba4a 68static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 69
f87e4cac 70/* IRQ <-> IPI mapping */
204fba4a 71static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 72
ced40d0f
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73/* Interrupt types. */
74enum xen_irq_type {
d77bbd4d 75 IRQT_UNBOUND = 0,
f87e4cac
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76 IRQT_PIRQ,
77 IRQT_VIRQ,
78 IRQT_IPI,
79 IRQT_EVTCHN
80};
e46cdb66 81
ced40d0f
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82/*
83 * Packed IRQ information:
84 * type - enum xen_irq_type
85 * event channel - irq->event channel mapping
86 * cpu - cpu this event channel is bound to
87 * index - type-specific information:
dec02dea 88 * PIRQ - physical IRQ, GSI, flags, and owner domain
ced40d0f
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89 * VIRQ - virq number
90 * IPI - IPI vector
91 * EVTCHN -
92 */
088c05a8 93struct irq_info {
6cb6537d 94 struct list_head list;
420eb554 95 int refcnt;
ced40d0f 96 enum xen_irq_type type; /* type */
6cb6537d 97 unsigned irq;
ced40d0f
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98 unsigned short evtchn; /* event channel */
99 unsigned short cpu; /* cpu bound */
100
101 union {
102 unsigned short virq;
103 enum ipi_vector ipi;
104 struct {
7a043f11 105 unsigned short pirq;
ced40d0f 106 unsigned short gsi;
d46a78b0 107 unsigned char flags;
beafbdc1 108 uint16_t domid;
ced40d0f
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109 } pirq;
110 } u;
111};
d46a78b0 112#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 113#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 114
b21ddbf5 115static int *evtchn_to_irq;
bf86ad80 116#ifdef CONFIG_X86
9846ff10 117static unsigned long *pirq_eoi_map;
bf86ad80 118#endif
9846ff10 119static bool (*pirq_needs_eoi)(unsigned irq);
3b32f574 120
c81611c4
IC
121/*
122 * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
123 * careful to only use bitops which allow for this (e.g
124 * test_bit/find_first_bit and friends but not __ffs) and to pass
125 * BITS_PER_EVTCHN_WORD as the bitmask length.
126 */
127#define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
128/*
129 * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
130 * array. Primarily to avoid long lines (hence the terse name).
131 */
132#define BM(x) (unsigned long *)(x)
133/* Find the first set bit in a evtchn mask */
134#define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
135
136static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
cb60d114 137 cpu_evtchn_mask);
e46cdb66 138
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139/* Xen will never allocate port zero for any purpose. */
140#define VALID_EVTCHN(chn) ((chn) != 0)
141
e46cdb66 142static struct irq_chip xen_dynamic_chip;
aaca4964 143static struct irq_chip xen_percpu_chip;
d46a78b0 144static struct irq_chip xen_pirq_chip;
7e186bdd
SS
145static void enable_dynirq(struct irq_data *data);
146static void disable_dynirq(struct irq_data *data);
e46cdb66 147
9158c358
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148/* Get info for IRQ */
149static struct irq_info *info_for_irq(unsigned irq)
ced40d0f 150{
c442b806 151 return irq_get_handler_data(irq);
ced40d0f
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152}
153
9158c358
IC
154/* Constructors for packed IRQ information. */
155static void xen_irq_info_common_init(struct irq_info *info,
3d4cfa37 156 unsigned irq,
9158c358
IC
157 enum xen_irq_type type,
158 unsigned short evtchn,
159 unsigned short cpu)
ced40d0f 160{
9158c358
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161
162 BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
163
164 info->type = type;
6cb6537d 165 info->irq = irq;
9158c358
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166 info->evtchn = evtchn;
167 info->cpu = cpu;
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168
169 evtchn_to_irq[evtchn] = irq;
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170
171 irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
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172}
173
9158c358
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174static void xen_irq_info_evtchn_init(unsigned irq,
175 unsigned short evtchn)
ced40d0f 176{
9158c358
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177 struct irq_info *info = info_for_irq(irq);
178
3d4cfa37 179 xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
ced40d0f
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180}
181
3d4cfa37
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182static void xen_irq_info_ipi_init(unsigned cpu,
183 unsigned irq,
9158c358
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184 unsigned short evtchn,
185 enum ipi_vector ipi)
e46cdb66 186{
9158c358
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187 struct irq_info *info = info_for_irq(irq);
188
3d4cfa37 189 xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
9158c358
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190
191 info->u.ipi = ipi;
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192
193 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
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194}
195
3d4cfa37
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196static void xen_irq_info_virq_init(unsigned cpu,
197 unsigned irq,
9158c358
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198 unsigned short evtchn,
199 unsigned short virq)
ced40d0f 200{
9158c358
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201 struct irq_info *info = info_for_irq(irq);
202
3d4cfa37 203 xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
9158c358
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204
205 info->u.virq = virq;
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206
207 per_cpu(virq_to_irq, cpu)[virq] = irq;
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208}
209
9158c358
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210static void xen_irq_info_pirq_init(unsigned irq,
211 unsigned short evtchn,
212 unsigned short pirq,
213 unsigned short gsi,
beafbdc1 214 uint16_t domid,
9158c358 215 unsigned char flags)
ced40d0f 216{
9158c358
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217 struct irq_info *info = info_for_irq(irq);
218
3d4cfa37 219 xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
9158c358
IC
220
221 info->u.pirq.pirq = pirq;
222 info->u.pirq.gsi = gsi;
beafbdc1 223 info->u.pirq.domid = domid;
9158c358 224 info->u.pirq.flags = flags;
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225}
226
227/*
228 * Accessors for packed IRQ information.
229 */
ced40d0f 230static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 231{
110e7c7e
JJ
232 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
233 return 0;
234
ced40d0f 235 return info_for_irq(irq)->evtchn;
e46cdb66
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236}
237
d4c04536
IC
238unsigned irq_from_evtchn(unsigned int evtchn)
239{
240 return evtchn_to_irq[evtchn];
241}
242EXPORT_SYMBOL_GPL(irq_from_evtchn);
243
ced40d0f 244static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 245{
ced40d0f
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246 struct irq_info *info = info_for_irq(irq);
247
248 BUG_ON(info == NULL);
249 BUG_ON(info->type != IRQT_IPI);
250
251 return info->u.ipi;
252}
253
254static unsigned virq_from_irq(unsigned irq)
255{
256 struct irq_info *info = info_for_irq(irq);
257
258 BUG_ON(info == NULL);
259 BUG_ON(info->type != IRQT_VIRQ);
260
261 return info->u.virq;
262}
263
7a043f11
SS
264static unsigned pirq_from_irq(unsigned irq)
265{
266 struct irq_info *info = info_for_irq(irq);
267
268 BUG_ON(info == NULL);
269 BUG_ON(info->type != IRQT_PIRQ);
270
271 return info->u.pirq.pirq;
272}
273
ced40d0f
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274static enum xen_irq_type type_from_irq(unsigned irq)
275{
276 return info_for_irq(irq)->type;
277}
278
279static unsigned cpu_from_irq(unsigned irq)
280{
281 return info_for_irq(irq)->cpu;
282}
283
284static unsigned int cpu_from_evtchn(unsigned int evtchn)
285{
286 int irq = evtchn_to_irq[evtchn];
287 unsigned ret = 0;
288
289 if (irq != -1)
290 ret = cpu_from_irq(irq);
291
292 return ret;
e46cdb66
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293}
294
bf86ad80 295#ifdef CONFIG_X86
9846ff10 296static bool pirq_check_eoi_map(unsigned irq)
d46a78b0 297{
521394e4 298 return test_bit(pirq_from_irq(irq), pirq_eoi_map);
9846ff10 299}
bf86ad80 300#endif
d46a78b0 301
9846ff10
SS
302static bool pirq_needs_eoi_flag(unsigned irq)
303{
304 struct irq_info *info = info_for_irq(irq);
d46a78b0
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305 BUG_ON(info->type != IRQT_PIRQ);
306
307 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
308}
309
c81611c4
IC
310static inline xen_ulong_t active_evtchns(unsigned int cpu,
311 struct shared_info *sh,
312 unsigned int idx)
e46cdb66 313{
088c05a8 314 return sh->evtchn_pending[idx] &
cb60d114 315 per_cpu(cpu_evtchn_mask, cpu)[idx] &
088c05a8 316 ~sh->evtchn_mask[idx];
e46cdb66
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317}
318
319static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
320{
321 int irq = evtchn_to_irq[chn];
322
323 BUG_ON(irq == -1);
324#ifdef CONFIG_SMP
c9e265e0 325 cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
e46cdb66
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326#endif
327
c81611c4
IC
328 clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
329 set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
e46cdb66 330
ca62ce8c 331 info_for_irq(irq)->cpu = cpu;
e46cdb66
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332}
333
334static void init_evtchn_cpu_bindings(void)
335{
1c6969ec 336 int i;
e46cdb66 337#ifdef CONFIG_SMP
6cb6537d 338 struct irq_info *info;
10e58084 339
e46cdb66 340 /* By default all event channels notify CPU#0. */
6cb6537d
IC
341 list_for_each_entry(info, &xen_irq_list_head, list) {
342 struct irq_desc *desc = irq_to_desc(info->irq);
c9e265e0 343 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
0b8f1efa 344 }
e46cdb66
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345#endif
346
1c6969ec 347 for_each_possible_cpu(i)
cb60d114 348 memset(per_cpu(cpu_evtchn_mask, i),
d8251a94 349 (i == 0) ? ~0 : 0, NR_EVENT_CHANNELS/8);
e46cdb66
JF
350}
351
e46cdb66
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352static inline void clear_evtchn(int port)
353{
354 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 355 sync_clear_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
356}
357
358static inline void set_evtchn(int port)
359{
360 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 361 sync_set_bit(port, BM(&s->evtchn_pending[0]));
e46cdb66
JF
362}
363
168d2f46
JF
364static inline int test_evtchn(int port)
365{
366 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 367 return sync_test_bit(port, BM(&s->evtchn_pending[0]));
168d2f46
JF
368}
369
e46cdb66
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370
371/**
372 * notify_remote_via_irq - send event to remote end of event channel via irq
373 * @irq: irq of event channel to send event to
374 *
375 * Unlike notify_remote_via_evtchn(), this is safe to use across
376 * save/restore. Notifications on a broken connection are silently
377 * dropped.
378 */
379void notify_remote_via_irq(int irq)
380{
381 int evtchn = evtchn_from_irq(irq);
382
383 if (VALID_EVTCHN(evtchn))
384 notify_remote_via_evtchn(evtchn);
385}
386EXPORT_SYMBOL_GPL(notify_remote_via_irq);
387
388static void mask_evtchn(int port)
389{
390 struct shared_info *s = HYPERVISOR_shared_info;
c81611c4 391 sync_set_bit(port, BM(&s->evtchn_mask[0]));
e46cdb66
JF
392}
393
394static void unmask_evtchn(int port)
395{
396 struct shared_info *s = HYPERVISOR_shared_info;
397 unsigned int cpu = get_cpu();
b5e57923 398 int do_hypercall = 0, evtchn_pending = 0;
e46cdb66
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399
400 BUG_ON(!irqs_disabled());
401
b5e57923
SS
402 if (unlikely((cpu != cpu_from_evtchn(port))))
403 do_hypercall = 1;
c26377e6
DV
404 else {
405 /*
406 * Need to clear the mask before checking pending to
407 * avoid a race with an event becoming pending.
408 *
409 * EVTCHNOP_unmask will only trigger an upcall if the
410 * mask bit was set, so if a hypercall is needed
411 * remask the event.
412 */
413 sync_clear_bit(port, BM(&s->evtchn_mask[0]));
c81611c4 414 evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
b5e57923 415
c26377e6
DV
416 if (unlikely(evtchn_pending && xen_hvm_domain())) {
417 sync_set_bit(port, BM(&s->evtchn_mask[0]));
418 do_hypercall = 1;
419 }
420 }
b5e57923
SS
421
422 /* Slow path (hypercall) if this is a non-local port or if this is
423 * an hvm domain and an event is pending (hvm domains don't have
424 * their own implementation of irq_enable). */
425 if (do_hypercall) {
e46cdb66
JF
426 struct evtchn_unmask unmask = { .port = port };
427 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
428 } else {
780f36d8 429 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66 430
e46cdb66
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431 /*
432 * The following is basically the equivalent of
433 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
434 * the interrupt edge' if the channel is masked.
435 */
b5e57923 436 if (evtchn_pending &&
c81611c4
IC
437 !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
438 BM(&vcpu_info->evtchn_pending_sel)))
e46cdb66
JF
439 vcpu_info->evtchn_upcall_pending = 1;
440 }
441
442 put_cpu();
443}
444
6cb6537d
IC
445static void xen_irq_init(unsigned irq)
446{
447 struct irq_info *info;
b5328cd1 448#ifdef CONFIG_SMP
6cb6537d
IC
449 struct irq_desc *desc = irq_to_desc(irq);
450
451 /* By default all event channels notify CPU#0. */
452 cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
44626e4a 453#endif
6cb6537d 454
ca62ce8c
IC
455 info = kzalloc(sizeof(*info), GFP_KERNEL);
456 if (info == NULL)
457 panic("Unable to allocate metadata for IRQ%d\n", irq);
6cb6537d
IC
458
459 info->type = IRQT_UNBOUND;
420eb554 460 info->refcnt = -1;
6cb6537d 461
c442b806 462 irq_set_handler_data(irq, info);
ca62ce8c 463
6cb6537d
IC
464 list_add_tail(&info->list, &xen_irq_list_head);
465}
466
7bee9768 467static int __must_check xen_allocate_irq_dynamic(void)
0794bfc7 468{
89911501
IC
469 int first = 0;
470 int irq;
0794bfc7
KRW
471
472#ifdef CONFIG_X86_IO_APIC
89911501
IC
473 /*
474 * For an HVM guest or domain 0 which see "real" (emulated or
25985edc 475 * actual respectively) GSIs we allocate dynamic IRQs
89911501
IC
476 * e.g. those corresponding to event channels or MSIs
477 * etc. from the range above those "real" GSIs to avoid
478 * collisions.
479 */
480 if (xen_initial_domain() || xen_hvm_domain())
481 first = get_nr_irqs_gsi();
0794bfc7
KRW
482#endif
483
89911501 484 irq = irq_alloc_desc_from(first, -1);
3a69e916 485
e6599225
KRW
486 if (irq >= 0)
487 xen_irq_init(irq);
ced40d0f 488
e46cdb66 489 return irq;
d46a78b0
JF
490}
491
7bee9768 492static int __must_check xen_allocate_irq_gsi(unsigned gsi)
c9df1ce5
IC
493{
494 int irq;
495
89911501
IC
496 /*
497 * A PV guest has no concept of a GSI (since it has no ACPI
498 * nor access to/knowledge of the physical APICs). Therefore
499 * all IRQs are dynamically allocated from the entire IRQ
500 * space.
501 */
502 if (xen_pv_domain() && !xen_initial_domain())
c9df1ce5
IC
503 return xen_allocate_irq_dynamic();
504
505 /* Legacy IRQ descriptors are already allocated by the arch. */
506 if (gsi < NR_IRQS_LEGACY)
6cb6537d
IC
507 irq = gsi;
508 else
509 irq = irq_alloc_desc_at(gsi, -1);
c9df1ce5 510
6cb6537d 511 xen_irq_init(irq);
c9df1ce5
IC
512
513 return irq;
514}
515
516static void xen_free_irq(unsigned irq)
517{
c442b806 518 struct irq_info *info = irq_get_handler_data(irq);
6cb6537d 519
94032c50
KRW
520 if (WARN_ON(!info))
521 return;
522
6cb6537d 523 list_del(&info->list);
9158c358 524
c442b806 525 irq_set_handler_data(irq, NULL);
ca62ce8c 526
420eb554
DDG
527 WARN_ON(info->refcnt > 0);
528
ca62ce8c
IC
529 kfree(info);
530
72146104
IC
531 /* Legacy IRQ descriptors are managed by the arch. */
532 if (irq < NR_IRQS_LEGACY)
533 return;
534
c9df1ce5
IC
535 irq_free_desc(irq);
536}
537
d46a78b0
JF
538static void pirq_query_unmask(int irq)
539{
540 struct physdev_irq_status_query irq_status;
541 struct irq_info *info = info_for_irq(irq);
542
543 BUG_ON(info->type != IRQT_PIRQ);
544
7a043f11 545 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
546 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
547 irq_status.flags = 0;
548
549 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
550 if (irq_status.flags & XENIRQSTAT_needs_eoi)
551 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
552}
553
554static bool probing_irq(int irq)
555{
556 struct irq_desc *desc = irq_to_desc(irq);
557
558 return desc && desc->action == NULL;
559}
560
7e186bdd
SS
561static void eoi_pirq(struct irq_data *data)
562{
563 int evtchn = evtchn_from_irq(data->irq);
564 struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
565 int rc = 0;
566
567 irq_move_irq(data);
568
569 if (VALID_EVTCHN(evtchn))
570 clear_evtchn(evtchn);
571
572 if (pirq_needs_eoi(data->irq)) {
573 rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
574 WARN_ON(rc);
575 }
576}
577
578static void mask_ack_pirq(struct irq_data *data)
579{
580 disable_dynirq(data);
581 eoi_pirq(data);
582}
583
c9e265e0 584static unsigned int __startup_pirq(unsigned int irq)
d46a78b0
JF
585{
586 struct evtchn_bind_pirq bind_pirq;
587 struct irq_info *info = info_for_irq(irq);
588 int evtchn = evtchn_from_irq(irq);
15ebbb82 589 int rc;
d46a78b0
JF
590
591 BUG_ON(info->type != IRQT_PIRQ);
592
593 if (VALID_EVTCHN(evtchn))
594 goto out;
595
7a043f11 596 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 597 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
598 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
599 BIND_PIRQ__WILL_SHARE : 0;
600 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
601 if (rc != 0) {
d46a78b0
JF
602 if (!probing_irq(irq))
603 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
604 irq);
605 return 0;
606 }
607 evtchn = bind_pirq.port;
608
609 pirq_query_unmask(irq);
610
611 evtchn_to_irq[evtchn] = irq;
612 bind_evtchn_to_cpu(evtchn, 0);
613 info->evtchn = evtchn;
614
615out:
616 unmask_evtchn(evtchn);
7e186bdd 617 eoi_pirq(irq_get_irq_data(irq));
d46a78b0
JF
618
619 return 0;
620}
621
c9e265e0
TG
622static unsigned int startup_pirq(struct irq_data *data)
623{
624 return __startup_pirq(data->irq);
625}
626
627static void shutdown_pirq(struct irq_data *data)
d46a78b0
JF
628{
629 struct evtchn_close close;
c9e265e0 630 unsigned int irq = data->irq;
d46a78b0
JF
631 struct irq_info *info = info_for_irq(irq);
632 int evtchn = evtchn_from_irq(irq);
633
634 BUG_ON(info->type != IRQT_PIRQ);
635
636 if (!VALID_EVTCHN(evtchn))
637 return;
638
639 mask_evtchn(evtchn);
640
641 close.port = evtchn;
642 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
643 BUG();
644
645 bind_evtchn_to_cpu(evtchn, 0);
646 evtchn_to_irq[evtchn] = -1;
647 info->evtchn = 0;
648}
649
c9e265e0 650static void enable_pirq(struct irq_data *data)
d46a78b0 651{
c9e265e0 652 startup_pirq(data);
d46a78b0
JF
653}
654
c9e265e0 655static void disable_pirq(struct irq_data *data)
d46a78b0 656{
7e186bdd 657 disable_dynirq(data);
d46a78b0
JF
658}
659
68c2c39a 660int xen_irq_from_gsi(unsigned gsi)
d46a78b0 661{
6cb6537d 662 struct irq_info *info;
d46a78b0 663
6cb6537d
IC
664 list_for_each_entry(info, &xen_irq_list_head, list) {
665 if (info->type != IRQT_PIRQ)
d46a78b0
JF
666 continue;
667
6cb6537d
IC
668 if (info->u.pirq.gsi == gsi)
669 return info->irq;
d46a78b0
JF
670 }
671
672 return -1;
673}
68c2c39a 674EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
d46a78b0 675
653378ac
IC
676/*
677 * Do not make any assumptions regarding the relationship between the
678 * IRQ number returned here and the Xen pirq argument.
7a043f11
SS
679 *
680 * Note: We don't assign an event channel until the irq actually started
681 * up. Return an existing irq if we've already got one for the gsi.
e5ac0bda
SS
682 *
683 * Shareable implies level triggered, not shareable implies edge
684 * triggered here.
d46a78b0 685 */
f4d0635b
IC
686int xen_bind_pirq_gsi_to_irq(unsigned gsi,
687 unsigned pirq, int shareable, char *name)
d46a78b0 688{
a0e18116 689 int irq = -1;
d46a78b0
JF
690 struct physdev_irq irq_op;
691
77365948 692 mutex_lock(&irq_mapping_update_lock);
d46a78b0 693
68c2c39a 694 irq = xen_irq_from_gsi(gsi);
d46a78b0 695 if (irq != -1) {
7a043f11 696 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0 697 irq, gsi);
420eb554 698 goto out;
d46a78b0
JF
699 }
700
c9df1ce5 701 irq = xen_allocate_irq_gsi(gsi);
7bee9768
IC
702 if (irq < 0)
703 goto out;
d46a78b0 704
d46a78b0 705 irq_op.irq = irq;
b5401a96
AN
706 irq_op.vector = 0;
707
708 /* Only the privileged domain can do this. For non-priv, the pcifront
709 * driver provides a PCI bus that does the call to do exactly
710 * this in the priv domain. */
711 if (xen_initial_domain() &&
712 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
c9df1ce5 713 xen_free_irq(irq);
d46a78b0
JF
714 irq = -ENOSPC;
715 goto out;
716 }
717
dec02dea 718 xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
9158c358 719 shareable ? PIRQ_SHAREABLE : 0);
d46a78b0 720
7e186bdd
SS
721 pirq_query_unmask(irq);
722 /* We try to use the handler with the appropriate semantic for the
e5ac0bda
SS
723 * type of interrupt: if the interrupt is an edge triggered
724 * interrupt we use handle_edge_irq.
7e186bdd 725 *
e5ac0bda
SS
726 * On the other hand if the interrupt is level triggered we use
727 * handle_fasteoi_irq like the native code does for this kind of
7e186bdd 728 * interrupts.
e5ac0bda 729 *
7e186bdd
SS
730 * Depending on the Xen version, pirq_needs_eoi might return true
731 * not only for level triggered interrupts but for edge triggered
732 * interrupts too. In any case Xen always honors the eoi mechanism,
733 * not injecting any more pirqs of the same kind if the first one
734 * hasn't received an eoi yet. Therefore using the fasteoi handler
735 * is the right choice either way.
736 */
e5ac0bda 737 if (shareable)
7e186bdd
SS
738 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
739 handle_fasteoi_irq, name);
740 else
741 irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
742 handle_edge_irq, name);
743
d46a78b0 744out:
77365948 745 mutex_unlock(&irq_mapping_update_lock);
d46a78b0
JF
746
747 return irq;
748}
749
f731e3ef 750#ifdef CONFIG_PCI_MSI
bf480d95 751int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
cbf6aa89 752{
5cad61a6 753 int rc;
cbf6aa89 754 struct physdev_get_free_pirq op_get_free_pirq;
cbf6aa89 755
bf480d95 756 op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
cbf6aa89 757 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
cbf6aa89 758
5cad61a6
IC
759 WARN_ONCE(rc == -ENOSYS,
760 "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
761
762 return rc ? -1 : op_get_free_pirq.pirq;
cbf6aa89
IC
763}
764
bf480d95 765int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
dec02dea 766 int pirq, const char *name, domid_t domid)
809f9267 767{
bf480d95 768 int irq, ret;
4b41df7f 769
77365948 770 mutex_lock(&irq_mapping_update_lock);
809f9267 771
4b41df7f 772 irq = xen_allocate_irq_dynamic();
e6599225 773 if (irq < 0)
bb5d079a 774 goto out;
809f9267 775
7e186bdd
SS
776 irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
777 name);
809f9267 778
dec02dea 779 xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
5f6fb454 780 ret = irq_set_msi_desc(irq, msidesc);
bf480d95
IC
781 if (ret < 0)
782 goto error_irq;
809f9267 783out:
77365948 784 mutex_unlock(&irq_mapping_update_lock);
4b41df7f 785 return irq;
bf480d95 786error_irq:
77365948 787 mutex_unlock(&irq_mapping_update_lock);
bf480d95 788 xen_free_irq(irq);
e6599225 789 return ret;
809f9267 790}
f731e3ef
QH
791#endif
792
b5401a96
AN
793int xen_destroy_irq(int irq)
794{
795 struct irq_desc *desc;
38aa66fc
JF
796 struct physdev_unmap_pirq unmap_irq;
797 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
798 int rc = -ENOENT;
799
77365948 800 mutex_lock(&irq_mapping_update_lock);
b5401a96
AN
801
802 desc = irq_to_desc(irq);
803 if (!desc)
804 goto out;
805
38aa66fc 806 if (xen_initial_domain()) {
12334715 807 unmap_irq.pirq = info->u.pirq.pirq;
beafbdc1 808 unmap_irq.domid = info->u.pirq.domid;
38aa66fc 809 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
1eff1ad0
KRW
810 /* If another domain quits without making the pci_disable_msix
811 * call, the Xen hypervisor takes care of freeing the PIRQs
812 * (free_domain_pirqs).
813 */
814 if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
815 printk(KERN_INFO "domain %d does not have %d anymore\n",
816 info->u.pirq.domid, info->u.pirq.pirq);
817 else if (rc) {
38aa66fc
JF
818 printk(KERN_WARNING "unmap irq failed %d\n", rc);
819 goto out;
820 }
821 }
b5401a96 822
c9df1ce5 823 xen_free_irq(irq);
b5401a96
AN
824
825out:
77365948 826 mutex_unlock(&irq_mapping_update_lock);
b5401a96
AN
827 return rc;
828}
829
af42b8d1 830int xen_irq_from_pirq(unsigned pirq)
d46a78b0 831{
69c358ce 832 int irq;
d46a78b0 833
69c358ce 834 struct irq_info *info;
e46cdb66 835
77365948 836 mutex_lock(&irq_mapping_update_lock);
69c358ce
IC
837
838 list_for_each_entry(info, &xen_irq_list_head, list) {
9bb9efe4 839 if (info->type != IRQT_PIRQ)
69c358ce
IC
840 continue;
841 irq = info->irq;
842 if (info->u.pirq.pirq == pirq)
843 goto out;
844 }
845 irq = -1;
846out:
77365948 847 mutex_unlock(&irq_mapping_update_lock);
69c358ce
IC
848
849 return irq;
af42b8d1
SS
850}
851
e6197acc
KRW
852
853int xen_pirq_from_irq(unsigned irq)
854{
855 return pirq_from_irq(irq);
856}
857EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
b536b4b9 858int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
859{
860 int irq;
861
77365948 862 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
863
864 irq = evtchn_to_irq[evtchn];
865
866 if (irq == -1) {
c9df1ce5 867 irq = xen_allocate_irq_dynamic();
68ba45ff 868 if (irq < 0)
7bee9768 869 goto out;
e46cdb66 870
c442b806 871 irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
7e186bdd 872 handle_edge_irq, "event");
e46cdb66 873
9158c358 874 xen_irq_info_evtchn_init(irq, evtchn);
5e152e6c
KRW
875 } else {
876 struct irq_info *info = info_for_irq(irq);
877 WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
e46cdb66
JF
878 }
879
7bee9768 880out:
77365948 881 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
882
883 return irq;
884}
b536b4b9 885EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 886
f87e4cac
JF
887static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
888{
889 struct evtchn_bind_ipi bind_ipi;
890 int evtchn, irq;
891
77365948 892 mutex_lock(&irq_mapping_update_lock);
f87e4cac
JF
893
894 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 895
f87e4cac 896 if (irq == -1) {
c9df1ce5 897 irq = xen_allocate_irq_dynamic();
f87e4cac
JF
898 if (irq < 0)
899 goto out;
900
c442b806 901 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
aaca4964 902 handle_percpu_irq, "ipi");
f87e4cac
JF
903
904 bind_ipi.vcpu = cpu;
905 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
906 &bind_ipi) != 0)
907 BUG();
908 evtchn = bind_ipi.port;
909
3d4cfa37 910 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
f87e4cac
JF
911
912 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
913 } else {
914 struct irq_info *info = info_for_irq(irq);
915 WARN_ON(info == NULL || info->type != IRQT_IPI);
f87e4cac
JF
916 }
917
f87e4cac 918 out:
77365948 919 mutex_unlock(&irq_mapping_update_lock);
f87e4cac
JF
920 return irq;
921}
922
2e820f58
IC
923static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
924 unsigned int remote_port)
925{
926 struct evtchn_bind_interdomain bind_interdomain;
927 int err;
928
929 bind_interdomain.remote_dom = remote_domain;
930 bind_interdomain.remote_port = remote_port;
931
932 err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
933 &bind_interdomain);
934
935 return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
936}
937
62cc5fc7
OH
938static int find_virq(unsigned int virq, unsigned int cpu)
939{
940 struct evtchn_status status;
941 int port, rc = -ENOENT;
942
943 memset(&status, 0, sizeof(status));
944 for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
945 status.dom = DOMID_SELF;
946 status.port = port;
947 rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
948 if (rc < 0)
949 continue;
950 if (status.status != EVTCHNSTAT_virq)
951 continue;
952 if (status.u.virq == virq && status.vcpu == cpu) {
953 rc = port;
954 break;
955 }
956 }
957 return rc;
958}
f87e4cac 959
4fe7d5a7 960int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
961{
962 struct evtchn_bind_virq bind_virq;
62cc5fc7 963 int evtchn, irq, ret;
e46cdb66 964
77365948 965 mutex_lock(&irq_mapping_update_lock);
e46cdb66
JF
966
967 irq = per_cpu(virq_to_irq, cpu)[virq];
968
969 if (irq == -1) {
c9df1ce5 970 irq = xen_allocate_irq_dynamic();
68ba45ff 971 if (irq < 0)
7bee9768 972 goto out;
a52521f1 973
c442b806 974 irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
a52521f1
JF
975 handle_percpu_irq, "virq");
976
e46cdb66
JF
977 bind_virq.virq = virq;
978 bind_virq.vcpu = cpu;
62cc5fc7
OH
979 ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
980 &bind_virq);
981 if (ret == 0)
982 evtchn = bind_virq.port;
983 else {
984 if (ret == -EEXIST)
985 ret = find_virq(virq, cpu);
986 BUG_ON(ret < 0);
987 evtchn = ret;
988 }
e46cdb66 989
3d4cfa37 990 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
e46cdb66
JF
991
992 bind_evtchn_to_cpu(evtchn, cpu);
5e152e6c
KRW
993 } else {
994 struct irq_info *info = info_for_irq(irq);
995 WARN_ON(info == NULL || info->type != IRQT_VIRQ);
e46cdb66
JF
996 }
997
7bee9768 998out:
77365948 999 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1000
1001 return irq;
1002}
1003
1004static void unbind_from_irq(unsigned int irq)
1005{
1006 struct evtchn_close close;
1007 int evtchn = evtchn_from_irq(irq);
420eb554 1008 struct irq_info *info = irq_get_handler_data(irq);
e46cdb66 1009
94032c50
KRW
1010 if (WARN_ON(!info))
1011 return;
1012
77365948 1013 mutex_lock(&irq_mapping_update_lock);
e46cdb66 1014
420eb554
DDG
1015 if (info->refcnt > 0) {
1016 info->refcnt--;
1017 if (info->refcnt != 0)
1018 goto done;
1019 }
1020
d77bbd4d 1021 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
1022 close.port = evtchn;
1023 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
1024 BUG();
1025
1026 switch (type_from_irq(irq)) {
1027 case IRQT_VIRQ:
1028 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1029 [virq_from_irq(irq)] = -1;
e46cdb66 1030 break;
d68d82af
AN
1031 case IRQT_IPI:
1032 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 1033 [ipi_from_irq(irq)] = -1;
d68d82af 1034 break;
e46cdb66
JF
1035 default:
1036 break;
1037 }
1038
1039 /* Closed ports are implicitly re-bound to VCPU0. */
1040 bind_evtchn_to_cpu(evtchn, 0);
1041
1042 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
1043 }
1044
ca62ce8c 1045 BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
e46cdb66 1046
9158c358 1047 xen_free_irq(irq);
e46cdb66 1048
420eb554 1049 done:
77365948 1050 mutex_unlock(&irq_mapping_update_lock);
e46cdb66
JF
1051}
1052
1053int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 1054 irq_handler_t handler,
e46cdb66
JF
1055 unsigned long irqflags,
1056 const char *devname, void *dev_id)
1057{
361ae8cb 1058 int irq, retval;
e46cdb66
JF
1059
1060 irq = bind_evtchn_to_irq(evtchn);
7bee9768
IC
1061 if (irq < 0)
1062 return irq;
e46cdb66
JF
1063 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1064 if (retval != 0) {
1065 unbind_from_irq(irq);
1066 return retval;
1067 }
1068
1069 return irq;
1070}
1071EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
1072
2e820f58
IC
1073int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
1074 unsigned int remote_port,
1075 irq_handler_t handler,
1076 unsigned long irqflags,
1077 const char *devname,
1078 void *dev_id)
1079{
1080 int irq, retval;
1081
1082 irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
1083 if (irq < 0)
1084 return irq;
1085
1086 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1087 if (retval != 0) {
1088 unbind_from_irq(irq);
1089 return retval;
1090 }
1091
1092 return irq;
1093}
1094EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
1095
e46cdb66 1096int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 1097 irq_handler_t handler,
e46cdb66
JF
1098 unsigned long irqflags, const char *devname, void *dev_id)
1099{
361ae8cb 1100 int irq, retval;
e46cdb66
JF
1101
1102 irq = bind_virq_to_irq(virq, cpu);
7bee9768
IC
1103 if (irq < 0)
1104 return irq;
e46cdb66
JF
1105 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1106 if (retval != 0) {
1107 unbind_from_irq(irq);
1108 return retval;
1109 }
1110
1111 return irq;
1112}
1113EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
1114
f87e4cac
JF
1115int bind_ipi_to_irqhandler(enum ipi_vector ipi,
1116 unsigned int cpu,
1117 irq_handler_t handler,
1118 unsigned long irqflags,
1119 const char *devname,
1120 void *dev_id)
1121{
1122 int irq, retval;
1123
1124 irq = bind_ipi_to_irq(ipi, cpu);
1125 if (irq < 0)
1126 return irq;
1127
9bab0b7f 1128 irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
f87e4cac
JF
1129 retval = request_irq(irq, handler, irqflags, devname, dev_id);
1130 if (retval != 0) {
1131 unbind_from_irq(irq);
1132 return retval;
1133 }
1134
1135 return irq;
1136}
1137
e46cdb66
JF
1138void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1139{
94032c50
KRW
1140 struct irq_info *info = irq_get_handler_data(irq);
1141
1142 if (WARN_ON(!info))
1143 return;
e46cdb66
JF
1144 free_irq(irq, dev_id);
1145 unbind_from_irq(irq);
1146}
1147EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1148
420eb554
DDG
1149int evtchn_make_refcounted(unsigned int evtchn)
1150{
1151 int irq = evtchn_to_irq[evtchn];
1152 struct irq_info *info;
1153
1154 if (irq == -1)
1155 return -ENOENT;
1156
1157 info = irq_get_handler_data(irq);
1158
1159 if (!info)
1160 return -ENOENT;
1161
1162 WARN_ON(info->refcnt != -1);
1163
1164 info->refcnt = 1;
1165
1166 return 0;
1167}
1168EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
1169
1170int evtchn_get(unsigned int evtchn)
1171{
1172 int irq;
1173 struct irq_info *info;
1174 int err = -ENOENT;
1175
c3b3f16d
DDG
1176 if (evtchn >= NR_EVENT_CHANNELS)
1177 return -EINVAL;
1178
420eb554
DDG
1179 mutex_lock(&irq_mapping_update_lock);
1180
1181 irq = evtchn_to_irq[evtchn];
1182 if (irq == -1)
1183 goto done;
1184
1185 info = irq_get_handler_data(irq);
1186
1187 if (!info)
1188 goto done;
1189
1190 err = -EINVAL;
1191 if (info->refcnt <= 0)
1192 goto done;
1193
1194 info->refcnt++;
1195 err = 0;
1196 done:
1197 mutex_unlock(&irq_mapping_update_lock);
1198
1199 return err;
1200}
1201EXPORT_SYMBOL_GPL(evtchn_get);
1202
1203void evtchn_put(unsigned int evtchn)
1204{
1205 int irq = evtchn_to_irq[evtchn];
1206 if (WARN_ON(irq == -1))
1207 return;
1208 unbind_from_irq(irq);
1209}
1210EXPORT_SYMBOL_GPL(evtchn_put);
1211
f87e4cac
JF
1212void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1213{
1214 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1215 BUG_ON(irq < 0);
1216 notify_remote_via_irq(irq);
1217}
1218
ee523ca1
JF
1219irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1220{
1221 struct shared_info *sh = HYPERVISOR_shared_info;
1222 int cpu = smp_processor_id();
c81611c4 1223 xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
ee523ca1
JF
1224 int i;
1225 unsigned long flags;
1226 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1227 struct vcpu_info *v;
ee523ca1
JF
1228
1229 spin_lock_irqsave(&debug_lock, flags);
1230
cb52e6d9 1231 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1232
1233 for_each_online_cpu(i) {
cb52e6d9
IC
1234 int pending;
1235 v = per_cpu(xen_vcpu, i);
1236 pending = (get_irq_regs() && i == cpu)
1237 ? xen_irqs_disabled(get_irq_regs())
1238 : v->evtchn_upcall_mask;
c81611c4 1239 printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
cb52e6d9
IC
1240 pending, v->evtchn_upcall_pending,
1241 (int)(sizeof(v->evtchn_pending_sel)*2),
1242 v->evtchn_pending_sel);
1243 }
1244 v = per_cpu(xen_vcpu, cpu);
1245
1246 printk("\npending:\n ");
1247 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
c81611c4
IC
1248 printk("%0*"PRI_xen_ulong"%s",
1249 (int)sizeof(sh->evtchn_pending[0])*2,
cb52e6d9
IC
1250 sh->evtchn_pending[i],
1251 i % 8 == 0 ? "\n " : " ");
1252 printk("\nglobal mask:\n ");
1253 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4 1254 printk("%0*"PRI_xen_ulong"%s",
cb52e6d9
IC
1255 (int)(sizeof(sh->evtchn_mask[0])*2),
1256 sh->evtchn_mask[i],
1257 i % 8 == 0 ? "\n " : " ");
1258
1259 printk("\nglobally unmasked:\n ");
1260 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
c81611c4
IC
1261 printk("%0*"PRI_xen_ulong"%s",
1262 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9
IC
1263 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1264 i % 8 == 0 ? "\n " : " ");
1265
1266 printk("\nlocal cpu%d mask:\n ", cpu);
c81611c4
IC
1267 for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
1268 printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
cb52e6d9
IC
1269 cpu_evtchn[i],
1270 i % 8 == 0 ? "\n " : " ");
1271
1272 printk("\nlocally unmasked:\n ");
1273 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
c81611c4 1274 xen_ulong_t pending = sh->evtchn_pending[i]
cb52e6d9
IC
1275 & ~sh->evtchn_mask[i]
1276 & cpu_evtchn[i];
c81611c4
IC
1277 printk("%0*"PRI_xen_ulong"%s",
1278 (int)(sizeof(sh->evtchn_mask[0])*2),
cb52e6d9 1279 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1280 }
ee523ca1
JF
1281
1282 printk("\npending list:\n");
cb52e6d9 1283 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
c81611c4
IC
1284 if (sync_test_bit(i, BM(sh->evtchn_pending))) {
1285 int word_idx = i / BITS_PER_EVTCHN_WORD;
cb52e6d9 1286 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1287 cpu_from_evtchn(i), i,
cb52e6d9 1288 evtchn_to_irq[i],
c81611c4 1289 sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
cb52e6d9 1290 ? "" : " l2-clear",
c81611c4 1291 !sync_test_bit(i, BM(sh->evtchn_mask))
cb52e6d9 1292 ? "" : " globally-masked",
c81611c4 1293 sync_test_bit(i, BM(cpu_evtchn))
cb52e6d9 1294 ? "" : " locally-masked");
ee523ca1
JF
1295 }
1296 }
1297
1298 spin_unlock_irqrestore(&debug_lock, flags);
1299
1300 return IRQ_HANDLED;
1301}
1302
245b2e70 1303static DEFINE_PER_CPU(unsigned, xed_nesting_count);
ada6814c
KF
1304static DEFINE_PER_CPU(unsigned int, current_word_idx);
1305static DEFINE_PER_CPU(unsigned int, current_bit_idx);
245b2e70 1306
ab7f863e
SR
1307/*
1308 * Mask out the i least significant bits of w
1309 */
c81611c4 1310#define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
245b2e70 1311
e46cdb66
JF
1312/*
1313 * Search the CPUs pending events bitmasks. For each one found, map
1314 * the event number to an irq, and feed it into do_IRQ() for
1315 * handling.
1316 *
1317 * Xen uses a two-level bitmap to speed searching. The first level is
1318 * a bitset of words which contain pending event bits. The second
1319 * level is a bitset of pending events themselves.
1320 */
38e20b07 1321static void __xen_evtchn_do_upcall(void)
e46cdb66 1322{
24b51c2f 1323 int start_word_idx, start_bit_idx;
ab7f863e 1324 int word_idx, bit_idx;
bee980d9 1325 int i, irq;
e46cdb66
JF
1326 int cpu = get_cpu();
1327 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1328 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
088c05a8 1329 unsigned count;
e46cdb66 1330
229664be 1331 do {
c81611c4 1332 xen_ulong_t pending_words;
bee980d9
KF
1333 xen_ulong_t pending_bits;
1334 struct irq_desc *desc;
e46cdb66 1335
229664be 1336 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1337
b2e4ae69 1338 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1339 goto out;
e46cdb66 1340
c81611c4
IC
1341 /*
1342 * Master flag must be cleared /before/ clearing
1343 * selector flag. xchg_xen_ulong must contain an
1344 * appropriate barrier.
1345 */
bee980d9
KF
1346 if ((irq = per_cpu(virq_to_irq, cpu)[VIRQ_TIMER]) != -1) {
1347 int evtchn = evtchn_from_irq(irq);
1348 word_idx = evtchn / BITS_PER_LONG;
1349 pending_bits = evtchn % BITS_PER_LONG;
1350 if (active_evtchns(cpu, s, word_idx) & (1ULL << pending_bits)) {
1351 desc = irq_to_desc(irq);
1352 if (desc)
1353 generic_handle_irq_desc(irq, desc);
1354 }
1355 }
1356
c81611c4 1357 pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
ab7f863e 1358
24b51c2f
KF
1359 start_word_idx = __this_cpu_read(current_word_idx);
1360 start_bit_idx = __this_cpu_read(current_bit_idx);
1361
1362 word_idx = start_word_idx;
ab7f863e 1363
24b51c2f 1364 for (i = 0; pending_words != 0; i++) {
c81611c4 1365 xen_ulong_t words;
229664be 1366
ab7f863e
SR
1367 words = MASK_LSBS(pending_words, word_idx);
1368
1369 /*
ada6814c 1370 * If we masked out all events, wrap to beginning.
ab7f863e
SR
1371 */
1372 if (words == 0) {
ada6814c
KF
1373 word_idx = 0;
1374 bit_idx = 0;
ab7f863e
SR
1375 continue;
1376 }
c81611c4 1377 word_idx = EVTCHN_FIRST_BIT(words);
229664be 1378
24b51c2f
KF
1379 pending_bits = active_evtchns(cpu, s, word_idx);
1380 bit_idx = 0; /* usually scan entire word from start */
1381 if (word_idx == start_word_idx) {
1382 /* We scan the starting word in two parts */
1383 if (i == 0)
1384 /* 1st time: start in the middle */
1385 bit_idx = start_bit_idx;
1386 else
1387 /* 2nd time: mask bits done already */
1388 bit_idx &= (1UL << start_bit_idx) - 1;
1389 }
1390
ab7f863e 1391 do {
c81611c4 1392 xen_ulong_t bits;
bee980d9 1393 int port;
229664be 1394
ab7f863e
SR
1395 bits = MASK_LSBS(pending_bits, bit_idx);
1396
1397 /* If we masked out all events, move on. */
ada6814c 1398 if (bits == 0)
ab7f863e 1399 break;
ab7f863e 1400
c81611c4 1401 bit_idx = EVTCHN_FIRST_BIT(bits);
ab7f863e
SR
1402
1403 /* Process port. */
c81611c4 1404 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
ab7f863e
SR
1405 irq = evtchn_to_irq[port];
1406
ca4dbc66
EB
1407 if (irq != -1) {
1408 desc = irq_to_desc(irq);
1409 if (desc)
1410 generic_handle_irq_desc(irq, desc);
1411 }
ab7f863e 1412
c81611c4 1413 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
ada6814c
KF
1414
1415 /* Next caller starts at last processed + 1 */
1416 __this_cpu_write(current_word_idx,
1417 bit_idx ? word_idx :
c81611c4 1418 (word_idx+1) % BITS_PER_EVTCHN_WORD);
ada6814c
KF
1419 __this_cpu_write(current_bit_idx, bit_idx);
1420 } while (bit_idx != 0);
ab7f863e 1421
24b51c2f
KF
1422 /* Scan start_l1i twice; all others once. */
1423 if ((word_idx != start_word_idx) || (i != 0))
ab7f863e 1424 pending_words &= ~(1UL << word_idx);
ada6814c 1425
c81611c4 1426 word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
e46cdb66 1427 }
e46cdb66 1428
229664be
JF
1429 BUG_ON(!irqs_disabled());
1430
780f36d8
CL
1431 count = __this_cpu_read(xed_nesting_count);
1432 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1433 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1434
1435out:
38e20b07
SY
1436
1437 put_cpu();
1438}
1439
1440void xen_evtchn_do_upcall(struct pt_regs *regs)
1441{
1442 struct pt_regs *old_regs = set_irq_regs(regs);
1443
772aebce 1444 irq_enter();
0ec53ecf 1445#ifdef CONFIG_X86
38e20b07 1446 exit_idle();
0ec53ecf 1447#endif
38e20b07
SY
1448
1449 __xen_evtchn_do_upcall();
1450
3445a8fd
JF
1451 irq_exit();
1452 set_irq_regs(old_regs);
38e20b07 1453}
3445a8fd 1454
38e20b07
SY
1455void xen_hvm_evtchn_do_upcall(void)
1456{
1457 __xen_evtchn_do_upcall();
e46cdb66 1458}
183d03cc 1459EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1460
eb1e305f
JF
1461/* Rebind a new event channel to an existing irq. */
1462void rebind_evtchn_irq(int evtchn, int irq)
1463{
d77bbd4d
JF
1464 struct irq_info *info = info_for_irq(irq);
1465
94032c50
KRW
1466 if (WARN_ON(!info))
1467 return;
1468
eb1e305f
JF
1469 /* Make sure the irq is masked, since the new event channel
1470 will also be masked. */
1471 disable_irq(irq);
1472
77365948 1473 mutex_lock(&irq_mapping_update_lock);
eb1e305f
JF
1474
1475 /* After resume the irq<->evtchn mappings are all cleared out */
1476 BUG_ON(evtchn_to_irq[evtchn] != -1);
1477 /* Expect irq to have been bound before,
d77bbd4d
JF
1478 so there should be a proper type */
1479 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f 1480
9158c358 1481 xen_irq_info_evtchn_init(irq, evtchn);
eb1e305f 1482
77365948 1483 mutex_unlock(&irq_mapping_update_lock);
eb1e305f
JF
1484
1485 /* new event channels are always bound to cpu 0 */
0de26520 1486 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1487
1488 /* Unmask the event channel. */
1489 enable_irq(irq);
1490}
1491
e46cdb66 1492/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1493static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66 1494{
131cb95f 1495 struct shared_info *s = HYPERVISOR_shared_info;
e46cdb66
JF
1496 struct evtchn_bind_vcpu bind_vcpu;
1497 int evtchn = evtchn_from_irq(irq);
131cb95f 1498 int masked;
e46cdb66 1499
be49472f
IC
1500 if (!VALID_EVTCHN(evtchn))
1501 return -1;
1502
1503 /*
1504 * Events delivered via platform PCI interrupts are always
1505 * routed to vcpu 0 and hence cannot be rebound.
1506 */
1507 if (xen_hvm_domain() && !xen_have_vector_callback)
d5dedd45 1508 return -1;
e46cdb66
JF
1509
1510 /* Send future instances of this interrupt to other vcpu. */
1511 bind_vcpu.port = evtchn;
1512 bind_vcpu.vcpu = tcpu;
1513
131cb95f
DV
1514 /*
1515 * Mask the event while changing the VCPU binding to prevent
1516 * it being delivered on an unexpected VCPU.
1517 */
1518 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1519
e46cdb66
JF
1520 /*
1521 * If this fails, it usually just indicates that we're dealing with a
1522 * virq or IPI channel, which don't actually need to be rebound. Ignore
1523 * it, but don't do the xenlinux-level rebind in that case.
1524 */
1525 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1526 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1527
131cb95f
DV
1528 if (!masked)
1529 unmask_evtchn(evtchn);
1530
d5dedd45
YL
1531 return 0;
1532}
e46cdb66 1533
c9e265e0
TG
1534static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
1535 bool force)
e46cdb66 1536{
0de26520 1537 unsigned tcpu = cpumask_first(dest);
d5dedd45 1538
c9e265e0 1539 return rebind_irq_to_cpu(data->irq, tcpu);
e46cdb66
JF
1540}
1541
642e0c88
IY
1542int resend_irq_on_evtchn(unsigned int irq)
1543{
1544 int masked, evtchn = evtchn_from_irq(irq);
1545 struct shared_info *s = HYPERVISOR_shared_info;
1546
1547 if (!VALID_EVTCHN(evtchn))
1548 return 1;
1549
c81611c4
IC
1550 masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
1551 sync_set_bit(evtchn, BM(s->evtchn_pending));
642e0c88
IY
1552 if (!masked)
1553 unmask_evtchn(evtchn);
1554
1555 return 1;
1556}
1557
c9e265e0 1558static void enable_dynirq(struct irq_data *data)
e46cdb66 1559{
c9e265e0 1560 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1561
1562 if (VALID_EVTCHN(evtchn))
1563 unmask_evtchn(evtchn);
1564}
1565
c9e265e0 1566static void disable_dynirq(struct irq_data *data)
e46cdb66 1567{
c9e265e0 1568 int evtchn = evtchn_from_irq(data->irq);
e46cdb66
JF
1569
1570 if (VALID_EVTCHN(evtchn))
1571 mask_evtchn(evtchn);
1572}
1573
c9e265e0 1574static void ack_dynirq(struct irq_data *data)
e46cdb66 1575{
c9e265e0 1576 int evtchn = evtchn_from_irq(data->irq);
e46cdb66 1577
7e186bdd 1578 irq_move_irq(data);
e46cdb66
JF
1579
1580 if (VALID_EVTCHN(evtchn))
7e186bdd
SS
1581 clear_evtchn(evtchn);
1582}
1583
1584static void mask_ack_dynirq(struct irq_data *data)
1585{
1586 disable_dynirq(data);
1587 ack_dynirq(data);
e46cdb66
JF
1588}
1589
c9e265e0 1590static int retrigger_dynirq(struct irq_data *data)
e46cdb66 1591{
c9e265e0 1592 int evtchn = evtchn_from_irq(data->irq);
ee8fa1c6 1593 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1594 int ret = 0;
1595
1596 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1597 int masked;
1598
c81611c4
IC
1599 masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
1600 sync_set_bit(evtchn, BM(sh->evtchn_pending));
ee8fa1c6
JF
1601 if (!masked)
1602 unmask_evtchn(evtchn);
e46cdb66
JF
1603 ret = 1;
1604 }
1605
1606 return ret;
1607}
1608
0a85226f 1609static void restore_pirqs(void)
9a069c33
SS
1610{
1611 int pirq, rc, irq, gsi;
1612 struct physdev_map_pirq map_irq;
69c358ce 1613 struct irq_info *info;
9a069c33 1614
69c358ce
IC
1615 list_for_each_entry(info, &xen_irq_list_head, list) {
1616 if (info->type != IRQT_PIRQ)
9a069c33
SS
1617 continue;
1618
69c358ce
IC
1619 pirq = info->u.pirq.pirq;
1620 gsi = info->u.pirq.gsi;
1621 irq = info->irq;
1622
9a069c33
SS
1623 /* save/restore of PT devices doesn't work, so at this point the
1624 * only devices present are GSI based emulated devices */
9a069c33
SS
1625 if (!gsi)
1626 continue;
1627
1628 map_irq.domid = DOMID_SELF;
1629 map_irq.type = MAP_PIRQ_TYPE_GSI;
1630 map_irq.index = gsi;
1631 map_irq.pirq = pirq;
1632
1633 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1634 if (rc) {
1635 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1636 gsi, irq, pirq, rc);
9158c358 1637 xen_free_irq(irq);
9a069c33
SS
1638 continue;
1639 }
1640
1641 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1642
c9e265e0 1643 __startup_pirq(irq);
9a069c33
SS
1644 }
1645}
1646
0e91398f
JF
1647static void restore_cpu_virqs(unsigned int cpu)
1648{
1649 struct evtchn_bind_virq bind_virq;
1650 int virq, irq, evtchn;
1651
1652 for (virq = 0; virq < NR_VIRQS; virq++) {
1653 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1654 continue;
1655
ced40d0f 1656 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1657
1658 /* Get a new binding from Xen. */
1659 bind_virq.virq = virq;
1660 bind_virq.vcpu = cpu;
1661 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1662 &bind_virq) != 0)
1663 BUG();
1664 evtchn = bind_virq.port;
1665
1666 /* Record the new mapping. */
3d4cfa37 1667 xen_irq_info_virq_init(cpu, irq, evtchn, virq);
0e91398f 1668 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1669 }
1670}
1671
1672static void restore_cpu_ipis(unsigned int cpu)
1673{
1674 struct evtchn_bind_ipi bind_ipi;
1675 int ipi, irq, evtchn;
1676
1677 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1678 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1679 continue;
1680
ced40d0f 1681 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1682
1683 /* Get a new binding from Xen. */
1684 bind_ipi.vcpu = cpu;
1685 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1686 &bind_ipi) != 0)
1687 BUG();
1688 evtchn = bind_ipi.port;
1689
1690 /* Record the new mapping. */
3d4cfa37 1691 xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
0e91398f 1692 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1693 }
1694}
1695
2d9e1e2f
JF
1696/* Clear an irq's pending state, in preparation for polling on it */
1697void xen_clear_irq_pending(int irq)
1698{
1699 int evtchn = evtchn_from_irq(irq);
1700
1701 if (VALID_EVTCHN(evtchn))
1702 clear_evtchn(evtchn);
1703}
d9a8814f 1704EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1705void xen_set_irq_pending(int irq)
1706{
1707 int evtchn = evtchn_from_irq(irq);
1708
1709 if (VALID_EVTCHN(evtchn))
1710 set_evtchn(evtchn);
1711}
1712
1713bool xen_test_irq_pending(int irq)
1714{
1715 int evtchn = evtchn_from_irq(irq);
1716 bool ret = false;
1717
1718 if (VALID_EVTCHN(evtchn))
1719 ret = test_evtchn(evtchn);
1720
1721 return ret;
1722}
1723
d9a8814f
KRW
1724/* Poll waiting for an irq to become pending with timeout. In the usual case,
1725 * the irq will be disabled so it won't deliver an interrupt. */
1726void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1727{
1728 evtchn_port_t evtchn = evtchn_from_irq(irq);
1729
1730 if (VALID_EVTCHN(evtchn)) {
1731 struct sched_poll poll;
1732
1733 poll.nr_ports = 1;
d9a8814f 1734 poll.timeout = timeout;
ff3c5362 1735 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1736
1737 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1738 BUG();
1739 }
1740}
d9a8814f
KRW
1741EXPORT_SYMBOL(xen_poll_irq_timeout);
1742/* Poll waiting for an irq to become pending. In the usual case, the
1743 * irq will be disabled so it won't deliver an interrupt. */
1744void xen_poll_irq(int irq)
1745{
1746 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1747}
2d9e1e2f 1748
c7c2c3a2
KRW
1749/* Check whether the IRQ line is shared with other guests. */
1750int xen_test_irq_shared(int irq)
1751{
1752 struct irq_info *info = info_for_irq(irq);
94032c50
KRW
1753 struct physdev_irq_status_query irq_status;
1754
1755 if (WARN_ON(!info))
1756 return -ENOENT;
1757
1758 irq_status.irq = info->u.pirq.pirq;
c7c2c3a2
KRW
1759
1760 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
1761 return 0;
1762 return !(irq_status.flags & XENIRQSTAT_shared);
1763}
1764EXPORT_SYMBOL_GPL(xen_test_irq_shared);
1765
0e91398f
JF
1766void xen_irq_resume(void)
1767{
6cb6537d
IC
1768 unsigned int cpu, evtchn;
1769 struct irq_info *info;
0e91398f
JF
1770
1771 init_evtchn_cpu_bindings();
1772
1773 /* New event-channel space is not 'live' yet. */
1774 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1775 mask_evtchn(evtchn);
1776
1777 /* No IRQ <-> event-channel mappings. */
6cb6537d
IC
1778 list_for_each_entry(info, &xen_irq_list_head, list)
1779 info->evtchn = 0; /* zap event-channel binding */
0e91398f
JF
1780
1781 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1782 evtchn_to_irq[evtchn] = -1;
1783
1784 for_each_possible_cpu(cpu) {
1785 restore_cpu_virqs(cpu);
1786 restore_cpu_ipis(cpu);
1787 }
6903591f 1788
0a85226f 1789 restore_pirqs();
0e91398f
JF
1790}
1791
e46cdb66 1792static struct irq_chip xen_dynamic_chip __read_mostly = {
c9e265e0 1793 .name = "xen-dyn",
54a353a0 1794
c9e265e0
TG
1795 .irq_disable = disable_dynirq,
1796 .irq_mask = disable_dynirq,
1797 .irq_unmask = enable_dynirq,
54a353a0 1798
7e186bdd
SS
1799 .irq_ack = ack_dynirq,
1800 .irq_mask_ack = mask_ack_dynirq,
1801
c9e265e0
TG
1802 .irq_set_affinity = set_affinity_irq,
1803 .irq_retrigger = retrigger_dynirq,
e46cdb66
JF
1804};
1805
d46a78b0 1806static struct irq_chip xen_pirq_chip __read_mostly = {
c9e265e0 1807 .name = "xen-pirq",
d46a78b0 1808
c9e265e0
TG
1809 .irq_startup = startup_pirq,
1810 .irq_shutdown = shutdown_pirq,
c9e265e0 1811 .irq_enable = enable_pirq,
c9e265e0 1812 .irq_disable = disable_pirq,
d46a78b0 1813
7e186bdd
SS
1814 .irq_mask = disable_dynirq,
1815 .irq_unmask = enable_dynirq,
1816
1817 .irq_ack = eoi_pirq,
1818 .irq_eoi = eoi_pirq,
1819 .irq_mask_ack = mask_ack_pirq,
d46a78b0 1820
c9e265e0 1821 .irq_set_affinity = set_affinity_irq,
d46a78b0 1822
c9e265e0 1823 .irq_retrigger = retrigger_dynirq,
d46a78b0
JF
1824};
1825
aaca4964 1826static struct irq_chip xen_percpu_chip __read_mostly = {
c9e265e0 1827 .name = "xen-percpu",
aaca4964 1828
c9e265e0
TG
1829 .irq_disable = disable_dynirq,
1830 .irq_mask = disable_dynirq,
1831 .irq_unmask = enable_dynirq,
aaca4964 1832
c9e265e0 1833 .irq_ack = ack_dynirq,
aaca4964
JF
1834};
1835
38e20b07
SY
1836int xen_set_callback_via(uint64_t via)
1837{
1838 struct xen_hvm_param a;
1839 a.domid = DOMID_SELF;
1840 a.index = HVM_PARAM_CALLBACK_IRQ;
1841 a.value = via;
1842 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1843}
1844EXPORT_SYMBOL_GPL(xen_set_callback_via);
1845
ca65f9fc 1846#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1847/* Vector callbacks are better than PCI interrupts to receive event
1848 * channel notifications because we can receive vector callbacks on any
1849 * vcpu and we don't need PCI support or APIC interactions. */
1850void xen_callback_vector(void)
1851{
1852 int rc;
1853 uint64_t callback_via;
1854 if (xen_have_vector_callback) {
bc2b0331 1855 callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
38e20b07
SY
1856 rc = xen_set_callback_via(callback_via);
1857 if (rc) {
1858 printk(KERN_ERR "Request for Xen HVM callback vector"
1859 " failed.\n");
1860 xen_have_vector_callback = 0;
1861 return;
1862 }
1863 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1864 "enabled\n");
1865 /* in the restore case the vector has already been allocated */
bc2b0331
S
1866 if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
1867 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
1868 xen_hvm_callback_vector);
38e20b07
SY
1869 }
1870}
ca65f9fc
SS
1871#else
1872void xen_callback_vector(void) {}
1873#endif
38e20b07 1874
2e3d8860 1875void __init xen_init_IRQ(void)
e46cdb66 1876{
0ec53ecf 1877 int i;
c7a3589e 1878
b21ddbf5
JF
1879 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1880 GFP_KERNEL);
9d093e29 1881 BUG_ON(!evtchn_to_irq);
b21ddbf5
JF
1882 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1883 evtchn_to_irq[i] = -1;
e46cdb66
JF
1884
1885 init_evtchn_cpu_bindings();
1886
1887 /* No event channels are 'live' right now. */
1888 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1889 mask_evtchn(i);
1890
9846ff10
SS
1891 pirq_needs_eoi = pirq_needs_eoi_flag;
1892
0ec53ecf 1893#ifdef CONFIG_X86
38e20b07
SY
1894 if (xen_hvm_domain()) {
1895 xen_callback_vector();
1896 native_init_IRQ();
3942b740
SS
1897 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1898 * __acpi_register_gsi can point at the right function */
1899 pci_xen_hvm_init();
38e20b07 1900 } else {
0ec53ecf 1901 int rc;
9846ff10
SS
1902 struct physdev_pirq_eoi_gmfn eoi_gmfn;
1903
38e20b07 1904 irq_ctx_init(smp_processor_id());
38aa66fc 1905 if (xen_initial_domain())
a0ee0567 1906 pci_xen_initial_domain();
9846ff10
SS
1907
1908 pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
1909 eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
1910 rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
1911 if (rc != 0) {
1912 free_page((unsigned long) pirq_eoi_map);
1913 pirq_eoi_map = NULL;
1914 } else
1915 pirq_needs_eoi = pirq_check_eoi_map;
38e20b07 1916 }
0ec53ecf 1917#endif
e46cdb66 1918}