Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
JF
130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
ced40d0f 173 return info_for_irq(irq)->evtchn;
e46cdb66
JF
174}
175
d4c04536
IC
176unsigned irq_from_evtchn(unsigned int evtchn)
177{
178 return evtchn_to_irq[evtchn];
179}
180EXPORT_SYMBOL_GPL(irq_from_evtchn);
181
ced40d0f 182static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 183{
ced40d0f
JF
184 struct irq_info *info = info_for_irq(irq);
185
186 BUG_ON(info == NULL);
187 BUG_ON(info->type != IRQT_IPI);
188
189 return info->u.ipi;
190}
191
192static unsigned virq_from_irq(unsigned irq)
193{
194 struct irq_info *info = info_for_irq(irq);
195
196 BUG_ON(info == NULL);
197 BUG_ON(info->type != IRQT_VIRQ);
198
199 return info->u.virq;
200}
201
7a043f11
SS
202static unsigned pirq_from_irq(unsigned irq)
203{
204 struct irq_info *info = info_for_irq(irq);
205
206 BUG_ON(info == NULL);
207 BUG_ON(info->type != IRQT_PIRQ);
208
209 return info->u.pirq.pirq;
210}
211
ced40d0f
JF
212static unsigned gsi_from_irq(unsigned irq)
213{
214 struct irq_info *info = info_for_irq(irq);
215
216 BUG_ON(info == NULL);
217 BUG_ON(info->type != IRQT_PIRQ);
218
219 return info->u.pirq.gsi;
220}
221
222static unsigned vector_from_irq(unsigned irq)
223{
224 struct irq_info *info = info_for_irq(irq);
225
226 BUG_ON(info == NULL);
227 BUG_ON(info->type != IRQT_PIRQ);
228
229 return info->u.pirq.vector;
230}
231
232static enum xen_irq_type type_from_irq(unsigned irq)
233{
234 return info_for_irq(irq)->type;
235}
236
237static unsigned cpu_from_irq(unsigned irq)
238{
239 return info_for_irq(irq)->cpu;
240}
241
242static unsigned int cpu_from_evtchn(unsigned int evtchn)
243{
244 int irq = evtchn_to_irq[evtchn];
245 unsigned ret = 0;
246
247 if (irq != -1)
248 ret = cpu_from_irq(irq);
249
250 return ret;
e46cdb66
JF
251}
252
d46a78b0
JF
253static bool pirq_needs_eoi(unsigned irq)
254{
255 struct irq_info *info = info_for_irq(irq);
256
257 BUG_ON(info->type != IRQT_PIRQ);
258
259 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
260}
261
e46cdb66
JF
262static inline unsigned long active_evtchns(unsigned int cpu,
263 struct shared_info *sh,
264 unsigned int idx)
265{
266 return (sh->evtchn_pending[idx] &
c7a3589e 267 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
268 ~sh->evtchn_mask[idx]);
269}
270
271static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
272{
273 int irq = evtchn_to_irq[chn];
274
275 BUG_ON(irq == -1);
276#ifdef CONFIG_SMP
7f7ace0c 277 cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
e46cdb66
JF
278#endif
279
e0419564
JF
280 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
281 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 282
ced40d0f 283 irq_info[irq].cpu = cpu;
e46cdb66
JF
284}
285
286static void init_evtchn_cpu_bindings(void)
287{
1c6969ec 288 int i;
e46cdb66 289#ifdef CONFIG_SMP
10e58084 290 struct irq_desc *desc;
10e58084 291
e46cdb66 292 /* By default all event channels notify CPU#0. */
0b8f1efa 293 for_each_irq_desc(i, desc) {
7f7ace0c 294 cpumask_copy(desc->affinity, cpumask_of(0));
0b8f1efa 295 }
e46cdb66
JF
296#endif
297
1c6969ec
JB
298 for_each_possible_cpu(i)
299 memset(cpu_evtchn_mask(i),
300 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
301
e46cdb66
JF
302}
303
e46cdb66
JF
304static inline void clear_evtchn(int port)
305{
306 struct shared_info *s = HYPERVISOR_shared_info;
307 sync_clear_bit(port, &s->evtchn_pending[0]);
308}
309
310static inline void set_evtchn(int port)
311{
312 struct shared_info *s = HYPERVISOR_shared_info;
313 sync_set_bit(port, &s->evtchn_pending[0]);
314}
315
168d2f46
JF
316static inline int test_evtchn(int port)
317{
318 struct shared_info *s = HYPERVISOR_shared_info;
319 return sync_test_bit(port, &s->evtchn_pending[0]);
320}
321
e46cdb66
JF
322
323/**
324 * notify_remote_via_irq - send event to remote end of event channel via irq
325 * @irq: irq of event channel to send event to
326 *
327 * Unlike notify_remote_via_evtchn(), this is safe to use across
328 * save/restore. Notifications on a broken connection are silently
329 * dropped.
330 */
331void notify_remote_via_irq(int irq)
332{
333 int evtchn = evtchn_from_irq(irq);
334
335 if (VALID_EVTCHN(evtchn))
336 notify_remote_via_evtchn(evtchn);
337}
338EXPORT_SYMBOL_GPL(notify_remote_via_irq);
339
340static void mask_evtchn(int port)
341{
342 struct shared_info *s = HYPERVISOR_shared_info;
343 sync_set_bit(port, &s->evtchn_mask[0]);
344}
345
346static void unmask_evtchn(int port)
347{
348 struct shared_info *s = HYPERVISOR_shared_info;
349 unsigned int cpu = get_cpu();
350
351 BUG_ON(!irqs_disabled());
352
353 /* Slow path (hypercall) if this is a non-local port. */
354 if (unlikely(cpu != cpu_from_evtchn(port))) {
355 struct evtchn_unmask unmask = { .port = port };
356 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
357 } else {
358 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
359
360 sync_clear_bit(port, &s->evtchn_mask[0]);
361
362 /*
363 * The following is basically the equivalent of
364 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
365 * the interrupt edge' if the channel is masked.
366 */
367 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
368 !sync_test_and_set_bit(port / BITS_PER_LONG,
369 &vcpu_info->evtchn_pending_sel))
370 vcpu_info->evtchn_upcall_pending = 1;
371 }
372
373 put_cpu();
374}
375
0794bfc7
KRW
376static int get_nr_hw_irqs(void)
377{
378 int ret = 1;
379
380#ifdef CONFIG_X86_IO_APIC
381 ret = get_nr_irqs_gsi();
382#endif
383
384 return ret;
385}
386
e5fc7345 387static int find_unbound_pirq(int type)
7a043f11 388{
e5fc7345
SS
389 int rc, i;
390 struct physdev_get_free_pirq op_get_free_pirq;
391 op_get_free_pirq.type = type;
392
393 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
394 if (!rc)
395 return op_get_free_pirq.pirq;
396
397 for (i = 0; i < nr_irqs; i++) {
7a043f11
SS
398 if (pirq_to_irq[i] < 0)
399 return i;
400 }
401 return -1;
402}
403
e46cdb66
JF
404static int find_unbound_irq(void)
405{
77dff1c7
TG
406 struct irq_data *data;
407 int irq, res;
3a69e916 408 int start = get_nr_hw_irqs();
e46cdb66 409
3a69e916
KRW
410 if (start == nr_irqs)
411 goto no_irqs;
412
413 /* nr_irqs is a magic value. Must not use it.*/
414 for (irq = nr_irqs-1; irq > start; irq--) {
77dff1c7 415 data = irq_get_irq_data(irq);
99ad198c 416 /* only 0->15 have init'd desc; handle irq > 16 */
77dff1c7 417 if (!data)
99ad198c 418 break;
77dff1c7 419 if (data->chip == &no_irq_chip)
99ad198c 420 break;
77dff1c7 421 if (data->chip != &xen_dynamic_chip)
99ad198c 422 continue;
d77bbd4d 423 if (irq_info[irq].type == IRQT_UNBOUND)
77dff1c7 424 return irq;
99ad198c 425 }
e46cdb66 426
3a69e916
KRW
427 if (irq == start)
428 goto no_irqs;
e46cdb66 429
29dcbc5c 430 res = irq_alloc_desc_at(irq, -1);
6f8a0ed4 431
77dff1c7
TG
432 if (WARN_ON(res != irq))
433 return -1;
ced40d0f 434
e46cdb66 435 return irq;
3a69e916
KRW
436
437no_irqs:
438 panic("No available IRQ to bind to: increase nr_irqs!\n");
e46cdb66
JF
439}
440
d46a78b0
JF
441static bool identity_mapped_irq(unsigned irq)
442{
0794bfc7
KRW
443 /* identity map all the hardware irqs */
444 return irq < get_nr_hw_irqs();
d46a78b0
JF
445}
446
447static void pirq_unmask_notify(int irq)
448{
7a043f11 449 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
450
451 if (unlikely(pirq_needs_eoi(irq))) {
452 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
453 WARN_ON(rc);
454 }
455}
456
457static void pirq_query_unmask(int irq)
458{
459 struct physdev_irq_status_query irq_status;
460 struct irq_info *info = info_for_irq(irq);
461
462 BUG_ON(info->type != IRQT_PIRQ);
463
7a043f11 464 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
465 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
466 irq_status.flags = 0;
467
468 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
469 if (irq_status.flags & XENIRQSTAT_needs_eoi)
470 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
471}
472
473static bool probing_irq(int irq)
474{
475 struct irq_desc *desc = irq_to_desc(irq);
476
477 return desc && desc->action == NULL;
478}
479
480static unsigned int startup_pirq(unsigned int irq)
481{
482 struct evtchn_bind_pirq bind_pirq;
483 struct irq_info *info = info_for_irq(irq);
484 int evtchn = evtchn_from_irq(irq);
15ebbb82 485 int rc;
d46a78b0
JF
486
487 BUG_ON(info->type != IRQT_PIRQ);
488
489 if (VALID_EVTCHN(evtchn))
490 goto out;
491
7a043f11 492 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 493 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
494 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
495 BIND_PIRQ__WILL_SHARE : 0;
496 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
497 if (rc != 0) {
d46a78b0
JF
498 if (!probing_irq(irq))
499 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
500 irq);
501 return 0;
502 }
503 evtchn = bind_pirq.port;
504
505 pirq_query_unmask(irq);
506
507 evtchn_to_irq[evtchn] = irq;
508 bind_evtchn_to_cpu(evtchn, 0);
509 info->evtchn = evtchn;
510
511out:
512 unmask_evtchn(evtchn);
513 pirq_unmask_notify(irq);
514
515 return 0;
516}
517
518static void shutdown_pirq(unsigned int irq)
519{
520 struct evtchn_close close;
521 struct irq_info *info = info_for_irq(irq);
522 int evtchn = evtchn_from_irq(irq);
523
524 BUG_ON(info->type != IRQT_PIRQ);
525
526 if (!VALID_EVTCHN(evtchn))
527 return;
528
529 mask_evtchn(evtchn);
530
531 close.port = evtchn;
532 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
533 BUG();
534
535 bind_evtchn_to_cpu(evtchn, 0);
536 evtchn_to_irq[evtchn] = -1;
537 info->evtchn = 0;
538}
539
540static void enable_pirq(unsigned int irq)
541{
542 startup_pirq(irq);
543}
544
545static void disable_pirq(unsigned int irq)
546{
547}
548
549static void ack_pirq(unsigned int irq)
550{
551 int evtchn = evtchn_from_irq(irq);
552
553 move_native_irq(irq);
554
555 if (VALID_EVTCHN(evtchn)) {
556 mask_evtchn(evtchn);
557 clear_evtchn(evtchn);
558 }
559}
560
561static void end_pirq(unsigned int irq)
562{
563 int evtchn = evtchn_from_irq(irq);
564 struct irq_desc *desc = irq_to_desc(irq);
565
566 if (WARN_ON(!desc))
567 return;
568
569 if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
570 (IRQ_DISABLED|IRQ_PENDING)) {
571 shutdown_pirq(irq);
572 } else if (VALID_EVTCHN(evtchn)) {
573 unmask_evtchn(evtchn);
574 pirq_unmask_notify(irq);
575 }
576}
577
578static int find_irq_by_gsi(unsigned gsi)
579{
580 int irq;
581
b21ddbf5 582 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
583 struct irq_info *info = info_for_irq(irq);
584
585 if (info == NULL || info->type != IRQT_PIRQ)
586 continue;
587
588 if (gsi_from_irq(irq) == gsi)
589 return irq;
590 }
591
592 return -1;
593}
594
7a043f11
SS
595int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
596{
597 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
598}
599
600/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
601 * consequence don't assume that the irq number returned has a low value
602 * or can be used as a pirq number unless you know otherwise.
603 *
7a043f11 604 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 605 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
606 * matches the gsi number passed as second argument.
607 *
608 * Note: We don't assign an event channel until the irq actually started
609 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 610 */
7a043f11 611int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 612{
7a043f11 613 int irq = 0;
d46a78b0
JF
614 struct physdev_irq irq_op;
615
616 spin_lock(&irq_mapping_update_lock);
617
e5fc7345 618 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 619 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
620 pirq > nr_irqs ? "pirq" :"",
621 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
622 goto out;
623 }
624
d46a78b0
JF
625 irq = find_irq_by_gsi(gsi);
626 if (irq != -1) {
7a043f11 627 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
628 irq, gsi);
629 goto out; /* XXX need refcount? */
630 }
631
b5401a96
AN
632 /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore
633 * we are using the !xen_initial_domain() to drop in the function.*/
3942b740
SS
634 if (identity_mapped_irq(gsi) || (!xen_initial_domain() &&
635 xen_pv_domain())) {
d46a78b0 636 irq = gsi;
29dcbc5c 637 irq_alloc_desc_at(irq, -1);
d46a78b0
JF
638 } else
639 irq = find_unbound_irq();
640
641 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 642 handle_level_irq, name);
d46a78b0
JF
643
644 irq_op.irq = irq;
b5401a96
AN
645 irq_op.vector = 0;
646
647 /* Only the privileged domain can do this. For non-priv, the pcifront
648 * driver provides a PCI bus that does the call to do exactly
649 * this in the priv domain. */
650 if (xen_initial_domain() &&
651 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
2c52f8d3 652 irq_free_desc(irq);
d46a78b0
JF
653 irq = -ENOSPC;
654 goto out;
655 }
656
7a043f11 657 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 658 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 659 pirq_to_irq[pirq] = irq;
d46a78b0
JF
660
661out:
662 spin_unlock(&irq_mapping_update_lock);
663
664 return irq;
665}
666
f731e3ef
QH
667#ifdef CONFIG_PCI_MSI
668#include <linux/msi.h>
669#include "../pci/msi.h"
670
af42b8d1 671void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
809f9267
SS
672{
673 spin_lock(&irq_mapping_update_lock);
674
af42b8d1
SS
675 if (alloc & XEN_ALLOC_IRQ) {
676 *irq = find_unbound_irq();
677 if (*irq == -1)
678 goto out;
679 }
809f9267 680
af42b8d1
SS
681 if (alloc & XEN_ALLOC_PIRQ) {
682 *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
683 if (*pirq == -1)
684 goto out;
685 }
809f9267
SS
686
687 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
688 handle_level_irq, name);
689
690 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
691 pirq_to_irq[*pirq] = *irq;
692
693out:
694 spin_unlock(&irq_mapping_update_lock);
695}
696
f731e3ef
QH
697int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
698{
699 int irq = -1;
700 struct physdev_map_pirq map_irq;
701 int rc;
702 int pos;
703 u32 table_offset, bir;
704
705 memset(&map_irq, 0, sizeof(map_irq));
706 map_irq.domid = DOMID_SELF;
707 map_irq.type = MAP_PIRQ_TYPE_MSI;
708 map_irq.index = -1;
709 map_irq.pirq = -1;
710 map_irq.bus = dev->bus->number;
711 map_irq.devfn = dev->devfn;
712
713 if (type == PCI_CAP_ID_MSIX) {
714 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
715
716 pci_read_config_dword(dev, msix_table_offset_reg(pos),
717 &table_offset);
718 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
719
720 map_irq.table_base = pci_resource_start(dev, bir);
721 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
722 }
723
724 spin_lock(&irq_mapping_update_lock);
725
726 irq = find_unbound_irq();
727
728 if (irq == -1)
729 goto out;
730
731 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
732 if (rc) {
733 printk(KERN_WARNING "xen map irq failed %d\n", rc);
734
735 irq_free_desc(irq);
736
737 irq = -1;
738 goto out;
739 }
740 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
741
742 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
743 handle_level_irq,
744 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
745
746out:
747 spin_unlock(&irq_mapping_update_lock);
748 return irq;
749}
750#endif
751
b5401a96
AN
752int xen_destroy_irq(int irq)
753{
754 struct irq_desc *desc;
38aa66fc
JF
755 struct physdev_unmap_pirq unmap_irq;
756 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
757 int rc = -ENOENT;
758
759 spin_lock(&irq_mapping_update_lock);
760
761 desc = irq_to_desc(irq);
762 if (!desc)
763 goto out;
764
38aa66fc 765 if (xen_initial_domain()) {
12334715 766 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
767 unmap_irq.domid = DOMID_SELF;
768 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
769 if (rc) {
770 printk(KERN_WARNING "unmap irq failed %d\n", rc);
771 goto out;
772 }
af42b8d1 773 pirq_to_irq[info->u.pirq.pirq] = -1;
38aa66fc 774 }
b5401a96
AN
775 irq_info[irq] = mk_unbound_info();
776
2c52f8d3 777 irq_free_desc(irq);
b5401a96
AN
778
779out:
780 spin_unlock(&irq_mapping_update_lock);
781 return rc;
782}
783
d46a78b0
JF
784int xen_vector_from_irq(unsigned irq)
785{
786 return vector_from_irq(irq);
787}
788
789int xen_gsi_from_irq(unsigned irq)
790{
791 return gsi_from_irq(irq);
e46cdb66
JF
792}
793
af42b8d1
SS
794int xen_irq_from_pirq(unsigned pirq)
795{
796 return pirq_to_irq[pirq];
797}
798
b536b4b9 799int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
800{
801 int irq;
802
803 spin_lock(&irq_mapping_update_lock);
804
805 irq = evtchn_to_irq[evtchn];
806
807 if (irq == -1) {
808 irq = find_unbound_irq();
809
e46cdb66 810 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 811 handle_fasteoi_irq, "event");
e46cdb66
JF
812
813 evtchn_to_irq[evtchn] = irq;
ced40d0f 814 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
815 }
816
e46cdb66
JF
817 spin_unlock(&irq_mapping_update_lock);
818
819 return irq;
820}
b536b4b9 821EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 822
f87e4cac
JF
823static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
824{
825 struct evtchn_bind_ipi bind_ipi;
826 int evtchn, irq;
827
828 spin_lock(&irq_mapping_update_lock);
829
830 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 831
f87e4cac
JF
832 if (irq == -1) {
833 irq = find_unbound_irq();
834 if (irq < 0)
835 goto out;
836
aaca4964
JF
837 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
838 handle_percpu_irq, "ipi");
f87e4cac
JF
839
840 bind_ipi.vcpu = cpu;
841 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
842 &bind_ipi) != 0)
843 BUG();
844 evtchn = bind_ipi.port;
845
846 evtchn_to_irq[evtchn] = irq;
ced40d0f 847 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
848 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
849
850 bind_evtchn_to_cpu(evtchn, cpu);
851 }
852
f87e4cac
JF
853 out:
854 spin_unlock(&irq_mapping_update_lock);
855 return irq;
856}
857
858
4fe7d5a7 859int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
860{
861 struct evtchn_bind_virq bind_virq;
862 int evtchn, irq;
863
864 spin_lock(&irq_mapping_update_lock);
865
866 irq = per_cpu(virq_to_irq, cpu)[virq];
867
868 if (irq == -1) {
a52521f1
JF
869 irq = find_unbound_irq();
870
871 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
872 handle_percpu_irq, "virq");
873
e46cdb66
JF
874 bind_virq.virq = virq;
875 bind_virq.vcpu = cpu;
876 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
877 &bind_virq) != 0)
878 BUG();
879 evtchn = bind_virq.port;
880
e46cdb66 881 evtchn_to_irq[evtchn] = irq;
ced40d0f 882 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
883
884 per_cpu(virq_to_irq, cpu)[virq] = irq;
885
886 bind_evtchn_to_cpu(evtchn, cpu);
887 }
888
e46cdb66
JF
889 spin_unlock(&irq_mapping_update_lock);
890
891 return irq;
892}
893
894static void unbind_from_irq(unsigned int irq)
895{
896 struct evtchn_close close;
897 int evtchn = evtchn_from_irq(irq);
898
899 spin_lock(&irq_mapping_update_lock);
900
d77bbd4d 901 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
902 close.port = evtchn;
903 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
904 BUG();
905
906 switch (type_from_irq(irq)) {
907 case IRQT_VIRQ:
908 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 909 [virq_from_irq(irq)] = -1;
e46cdb66 910 break;
d68d82af
AN
911 case IRQT_IPI:
912 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 913 [ipi_from_irq(irq)] = -1;
d68d82af 914 break;
e46cdb66
JF
915 default:
916 break;
917 }
918
919 /* Closed ports are implicitly re-bound to VCPU0. */
920 bind_evtchn_to_cpu(evtchn, 0);
921
922 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
923 }
924
925 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 926 irq_info[irq] = mk_unbound_info();
e46cdb66 927
77dff1c7 928 irq_free_desc(irq);
e46cdb66
JF
929 }
930
931 spin_unlock(&irq_mapping_update_lock);
932}
933
934int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 935 irq_handler_t handler,
e46cdb66
JF
936 unsigned long irqflags,
937 const char *devname, void *dev_id)
938{
939 unsigned int irq;
940 int retval;
941
942 irq = bind_evtchn_to_irq(evtchn);
943 retval = request_irq(irq, handler, irqflags, devname, dev_id);
944 if (retval != 0) {
945 unbind_from_irq(irq);
946 return retval;
947 }
948
949 return irq;
950}
951EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
952
953int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 954 irq_handler_t handler,
e46cdb66
JF
955 unsigned long irqflags, const char *devname, void *dev_id)
956{
957 unsigned int irq;
958 int retval;
959
960 irq = bind_virq_to_irq(virq, cpu);
961 retval = request_irq(irq, handler, irqflags, devname, dev_id);
962 if (retval != 0) {
963 unbind_from_irq(irq);
964 return retval;
965 }
966
967 return irq;
968}
969EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
970
f87e4cac
JF
971int bind_ipi_to_irqhandler(enum ipi_vector ipi,
972 unsigned int cpu,
973 irq_handler_t handler,
974 unsigned long irqflags,
975 const char *devname,
976 void *dev_id)
977{
978 int irq, retval;
979
980 irq = bind_ipi_to_irq(ipi, cpu);
981 if (irq < 0)
982 return irq;
983
4877c737 984 irqflags |= IRQF_NO_SUSPEND;
f87e4cac
JF
985 retval = request_irq(irq, handler, irqflags, devname, dev_id);
986 if (retval != 0) {
987 unbind_from_irq(irq);
988 return retval;
989 }
990
991 return irq;
992}
993
e46cdb66
JF
994void unbind_from_irqhandler(unsigned int irq, void *dev_id)
995{
996 free_irq(irq, dev_id);
997 unbind_from_irq(irq);
998}
999EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1000
f87e4cac
JF
1001void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1002{
1003 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1004 BUG_ON(irq < 0);
1005 notify_remote_via_irq(irq);
1006}
1007
ee523ca1
JF
1008irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1009{
1010 struct shared_info *sh = HYPERVISOR_shared_info;
1011 int cpu = smp_processor_id();
cb52e6d9 1012 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
1013 int i;
1014 unsigned long flags;
1015 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1016 struct vcpu_info *v;
ee523ca1
JF
1017
1018 spin_lock_irqsave(&debug_lock, flags);
1019
cb52e6d9 1020 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1021
1022 for_each_online_cpu(i) {
cb52e6d9
IC
1023 int pending;
1024 v = per_cpu(xen_vcpu, i);
1025 pending = (get_irq_regs() && i == cpu)
1026 ? xen_irqs_disabled(get_irq_regs())
1027 : v->evtchn_upcall_mask;
1028 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1029 pending, v->evtchn_upcall_pending,
1030 (int)(sizeof(v->evtchn_pending_sel)*2),
1031 v->evtchn_pending_sel);
1032 }
1033 v = per_cpu(xen_vcpu, cpu);
1034
1035 printk("\npending:\n ");
1036 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1037 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1038 sh->evtchn_pending[i],
1039 i % 8 == 0 ? "\n " : " ");
1040 printk("\nglobal mask:\n ");
1041 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1042 printk("%0*lx%s",
1043 (int)(sizeof(sh->evtchn_mask[0])*2),
1044 sh->evtchn_mask[i],
1045 i % 8 == 0 ? "\n " : " ");
1046
1047 printk("\nglobally unmasked:\n ");
1048 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1049 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1050 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1051 i % 8 == 0 ? "\n " : " ");
1052
1053 printk("\nlocal cpu%d mask:\n ", cpu);
1054 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1055 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1056 cpu_evtchn[i],
1057 i % 8 == 0 ? "\n " : " ");
1058
1059 printk("\nlocally unmasked:\n ");
1060 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1061 unsigned long pending = sh->evtchn_pending[i]
1062 & ~sh->evtchn_mask[i]
1063 & cpu_evtchn[i];
1064 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1065 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1066 }
ee523ca1
JF
1067
1068 printk("\npending list:\n");
cb52e6d9 1069 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1070 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1071 int word_idx = i / BITS_PER_LONG;
1072 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1073 cpu_from_evtchn(i), i,
cb52e6d9
IC
1074 evtchn_to_irq[i],
1075 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1076 ? "" : " l2-clear",
1077 !sync_test_bit(i, sh->evtchn_mask)
1078 ? "" : " globally-masked",
1079 sync_test_bit(i, cpu_evtchn)
1080 ? "" : " locally-masked");
ee523ca1
JF
1081 }
1082 }
1083
1084 spin_unlock_irqrestore(&debug_lock, flags);
1085
1086 return IRQ_HANDLED;
1087}
1088
245b2e70
TH
1089static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1090
e46cdb66
JF
1091/*
1092 * Search the CPUs pending events bitmasks. For each one found, map
1093 * the event number to an irq, and feed it into do_IRQ() for
1094 * handling.
1095 *
1096 * Xen uses a two-level bitmap to speed searching. The first level is
1097 * a bitset of words which contain pending event bits. The second
1098 * level is a bitset of pending events themselves.
1099 */
38e20b07 1100static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1101{
1102 int cpu = get_cpu();
1103 struct shared_info *s = HYPERVISOR_shared_info;
1104 struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
229664be 1105 unsigned count;
e46cdb66 1106
229664be
JF
1107 do {
1108 unsigned long pending_words;
e46cdb66 1109
229664be 1110 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1111
245b2e70 1112 if (__get_cpu_var(xed_nesting_count)++)
229664be 1113 goto out;
e46cdb66 1114
e849c3e9
IY
1115#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1116 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1117 wmb();
e849c3e9 1118#endif
229664be
JF
1119 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1120 while (pending_words != 0) {
1121 unsigned long pending_bits;
1122 int word_idx = __ffs(pending_words);
1123 pending_words &= ~(1UL << word_idx);
1124
1125 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1126 int bit_idx = __ffs(pending_bits);
1127 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1128 int irq = evtchn_to_irq[port];
ca4dbc66 1129 struct irq_desc *desc;
229664be 1130
3588fe2e
JF
1131 mask_evtchn(port);
1132 clear_evtchn(port);
1133
ca4dbc66
EB
1134 if (irq != -1) {
1135 desc = irq_to_desc(irq);
1136 if (desc)
1137 generic_handle_irq_desc(irq, desc);
1138 }
e46cdb66
JF
1139 }
1140 }
e46cdb66 1141
229664be
JF
1142 BUG_ON(!irqs_disabled());
1143
245b2e70
TH
1144 count = __get_cpu_var(xed_nesting_count);
1145 __get_cpu_var(xed_nesting_count) = 0;
183d03cc 1146 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1147
1148out:
38e20b07
SY
1149
1150 put_cpu();
1151}
1152
1153void xen_evtchn_do_upcall(struct pt_regs *regs)
1154{
1155 struct pt_regs *old_regs = set_irq_regs(regs);
1156
1157 exit_idle();
1158 irq_enter();
1159
1160 __xen_evtchn_do_upcall();
1161
3445a8fd
JF
1162 irq_exit();
1163 set_irq_regs(old_regs);
38e20b07 1164}
3445a8fd 1165
38e20b07
SY
1166void xen_hvm_evtchn_do_upcall(void)
1167{
1168 __xen_evtchn_do_upcall();
e46cdb66 1169}
183d03cc 1170EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1171
eb1e305f
JF
1172/* Rebind a new event channel to an existing irq. */
1173void rebind_evtchn_irq(int evtchn, int irq)
1174{
d77bbd4d
JF
1175 struct irq_info *info = info_for_irq(irq);
1176
eb1e305f
JF
1177 /* Make sure the irq is masked, since the new event channel
1178 will also be masked. */
1179 disable_irq(irq);
1180
1181 spin_lock(&irq_mapping_update_lock);
1182
1183 /* After resume the irq<->evtchn mappings are all cleared out */
1184 BUG_ON(evtchn_to_irq[evtchn] != -1);
1185 /* Expect irq to have been bound before,
d77bbd4d
JF
1186 so there should be a proper type */
1187 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1188
1189 evtchn_to_irq[evtchn] = irq;
ced40d0f 1190 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1191
1192 spin_unlock(&irq_mapping_update_lock);
1193
1194 /* new event channels are always bound to cpu 0 */
0de26520 1195 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1196
1197 /* Unmask the event channel. */
1198 enable_irq(irq);
1199}
1200
e46cdb66 1201/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1202static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1203{
1204 struct evtchn_bind_vcpu bind_vcpu;
1205 int evtchn = evtchn_from_irq(irq);
1206
183d03cc
SS
1207 /* events delivered via platform PCI interrupts are always
1208 * routed to vcpu 0 */
1209 if (!VALID_EVTCHN(evtchn) ||
1210 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1211 return -1;
e46cdb66
JF
1212
1213 /* Send future instances of this interrupt to other vcpu. */
1214 bind_vcpu.port = evtchn;
1215 bind_vcpu.vcpu = tcpu;
1216
1217 /*
1218 * If this fails, it usually just indicates that we're dealing with a
1219 * virq or IPI channel, which don't actually need to be rebound. Ignore
1220 * it, but don't do the xenlinux-level rebind in that case.
1221 */
1222 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1223 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1224
d5dedd45
YL
1225 return 0;
1226}
e46cdb66 1227
d5dedd45 1228static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
e46cdb66 1229{
0de26520 1230 unsigned tcpu = cpumask_first(dest);
d5dedd45
YL
1231
1232 return rebind_irq_to_cpu(irq, tcpu);
e46cdb66
JF
1233}
1234
642e0c88
IY
1235int resend_irq_on_evtchn(unsigned int irq)
1236{
1237 int masked, evtchn = evtchn_from_irq(irq);
1238 struct shared_info *s = HYPERVISOR_shared_info;
1239
1240 if (!VALID_EVTCHN(evtchn))
1241 return 1;
1242
1243 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1244 sync_set_bit(evtchn, s->evtchn_pending);
1245 if (!masked)
1246 unmask_evtchn(evtchn);
1247
1248 return 1;
1249}
1250
e46cdb66
JF
1251static void enable_dynirq(unsigned int irq)
1252{
1253 int evtchn = evtchn_from_irq(irq);
1254
1255 if (VALID_EVTCHN(evtchn))
1256 unmask_evtchn(evtchn);
1257}
1258
1259static void disable_dynirq(unsigned int irq)
1260{
1261 int evtchn = evtchn_from_irq(irq);
1262
1263 if (VALID_EVTCHN(evtchn))
1264 mask_evtchn(evtchn);
1265}
1266
1267static void ack_dynirq(unsigned int irq)
1268{
1269 int evtchn = evtchn_from_irq(irq);
1270
3588fe2e 1271 move_masked_irq(irq);
e46cdb66
JF
1272
1273 if (VALID_EVTCHN(evtchn))
3588fe2e 1274 unmask_evtchn(evtchn);
e46cdb66
JF
1275}
1276
1277static int retrigger_dynirq(unsigned int irq)
1278{
1279 int evtchn = evtchn_from_irq(irq);
ee8fa1c6 1280 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1281 int ret = 0;
1282
1283 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1284 int masked;
1285
1286 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1287 sync_set_bit(evtchn, sh->evtchn_pending);
1288 if (!masked)
1289 unmask_evtchn(evtchn);
e46cdb66
JF
1290 ret = 1;
1291 }
1292
1293 return ret;
1294}
1295
9a069c33
SS
1296static void restore_cpu_pirqs(void)
1297{
1298 int pirq, rc, irq, gsi;
1299 struct physdev_map_pirq map_irq;
1300
1301 for (pirq = 0; pirq < nr_irqs; pirq++) {
1302 irq = pirq_to_irq[pirq];
1303 if (irq == -1)
1304 continue;
1305
1306 /* save/restore of PT devices doesn't work, so at this point the
1307 * only devices present are GSI based emulated devices */
1308 gsi = gsi_from_irq(irq);
1309 if (!gsi)
1310 continue;
1311
1312 map_irq.domid = DOMID_SELF;
1313 map_irq.type = MAP_PIRQ_TYPE_GSI;
1314 map_irq.index = gsi;
1315 map_irq.pirq = pirq;
1316
1317 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1318 if (rc) {
1319 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1320 gsi, irq, pirq, rc);
1321 irq_info[irq] = mk_unbound_info();
1322 pirq_to_irq[pirq] = -1;
1323 continue;
1324 }
1325
1326 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1327
1328 startup_pirq(irq);
1329 }
1330}
1331
0e91398f
JF
1332static void restore_cpu_virqs(unsigned int cpu)
1333{
1334 struct evtchn_bind_virq bind_virq;
1335 int virq, irq, evtchn;
1336
1337 for (virq = 0; virq < NR_VIRQS; virq++) {
1338 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1339 continue;
1340
ced40d0f 1341 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1342
1343 /* Get a new binding from Xen. */
1344 bind_virq.virq = virq;
1345 bind_virq.vcpu = cpu;
1346 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1347 &bind_virq) != 0)
1348 BUG();
1349 evtchn = bind_virq.port;
1350
1351 /* Record the new mapping. */
1352 evtchn_to_irq[evtchn] = irq;
ced40d0f 1353 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1354 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1355 }
1356}
1357
1358static void restore_cpu_ipis(unsigned int cpu)
1359{
1360 struct evtchn_bind_ipi bind_ipi;
1361 int ipi, irq, evtchn;
1362
1363 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1364 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1365 continue;
1366
ced40d0f 1367 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1368
1369 /* Get a new binding from Xen. */
1370 bind_ipi.vcpu = cpu;
1371 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1372 &bind_ipi) != 0)
1373 BUG();
1374 evtchn = bind_ipi.port;
1375
1376 /* Record the new mapping. */
1377 evtchn_to_irq[evtchn] = irq;
ced40d0f 1378 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1379 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1380 }
1381}
1382
2d9e1e2f
JF
1383/* Clear an irq's pending state, in preparation for polling on it */
1384void xen_clear_irq_pending(int irq)
1385{
1386 int evtchn = evtchn_from_irq(irq);
1387
1388 if (VALID_EVTCHN(evtchn))
1389 clear_evtchn(evtchn);
1390}
d9a8814f 1391EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1392void xen_set_irq_pending(int irq)
1393{
1394 int evtchn = evtchn_from_irq(irq);
1395
1396 if (VALID_EVTCHN(evtchn))
1397 set_evtchn(evtchn);
1398}
1399
1400bool xen_test_irq_pending(int irq)
1401{
1402 int evtchn = evtchn_from_irq(irq);
1403 bool ret = false;
1404
1405 if (VALID_EVTCHN(evtchn))
1406 ret = test_evtchn(evtchn);
1407
1408 return ret;
1409}
1410
d9a8814f
KRW
1411/* Poll waiting for an irq to become pending with timeout. In the usual case,
1412 * the irq will be disabled so it won't deliver an interrupt. */
1413void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1414{
1415 evtchn_port_t evtchn = evtchn_from_irq(irq);
1416
1417 if (VALID_EVTCHN(evtchn)) {
1418 struct sched_poll poll;
1419
1420 poll.nr_ports = 1;
d9a8814f 1421 poll.timeout = timeout;
ff3c5362 1422 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1423
1424 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1425 BUG();
1426 }
1427}
d9a8814f
KRW
1428EXPORT_SYMBOL(xen_poll_irq_timeout);
1429/* Poll waiting for an irq to become pending. In the usual case, the
1430 * irq will be disabled so it won't deliver an interrupt. */
1431void xen_poll_irq(int irq)
1432{
1433 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1434}
2d9e1e2f 1435
0e91398f
JF
1436void xen_irq_resume(void)
1437{
1438 unsigned int cpu, irq, evtchn;
6903591f 1439 struct irq_desc *desc;
0e91398f
JF
1440
1441 init_evtchn_cpu_bindings();
1442
1443 /* New event-channel space is not 'live' yet. */
1444 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1445 mask_evtchn(evtchn);
1446
1447 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1448 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1449 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1450
1451 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1452 evtchn_to_irq[evtchn] = -1;
1453
1454 for_each_possible_cpu(cpu) {
1455 restore_cpu_virqs(cpu);
1456 restore_cpu_ipis(cpu);
1457 }
6903591f
IC
1458
1459 /*
1460 * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
1461 * are not handled by the IRQ core.
1462 */
1463 for_each_irq_desc(irq, desc) {
1464 if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
1465 continue;
1466 if (desc->status & IRQ_DISABLED)
1467 continue;
1468
1469 evtchn = evtchn_from_irq(irq);
1470 if (evtchn == -1)
1471 continue;
1472
1473 unmask_evtchn(evtchn);
1474 }
9a069c33
SS
1475
1476 restore_cpu_pirqs();
0e91398f
JF
1477}
1478
e46cdb66
JF
1479static struct irq_chip xen_dynamic_chip __read_mostly = {
1480 .name = "xen-dyn",
54a353a0
JF
1481
1482 .disable = disable_dynirq,
e46cdb66
JF
1483 .mask = disable_dynirq,
1484 .unmask = enable_dynirq,
54a353a0 1485
3588fe2e 1486 .eoi = ack_dynirq,
e46cdb66
JF
1487 .set_affinity = set_affinity_irq,
1488 .retrigger = retrigger_dynirq,
1489};
1490
d46a78b0
JF
1491static struct irq_chip xen_pirq_chip __read_mostly = {
1492 .name = "xen-pirq",
1493
1494 .startup = startup_pirq,
1495 .shutdown = shutdown_pirq,
1496
1497 .enable = enable_pirq,
1498 .unmask = enable_pirq,
1499
1500 .disable = disable_pirq,
1501 .mask = disable_pirq,
1502
1503 .ack = ack_pirq,
1504 .end = end_pirq,
1505
1506 .set_affinity = set_affinity_irq,
1507
1508 .retrigger = retrigger_dynirq,
1509};
1510
aaca4964
JF
1511static struct irq_chip xen_percpu_chip __read_mostly = {
1512 .name = "xen-percpu",
1513
1514 .disable = disable_dynirq,
1515 .mask = disable_dynirq,
1516 .unmask = enable_dynirq,
1517
1518 .ack = ack_dynirq,
1519};
1520
38e20b07
SY
1521int xen_set_callback_via(uint64_t via)
1522{
1523 struct xen_hvm_param a;
1524 a.domid = DOMID_SELF;
1525 a.index = HVM_PARAM_CALLBACK_IRQ;
1526 a.value = via;
1527 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1528}
1529EXPORT_SYMBOL_GPL(xen_set_callback_via);
1530
ca65f9fc 1531#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1532/* Vector callbacks are better than PCI interrupts to receive event
1533 * channel notifications because we can receive vector callbacks on any
1534 * vcpu and we don't need PCI support or APIC interactions. */
1535void xen_callback_vector(void)
1536{
1537 int rc;
1538 uint64_t callback_via;
1539 if (xen_have_vector_callback) {
1540 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1541 rc = xen_set_callback_via(callback_via);
1542 if (rc) {
1543 printk(KERN_ERR "Request for Xen HVM callback vector"
1544 " failed.\n");
1545 xen_have_vector_callback = 0;
1546 return;
1547 }
1548 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1549 "enabled\n");
1550 /* in the restore case the vector has already been allocated */
1551 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1552 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1553 }
1554}
ca65f9fc
SS
1555#else
1556void xen_callback_vector(void) {}
1557#endif
38e20b07 1558
e46cdb66
JF
1559void __init xen_init_IRQ(void)
1560{
e5fc7345 1561 int i;
c7a3589e 1562
a70c352a
PE
1563 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1564 GFP_KERNEL);
b21ddbf5
JF
1565 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1566
e5fc7345
SS
1567 /* We are using nr_irqs as the maximum number of pirq available but
1568 * that number is actually chosen by Xen and we don't know exactly
1569 * what it is. Be careful choosing high pirq numbers. */
1570 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1571 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1572 pirq_to_irq[i] = -1;
1573
b21ddbf5
JF
1574 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1575 GFP_KERNEL);
1576 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1577 evtchn_to_irq[i] = -1;
e46cdb66
JF
1578
1579 init_evtchn_cpu_bindings();
1580
1581 /* No event channels are 'live' right now. */
1582 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1583 mask_evtchn(i);
1584
38e20b07
SY
1585 if (xen_hvm_domain()) {
1586 xen_callback_vector();
1587 native_init_IRQ();
3942b740
SS
1588 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1589 * __acpi_register_gsi can point at the right function */
1590 pci_xen_hvm_init();
38e20b07
SY
1591 } else {
1592 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1593 if (xen_initial_domain())
1594 xen_setup_pirqs();
38e20b07 1595 }
e46cdb66 1596}