Commit | Line | Data |
---|---|---|
7768a13c | 1 | /* |
2817142f | 2 | * omap_wdt.c |
7768a13c | 3 | * |
2817142f | 4 | * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog |
7768a13c KS |
5 | * |
6 | * Author: MontaVista Software, Inc. | |
7 | * <gdavis@mvista.com> or <source@mvista.com> | |
8 | * | |
9 | * 2003 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is | |
11 | * licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | * | |
14 | * History: | |
15 | * | |
16 | * 20030527: George G. Davis <gdavis@mvista.com> | |
17 | * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c | |
18 | * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> | |
29fa0586 | 19 | * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> |
7768a13c KS |
20 | * |
21 | * Copyright (c) 2004 Texas Instruments. | |
22 | * 1. Modified to support OMAP1610 32-KHz watchdog timer | |
23 | * 2. Ported to 2.6 kernel | |
24 | * | |
25 | * Copyright (c) 2005 David Brownell | |
26 | * Use the driver model and standard identifiers; handle bigger timeouts. | |
27 | */ | |
28 | ||
27c766aa JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
7768a13c | 31 | #include <linux/module.h> |
7768a13c KS |
32 | #include <linux/types.h> |
33 | #include <linux/kernel.h> | |
7768a13c | 34 | #include <linux/mm.h> |
7768a13c KS |
35 | #include <linux/watchdog.h> |
36 | #include <linux/reboot.h> | |
7768a13c KS |
37 | #include <linux/err.h> |
38 | #include <linux/platform_device.h> | |
39 | #include <linux/moduleparam.h> | |
089ab079 | 40 | #include <linux/io.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
7ec5ad0f | 42 | #include <linux/pm_runtime.h> |
129f5577 | 43 | #include <linux/platform_data/omap-wd-timer.h> |
7768a13c KS |
44 | |
45 | #include "omap_wdt.h" | |
46 | ||
2dd7b244 PR |
47 | static bool nowayout = WATCHDOG_NOWAYOUT; |
48 | module_param(nowayout, bool, 0); | |
49 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " | |
50 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
51 | ||
7768a13c KS |
52 | static unsigned timer_margin; |
53 | module_param(timer_margin, uint, 0); | |
54 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | |
55 | ||
2817142f FB |
56 | struct omap_wdt_dev { |
57 | void __iomem *base; /* physical */ | |
58 | struct device *dev; | |
67c0f554 | 59 | bool omap_wdt_users; |
67c0f554 AK |
60 | int wdt_trgr_pattern; |
61 | struct mutex lock; /* to avoid races with PM */ | |
2817142f FB |
62 | }; |
63 | ||
67c0f554 | 64 | static void omap_wdt_reload(struct omap_wdt_dev *wdev) |
7768a13c | 65 | { |
2817142f | 66 | void __iomem *base = wdev->base; |
b3112180 | 67 | |
7768a13c | 68 | /* wait for posted write to complete */ |
4a7e94a0 | 69 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c | 70 | cpu_relax(); |
b3112180 | 71 | |
67c0f554 | 72 | wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; |
4a7e94a0 | 73 | writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); |
b3112180 | 74 | |
7768a13c | 75 | /* wait for posted write to complete */ |
4a7e94a0 | 76 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c KS |
77 | cpu_relax(); |
78 | /* reloaded WCRR from WLDR */ | |
79 | } | |
80 | ||
2817142f | 81 | static void omap_wdt_enable(struct omap_wdt_dev *wdev) |
7768a13c | 82 | { |
b3112180 FB |
83 | void __iomem *base = wdev->base; |
84 | ||
7768a13c | 85 | /* Sequence to enable the watchdog */ |
4a7e94a0 VK |
86 | writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); |
87 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c | 88 | cpu_relax(); |
b3112180 | 89 | |
4a7e94a0 VK |
90 | writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); |
91 | while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c KS |
92 | cpu_relax(); |
93 | } | |
94 | ||
2817142f | 95 | static void omap_wdt_disable(struct omap_wdt_dev *wdev) |
7768a13c | 96 | { |
b3112180 FB |
97 | void __iomem *base = wdev->base; |
98 | ||
7768a13c | 99 | /* sequence required to disable watchdog */ |
4a7e94a0 VK |
100 | writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
101 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c | 102 | cpu_relax(); |
b3112180 | 103 | |
4a7e94a0 VK |
104 | writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
105 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c KS |
106 | cpu_relax(); |
107 | } | |
108 | ||
67c0f554 AK |
109 | static void omap_wdt_set_timer(struct omap_wdt_dev *wdev, |
110 | unsigned int timeout) | |
7768a13c | 111 | { |
67c0f554 | 112 | u32 pre_margin = GET_WLDR_VAL(timeout); |
b3112180 | 113 | void __iomem *base = wdev->base; |
7768a13c KS |
114 | |
115 | /* just count up at 32 KHz */ | |
4a7e94a0 | 116 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) |
7768a13c | 117 | cpu_relax(); |
b3112180 | 118 | |
4a7e94a0 VK |
119 | writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR); |
120 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) | |
7768a13c KS |
121 | cpu_relax(); |
122 | } | |
123 | ||
67c0f554 | 124 | static int omap_wdt_start(struct watchdog_device *wdog) |
7768a13c | 125 | { |
67c0f554 | 126 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 FB |
127 | void __iomem *base = wdev->base; |
128 | ||
67c0f554 AK |
129 | mutex_lock(&wdev->lock); |
130 | ||
131 | wdev->omap_wdt_users = true; | |
7768a13c | 132 | |
7ec5ad0f | 133 | pm_runtime_get_sync(wdev->dev); |
7768a13c KS |
134 | |
135 | /* initialize prescaler */ | |
4a7e94a0 | 136 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) |
7768a13c | 137 | cpu_relax(); |
b3112180 | 138 | |
4a7e94a0 VK |
139 | writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
140 | while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) | |
7768a13c KS |
141 | cpu_relax(); |
142 | ||
67c0f554 AK |
143 | omap_wdt_set_timer(wdev, wdog->timeout); |
144 | omap_wdt_reload(wdev); /* trigger loading of new timeout value */ | |
2817142f | 145 | omap_wdt_enable(wdev); |
b3112180 | 146 | |
67c0f554 AK |
147 | mutex_unlock(&wdev->lock); |
148 | ||
149 | return 0; | |
7768a13c KS |
150 | } |
151 | ||
67c0f554 | 152 | static int omap_wdt_stop(struct watchdog_device *wdog) |
7768a13c | 153 | { |
67c0f554 | 154 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 | 155 | |
67c0f554 | 156 | mutex_lock(&wdev->lock); |
2817142f | 157 | omap_wdt_disable(wdev); |
7ec5ad0f | 158 | pm_runtime_put_sync(wdev->dev); |
67c0f554 AK |
159 | wdev->omap_wdt_users = false; |
160 | mutex_unlock(&wdev->lock); | |
7768a13c KS |
161 | return 0; |
162 | } | |
163 | ||
67c0f554 | 164 | static int omap_wdt_ping(struct watchdog_device *wdog) |
7768a13c | 165 | { |
67c0f554 | 166 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
b3112180 | 167 | |
67c0f554 AK |
168 | mutex_lock(&wdev->lock); |
169 | omap_wdt_reload(wdev); | |
170 | mutex_unlock(&wdev->lock); | |
171 | ||
172 | return 0; | |
7768a13c KS |
173 | } |
174 | ||
67c0f554 AK |
175 | static int omap_wdt_set_timeout(struct watchdog_device *wdog, |
176 | unsigned int timeout) | |
7768a13c | 177 | { |
67c0f554 | 178 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); |
7768a13c | 179 | |
67c0f554 AK |
180 | mutex_lock(&wdev->lock); |
181 | omap_wdt_disable(wdev); | |
182 | omap_wdt_set_timer(wdev, timeout); | |
183 | omap_wdt_enable(wdev); | |
184 | omap_wdt_reload(wdev); | |
185 | wdog->timeout = timeout; | |
186 | mutex_unlock(&wdev->lock); | |
187 | ||
188 | return 0; | |
7768a13c KS |
189 | } |
190 | ||
67c0f554 | 191 | static const struct watchdog_info omap_wdt_info = { |
fb1cbeae | 192 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
67c0f554 AK |
193 | .identity = "OMAP Watchdog", |
194 | }; | |
195 | ||
196 | static const struct watchdog_ops omap_wdt_ops = { | |
197 | .owner = THIS_MODULE, | |
198 | .start = omap_wdt_start, | |
199 | .stop = omap_wdt_stop, | |
200 | .ping = omap_wdt_ping, | |
201 | .set_timeout = omap_wdt_set_timeout, | |
7768a13c KS |
202 | }; |
203 | ||
2d991a16 | 204 | static int omap_wdt_probe(struct platform_device *pdev) |
7768a13c | 205 | { |
bc8fdfbe | 206 | struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev); |
67c0f554 | 207 | struct watchdog_device *omap_wdt; |
6e272061 | 208 | struct resource *res; |
2817142f | 209 | struct omap_wdt_dev *wdev; |
67c0f554 | 210 | u32 rs; |
b3112180 | 211 | int ret; |
7768a13c | 212 | |
4f4753d9 | 213 | omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL); |
67c0f554 AK |
214 | if (!omap_wdt) |
215 | return -ENOMEM; | |
216 | ||
4f4753d9 AK |
217 | wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); |
218 | if (!wdev) | |
219 | return -ENOMEM; | |
b3112180 | 220 | |
67c0f554 | 221 | wdev->omap_wdt_users = false; |
67c0f554 AK |
222 | wdev->dev = &pdev->dev; |
223 | wdev->wdt_trgr_pattern = 0x1234; | |
224 | mutex_init(&wdev->lock); | |
2817142f | 225 | |
6e272061 JH |
226 | /* reserve static register mappings */ |
227 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
228 | wdev->base = devm_ioremap_resource(&pdev->dev, res); | |
229 | if (IS_ERR(wdev->base)) | |
230 | return PTR_ERR(wdev->base); | |
9f69e3b0 | 231 | |
67c0f554 AK |
232 | omap_wdt->info = &omap_wdt_info; |
233 | omap_wdt->ops = &omap_wdt_ops; | |
234 | omap_wdt->min_timeout = TIMER_MARGIN_MIN; | |
235 | omap_wdt->max_timeout = TIMER_MARGIN_MAX; | |
236 | ||
a4f741e3 | 237 | if (watchdog_init_timeout(omap_wdt, timer_margin, &pdev->dev) < 0) |
67c0f554 AK |
238 | omap_wdt->timeout = TIMER_MARGIN_DEFAULT; |
239 | ||
240 | watchdog_set_drvdata(omap_wdt, wdev); | |
241 | watchdog_set_nowayout(omap_wdt, nowayout); | |
242 | ||
243 | platform_set_drvdata(pdev, omap_wdt); | |
7768a13c | 244 | |
7ec5ad0f VC |
245 | pm_runtime_enable(wdev->dev); |
246 | pm_runtime_get_sync(wdev->dev); | |
789cd470 | 247 | |
67c0f554 AK |
248 | if (pdata && pdata->read_reset_sources) |
249 | rs = pdata->read_reset_sources(); | |
250 | else | |
251 | rs = 0; | |
252 | omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ? | |
253 | WDIOF_CARDRESET : 0; | |
7768a13c | 254 | |
67c0f554 | 255 | omap_wdt_disable(wdev); |
2817142f | 256 | |
67c0f554 | 257 | ret = watchdog_register_device(omap_wdt); |
1ba85387 AK |
258 | if (ret) { |
259 | pm_runtime_disable(wdev->dev); | |
260 | return ret; | |
261 | } | |
7768a13c | 262 | |
2817142f | 263 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
4a7e94a0 | 264 | readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
67c0f554 | 265 | omap_wdt->timeout); |
7768a13c | 266 | |
7ec5ad0f | 267 | pm_runtime_put_sync(wdev->dev); |
789cd470 | 268 | |
7768a13c | 269 | return 0; |
7768a13c KS |
270 | } |
271 | ||
272 | static void omap_wdt_shutdown(struct platform_device *pdev) | |
273 | { | |
67c0f554 AK |
274 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
275 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
2817142f | 276 | |
67c0f554 | 277 | mutex_lock(&wdev->lock); |
0503add9 | 278 | if (wdev->omap_wdt_users) { |
2817142f | 279 | omap_wdt_disable(wdev); |
0503add9 PW |
280 | pm_runtime_put_sync(wdev->dev); |
281 | } | |
67c0f554 | 282 | mutex_unlock(&wdev->lock); |
7768a13c KS |
283 | } |
284 | ||
4b12b896 | 285 | static int omap_wdt_remove(struct platform_device *pdev) |
7768a13c | 286 | { |
67c0f554 AK |
287 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
288 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
2817142f | 289 | |
12c583d8 | 290 | pm_runtime_disable(wdev->dev); |
67c0f554 | 291 | watchdog_unregister_device(wdog); |
b3112180 | 292 | |
7768a13c KS |
293 | return 0; |
294 | } | |
295 | ||
296 | #ifdef CONFIG_PM | |
297 | ||
298 | /* REVISIT ... not clear this is the best way to handle system suspend; and | |
299 | * it's very inappropriate for selective device suspend (e.g. suspending this | |
300 | * through sysfs rather than by stopping the watchdog daemon). Also, this | |
301 | * may not play well enough with NOWAYOUT... | |
302 | */ | |
303 | ||
304 | static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) | |
305 | { | |
67c0f554 AK |
306 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
307 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
b3112180 | 308 | |
67c0f554 | 309 | mutex_lock(&wdev->lock); |
0503add9 | 310 | if (wdev->omap_wdt_users) { |
2817142f | 311 | omap_wdt_disable(wdev); |
0503add9 PW |
312 | pm_runtime_put_sync(wdev->dev); |
313 | } | |
67c0f554 | 314 | mutex_unlock(&wdev->lock); |
b3112180 | 315 | |
7768a13c KS |
316 | return 0; |
317 | } | |
318 | ||
319 | static int omap_wdt_resume(struct platform_device *pdev) | |
320 | { | |
67c0f554 AK |
321 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
322 | struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); | |
b3112180 | 323 | |
67c0f554 | 324 | mutex_lock(&wdev->lock); |
2817142f | 325 | if (wdev->omap_wdt_users) { |
0503add9 | 326 | pm_runtime_get_sync(wdev->dev); |
2817142f | 327 | omap_wdt_enable(wdev); |
67c0f554 | 328 | omap_wdt_reload(wdev); |
7768a13c | 329 | } |
67c0f554 | 330 | mutex_unlock(&wdev->lock); |
b3112180 | 331 | |
7768a13c KS |
332 | return 0; |
333 | } | |
334 | ||
335 | #else | |
336 | #define omap_wdt_suspend NULL | |
337 | #define omap_wdt_resume NULL | |
338 | #endif | |
339 | ||
e6ca04ea XJ |
340 | static const struct of_device_id omap_wdt_of_match[] = { |
341 | { .compatible = "ti,omap3-wdt", }, | |
342 | {}, | |
343 | }; | |
344 | MODULE_DEVICE_TABLE(of, omap_wdt_of_match); | |
345 | ||
7768a13c KS |
346 | static struct platform_driver omap_wdt_driver = { |
347 | .probe = omap_wdt_probe, | |
82268714 | 348 | .remove = omap_wdt_remove, |
7768a13c KS |
349 | .shutdown = omap_wdt_shutdown, |
350 | .suspend = omap_wdt_suspend, | |
351 | .resume = omap_wdt_resume, | |
352 | .driver = { | |
7768a13c | 353 | .name = "omap_wdt", |
e6ca04ea | 354 | .of_match_table = omap_wdt_of_match, |
7768a13c KS |
355 | }, |
356 | }; | |
357 | ||
b8ec6118 | 358 | module_platform_driver(omap_wdt_driver); |
7768a13c KS |
359 | |
360 | MODULE_AUTHOR("George G. Davis"); | |
361 | MODULE_LICENSE("GPL"); | |
f37d193c | 362 | MODULE_ALIAS("platform:omap_wdt"); |