Commit | Line | Data |
---|---|---|
e9659e69 | 1 | /* |
9419c07c MS |
2 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
3 | * | |
4 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
e9659e69 | 11 | |
27c766aa JP |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
13 | ||
e9659e69 AC |
14 | #include <linux/module.h> |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/fs.h> | |
18 | #include <linux/miscdevice.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/watchdog.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/uaccess.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/of_address.h> | |
27 | ||
28 | /* Register offsets for the Wdt device */ | |
29 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
30 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
31 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
32 | ||
33 | /* Control/Status Register Masks */ | |
34 | #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ | |
35 | #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ | |
36 | #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ | |
37 | ||
38 | /* Control/Status Register 0/1 bits */ | |
39 | #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ | |
40 | ||
41 | /* SelfTest constants */ | |
42 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
43 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
44 | ||
45 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
46 | #define PFX WATCHDOG_NAME ": " | |
47 | ||
48 | struct xwdt_device { | |
49 | struct resource res; | |
50 | void __iomem *base; | |
51 | u32 nowayout; | |
52 | u32 wdt_interval; | |
53 | u32 boot_status; | |
54 | }; | |
55 | ||
56 | static struct xwdt_device xdev; | |
57 | ||
58 | static u32 timeout; | |
59 | static u32 control_status_reg; | |
60 | static u8 expect_close; | |
61 | static u8 no_timeout; | |
62 | static unsigned long driver_open; | |
63 | ||
64 | static DEFINE_SPINLOCK(spinlock); | |
65 | ||
66 | static void xwdt_start(void) | |
67 | { | |
68 | spin_lock(&spinlock); | |
69 | ||
70 | /* Clean previous status and enable the watchdog timer */ | |
71 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
72 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); | |
73 | ||
74 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
75 | xdev.base + XWT_TWCSR0_OFFSET); | |
76 | ||
77 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET); | |
78 | ||
79 | spin_unlock(&spinlock); | |
80 | } | |
81 | ||
82 | static void xwdt_stop(void) | |
83 | { | |
84 | spin_lock(&spinlock); | |
85 | ||
86 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
87 | ||
88 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
89 | xdev.base + XWT_TWCSR0_OFFSET); | |
90 | ||
91 | iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET); | |
92 | ||
93 | spin_unlock(&spinlock); | |
27c766aa | 94 | pr_info("Stopped!\n"); |
e9659e69 AC |
95 | } |
96 | ||
97 | static void xwdt_keepalive(void) | |
98 | { | |
99 | spin_lock(&spinlock); | |
100 | ||
101 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
102 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); | |
103 | iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET); | |
104 | ||
105 | spin_unlock(&spinlock); | |
106 | } | |
107 | ||
108 | static void xwdt_get_status(int *status) | |
109 | { | |
110 | int new_status; | |
111 | ||
112 | spin_lock(&spinlock); | |
113 | ||
114 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
115 | new_status = ((control_status_reg & | |
116 | (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK)) != 0); | |
117 | spin_unlock(&spinlock); | |
118 | ||
119 | *status = 0; | |
120 | if (new_status & 1) | |
121 | *status |= WDIOF_CARDRESET; | |
122 | } | |
123 | ||
124 | static u32 xwdt_selftest(void) | |
125 | { | |
126 | int i; | |
127 | u32 timer_value1; | |
128 | u32 timer_value2; | |
129 | ||
130 | spin_lock(&spinlock); | |
131 | ||
132 | timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET); | |
133 | timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET); | |
134 | ||
135 | for (i = 0; | |
136 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
137 | (timer_value2 == timer_value1)); i++) { | |
138 | timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET); | |
139 | } | |
140 | ||
141 | spin_unlock(&spinlock); | |
142 | ||
143 | if (timer_value2 != timer_value1) | |
144 | return ~XWT_TIMER_FAILED; | |
145 | else | |
146 | return XWT_TIMER_FAILED; | |
147 | } | |
148 | ||
149 | static int xwdt_open(struct inode *inode, struct file *file) | |
150 | { | |
151 | /* Only one process can handle the wdt at a time */ | |
152 | if (test_and_set_bit(0, &driver_open)) | |
153 | return -EBUSY; | |
154 | ||
155 | /* Make sure that the module are always loaded...*/ | |
156 | if (xdev.nowayout) | |
157 | __module_get(THIS_MODULE); | |
158 | ||
159 | xwdt_start(); | |
27c766aa | 160 | pr_info("Started...\n"); |
e9659e69 AC |
161 | |
162 | return nonseekable_open(inode, file); | |
163 | } | |
164 | ||
165 | static int xwdt_release(struct inode *inode, struct file *file) | |
166 | { | |
167 | if (expect_close == 42) { | |
168 | xwdt_stop(); | |
169 | } else { | |
27c766aa | 170 | pr_crit("Unexpected close, not stopping watchdog!\n"); |
e9659e69 AC |
171 | xwdt_keepalive(); |
172 | } | |
173 | ||
174 | clear_bit(0, &driver_open); | |
175 | expect_close = 0; | |
176 | return 0; | |
177 | } | |
178 | ||
179 | /* | |
180 | * xwdt_write: | |
181 | * @file: file handle to the watchdog | |
182 | * @buf: buffer to write (unused as data does not matter here | |
183 | * @count: count of bytes | |
184 | * @ppos: pointer to the position to write. No seeks allowed | |
185 | * | |
186 | * A write to a watchdog device is defined as a keepalive signal. Any | |
187 | * write of data will do, as we don't define content meaning. | |
188 | */ | |
189 | static ssize_t xwdt_write(struct file *file, const char __user *buf, | |
190 | size_t len, loff_t *ppos) | |
191 | { | |
192 | if (len) { | |
193 | if (!xdev.nowayout) { | |
194 | size_t i; | |
195 | ||
196 | /* In case it was set long ago */ | |
197 | expect_close = 0; | |
198 | ||
199 | for (i = 0; i != len; i++) { | |
200 | char c; | |
201 | ||
202 | if (get_user(c, buf + i)) | |
203 | return -EFAULT; | |
204 | if (c == 'V') | |
205 | expect_close = 42; | |
206 | } | |
207 | } | |
208 | xwdt_keepalive(); | |
209 | } | |
210 | return len; | |
211 | } | |
212 | ||
213 | static const struct watchdog_info ident = { | |
214 | .options = WDIOF_MAGICCLOSE | | |
215 | WDIOF_KEEPALIVEPING, | |
216 | .firmware_version = 1, | |
217 | .identity = WATCHDOG_NAME, | |
218 | }; | |
219 | ||
220 | /* | |
221 | * xwdt_ioctl: | |
222 | * @file: file handle to the device | |
223 | * @cmd: watchdog command | |
224 | * @arg: argument pointer | |
225 | * | |
226 | * The watchdog API defines a common set of functions for all watchdogs | |
227 | * according to their available features. | |
228 | */ | |
229 | static long xwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
230 | { | |
231 | int status; | |
232 | ||
233 | union { | |
234 | struct watchdog_info __user *ident; | |
235 | int __user *i; | |
236 | } uarg; | |
237 | ||
238 | uarg.i = (int __user *)arg; | |
239 | ||
240 | switch (cmd) { | |
241 | case WDIOC_GETSUPPORT: | |
242 | return copy_to_user(uarg.ident, &ident, | |
243 | sizeof(ident)) ? -EFAULT : 0; | |
244 | ||
245 | case WDIOC_GETBOOTSTATUS: | |
246 | return put_user(xdev.boot_status, uarg.i); | |
247 | ||
248 | case WDIOC_GETSTATUS: | |
249 | xwdt_get_status(&status); | |
250 | return put_user(status, uarg.i); | |
251 | ||
252 | case WDIOC_KEEPALIVE: | |
253 | xwdt_keepalive(); | |
254 | return 0; | |
255 | ||
256 | case WDIOC_GETTIMEOUT: | |
257 | if (no_timeout) | |
258 | return -ENOTTY; | |
259 | else | |
260 | return put_user(timeout, uarg.i); | |
261 | ||
262 | default: | |
263 | return -ENOTTY; | |
264 | } | |
265 | } | |
266 | ||
267 | static const struct file_operations xwdt_fops = { | |
268 | .owner = THIS_MODULE, | |
269 | .llseek = no_llseek, | |
270 | .write = xwdt_write, | |
271 | .open = xwdt_open, | |
272 | .release = xwdt_release, | |
273 | .unlocked_ioctl = xwdt_ioctl, | |
274 | }; | |
275 | ||
276 | static struct miscdevice xwdt_miscdev = { | |
277 | .minor = WATCHDOG_MINOR, | |
278 | .name = "watchdog", | |
279 | .fops = &xwdt_fops, | |
280 | }; | |
281 | ||
2d991a16 | 282 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 AC |
283 | { |
284 | int rc; | |
285 | u32 *tmptr; | |
286 | u32 *pfreq; | |
287 | ||
288 | no_timeout = 0; | |
289 | ||
90fe6c60 | 290 | pfreq = (u32 *)of_get_property(pdev->dev.of_node, |
e9659e69 AC |
291 | "clock-frequency", NULL); |
292 | ||
293 | if (pfreq == NULL) { | |
27c766aa | 294 | pr_warn("The watchdog clock frequency cannot be obtained!\n"); |
e9659e69 AC |
295 | no_timeout = 1; |
296 | } | |
297 | ||
298 | rc = of_address_to_resource(pdev->dev.of_node, 0, &xdev.res); | |
299 | if (rc) { | |
27c766aa | 300 | pr_warn("invalid address!\n"); |
e9659e69 AC |
301 | return rc; |
302 | } | |
303 | ||
304 | tmptr = (u32 *)of_get_property(pdev->dev.of_node, | |
305 | "xlnx,wdt-interval", NULL); | |
306 | if (tmptr == NULL) { | |
27c766aa | 307 | pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n"); |
e9659e69 AC |
308 | no_timeout = 1; |
309 | } else { | |
310 | xdev.wdt_interval = *tmptr; | |
311 | } | |
312 | ||
313 | tmptr = (u32 *)of_get_property(pdev->dev.of_node, | |
314 | "xlnx,wdt-enable-once", NULL); | |
315 | if (tmptr == NULL) { | |
27c766aa | 316 | pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n"); |
e9659e69 AC |
317 | xdev.nowayout = WATCHDOG_NOWAYOUT; |
318 | } | |
319 | ||
320 | /* | |
321 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
322 | * ignored (interrupt), reset is only generated at second wdt overflow | |
323 | */ | |
324 | if (!no_timeout) | |
325 | timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq); | |
326 | ||
327 | if (!request_mem_region(xdev.res.start, | |
328 | xdev.res.end - xdev.res.start + 1, WATCHDOG_NAME)) { | |
329 | rc = -ENXIO; | |
27c766aa | 330 | pr_err("memory request failure!\n"); |
e9659e69 AC |
331 | goto err_out; |
332 | } | |
333 | ||
334 | xdev.base = ioremap(xdev.res.start, xdev.res.end - xdev.res.start + 1); | |
335 | if (xdev.base == NULL) { | |
336 | rc = -ENOMEM; | |
27c766aa | 337 | pr_err("ioremap failure!\n"); |
e9659e69 AC |
338 | goto release_mem; |
339 | } | |
340 | ||
341 | rc = xwdt_selftest(); | |
342 | if (rc == XWT_TIMER_FAILED) { | |
27c766aa | 343 | pr_err("SelfTest routine error!\n"); |
e9659e69 AC |
344 | goto unmap_io; |
345 | } | |
346 | ||
347 | xwdt_get_status(&xdev.boot_status); | |
348 | ||
349 | rc = misc_register(&xwdt_miscdev); | |
350 | if (rc) { | |
27c766aa JP |
351 | pr_err("cannot register miscdev on minor=%d (err=%d)\n", |
352 | xwdt_miscdev.minor, rc); | |
e9659e69 AC |
353 | goto unmap_io; |
354 | } | |
355 | ||
356 | if (no_timeout) | |
27c766aa JP |
357 | pr_info("driver loaded (timeout=? sec, nowayout=%d)\n", |
358 | xdev.nowayout); | |
e9659e69 | 359 | else |
27c766aa JP |
360 | pr_info("driver loaded (timeout=%d sec, nowayout=%d)\n", |
361 | timeout, xdev.nowayout); | |
e9659e69 AC |
362 | |
363 | expect_close = 0; | |
364 | clear_bit(0, &driver_open); | |
365 | ||
366 | return 0; | |
367 | ||
368 | unmap_io: | |
369 | iounmap(xdev.base); | |
370 | release_mem: | |
371 | release_mem_region(xdev.res.start, resource_size(&xdev.res)); | |
372 | err_out: | |
373 | return rc; | |
374 | } | |
375 | ||
4b12b896 | 376 | static int xwdt_remove(struct platform_device *dev) |
e9659e69 AC |
377 | { |
378 | misc_deregister(&xwdt_miscdev); | |
379 | iounmap(xdev.base); | |
380 | release_mem_region(xdev.res.start, resource_size(&xdev.res)); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | /* Match table for of_platform binding */ | |
1d131368 | 386 | static struct of_device_id xwdt_of_match[] = { |
e9659e69 AC |
387 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
388 | {}, | |
389 | }; | |
390 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
391 | ||
392 | static struct platform_driver xwdt_driver = { | |
393 | .probe = xwdt_probe, | |
82268714 | 394 | .remove = xwdt_remove, |
e9659e69 AC |
395 | .driver = { |
396 | .owner = THIS_MODULE, | |
397 | .name = WATCHDOG_NAME, | |
398 | .of_match_table = xwdt_of_match, | |
399 | }, | |
400 | }; | |
401 | ||
b8ec6118 | 402 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
403 | |
404 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
405 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
9419c07c | 406 | MODULE_LICENSE("GPL v2"); |
e9659e69 | 407 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |