Commit | Line | Data |
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e9659e69 | 1 | /* |
9419c07c MS |
2 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
3 | * | |
d14fd964 | 4 | * (C) Copyright 2013 - 2014 Xilinx, Inc. |
9419c07c MS |
5 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
e9659e69 | 12 | |
27c766aa JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
f06cdfd1 | 15 | #include <linux/err.h> |
e9659e69 AC |
16 | #include <linux/module.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
e9659e69 AC |
19 | #include <linux/ioport.h> |
20 | #include <linux/watchdog.h> | |
21 | #include <linux/io.h> | |
e9659e69 AC |
22 | #include <linux/of.h> |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_address.h> | |
25 | ||
26 | /* Register offsets for the Wdt device */ | |
27 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
28 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
29 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
30 | ||
31 | /* Control/Status Register Masks */ | |
32 | #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ | |
33 | #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ | |
34 | #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ | |
35 | ||
36 | /* Control/Status Register 0/1 bits */ | |
37 | #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ | |
38 | ||
39 | /* SelfTest constants */ | |
40 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
41 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
42 | ||
43 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
44 | #define PFX WATCHDOG_NAME ": " | |
45 | ||
46 | struct xwdt_device { | |
e9659e69 | 47 | void __iomem *base; |
e9659e69 | 48 | u32 wdt_interval; |
90663171 MS |
49 | spinlock_t spinlock; |
50 | struct watchdog_device xilinx_wdt_wdd; | |
e9659e69 AC |
51 | }; |
52 | ||
d14fd964 | 53 | static int xilinx_wdt_start(struct watchdog_device *wdd) |
e9659e69 | 54 | { |
5cf4e69d | 55 | u32 control_status_reg; |
90663171 | 56 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 57 | |
90663171 | 58 | spin_lock(&xdev->spinlock); |
e9659e69 AC |
59 | |
60 | /* Clean previous status and enable the watchdog timer */ | |
90663171 | 61 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
62 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
63 | ||
64 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
90663171 | 65 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 66 | |
90663171 | 67 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 68 | |
90663171 | 69 | spin_unlock(&xdev->spinlock); |
d14fd964 MS |
70 | |
71 | return 0; | |
e9659e69 AC |
72 | } |
73 | ||
d14fd964 | 74 | static int xilinx_wdt_stop(struct watchdog_device *wdd) |
e9659e69 | 75 | { |
5cf4e69d | 76 | u32 control_status_reg; |
90663171 | 77 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 78 | |
90663171 | 79 | spin_lock(&xdev->spinlock); |
e9659e69 | 80 | |
90663171 | 81 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
82 | |
83 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
90663171 | 84 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 85 | |
90663171 | 86 | iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 87 | |
90663171 | 88 | spin_unlock(&xdev->spinlock); |
27c766aa | 89 | pr_info("Stopped!\n"); |
d14fd964 MS |
90 | |
91 | return 0; | |
e9659e69 AC |
92 | } |
93 | ||
d14fd964 | 94 | static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
e9659e69 | 95 | { |
5cf4e69d | 96 | u32 control_status_reg; |
90663171 | 97 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 98 | |
90663171 | 99 | spin_lock(&xdev->spinlock); |
e9659e69 | 100 | |
90663171 | 101 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 102 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
90663171 | 103 | iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 104 | |
90663171 | 105 | spin_unlock(&xdev->spinlock); |
e9659e69 | 106 | |
d14fd964 MS |
107 | return 0; |
108 | } | |
e9659e69 | 109 | |
d14fd964 MS |
110 | static const struct watchdog_info xilinx_wdt_ident = { |
111 | .options = WDIOF_MAGICCLOSE | | |
112 | WDIOF_KEEPALIVEPING, | |
113 | .firmware_version = 1, | |
114 | .identity = WATCHDOG_NAME, | |
115 | }; | |
e9659e69 | 116 | |
d14fd964 MS |
117 | static const struct watchdog_ops xilinx_wdt_ops = { |
118 | .owner = THIS_MODULE, | |
119 | .start = xilinx_wdt_start, | |
120 | .stop = xilinx_wdt_stop, | |
121 | .ping = xilinx_wdt_keepalive, | |
122 | }; | |
e9659e69 | 123 | |
90663171 | 124 | static u32 xwdt_selftest(struct xwdt_device *xdev) |
e9659e69 AC |
125 | { |
126 | int i; | |
127 | u32 timer_value1; | |
128 | u32 timer_value2; | |
129 | ||
90663171 | 130 | spin_lock(&xdev->spinlock); |
e9659e69 | 131 | |
90663171 MS |
132 | timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); |
133 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); | |
e9659e69 AC |
134 | |
135 | for (i = 0; | |
136 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
137 | (timer_value2 == timer_value1)); i++) { | |
90663171 | 138 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
e9659e69 AC |
139 | } |
140 | ||
90663171 | 141 | spin_unlock(&xdev->spinlock); |
e9659e69 AC |
142 | |
143 | if (timer_value2 != timer_value1) | |
144 | return ~XWT_TIMER_FAILED; | |
145 | else | |
146 | return XWT_TIMER_FAILED; | |
147 | } | |
148 | ||
2d991a16 | 149 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 AC |
150 | { |
151 | int rc; | |
152 | u32 *tmptr; | |
153 | u32 *pfreq; | |
f06cdfd1 | 154 | struct resource *res; |
90663171 | 155 | struct xwdt_device *xdev; |
ffb8eee4 | 156 | bool no_timeout = false; |
90663171 MS |
157 | struct watchdog_device *xilinx_wdt_wdd; |
158 | ||
159 | xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); | |
160 | if (!xdev) | |
161 | return -ENOMEM; | |
162 | ||
163 | xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; | |
164 | xilinx_wdt_wdd->info = &xilinx_wdt_ident; | |
165 | xilinx_wdt_wdd->ops = &xilinx_wdt_ops; | |
166 | xilinx_wdt_wdd->parent = &pdev->dev; | |
e9659e69 | 167 | |
f06cdfd1 | 168 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
90663171 MS |
169 | xdev->base = devm_ioremap_resource(&pdev->dev, res); |
170 | if (IS_ERR(xdev->base)) | |
171 | return PTR_ERR(xdev->base); | |
f06cdfd1 | 172 | |
90fe6c60 | 173 | pfreq = (u32 *)of_get_property(pdev->dev.of_node, |
e9659e69 AC |
174 | "clock-frequency", NULL); |
175 | ||
176 | if (pfreq == NULL) { | |
27c766aa | 177 | pr_warn("The watchdog clock frequency cannot be obtained!\n"); |
ffb8eee4 | 178 | no_timeout = true; |
e9659e69 AC |
179 | } |
180 | ||
e9659e69 AC |
181 | tmptr = (u32 *)of_get_property(pdev->dev.of_node, |
182 | "xlnx,wdt-interval", NULL); | |
183 | if (tmptr == NULL) { | |
27c766aa | 184 | pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n"); |
ffb8eee4 | 185 | no_timeout = true; |
e9659e69 | 186 | } else { |
90663171 | 187 | xdev->wdt_interval = *tmptr; |
e9659e69 AC |
188 | } |
189 | ||
190 | tmptr = (u32 *)of_get_property(pdev->dev.of_node, | |
191 | "xlnx,wdt-enable-once", NULL); | |
192 | if (tmptr == NULL) { | |
27c766aa | 193 | pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n"); |
90663171 | 194 | watchdog_set_nowayout(xilinx_wdt_wdd, true); |
e9659e69 AC |
195 | } |
196 | ||
197 | /* | |
198 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
199 | * ignored (interrupt), reset is only generated at second wdt overflow | |
200 | */ | |
201 | if (!no_timeout) | |
90663171 MS |
202 | xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / |
203 | *pfreq); | |
204 | ||
205 | spin_lock_init(&xdev->spinlock); | |
206 | watchdog_set_drvdata(xilinx_wdt_wdd, xdev); | |
e9659e69 | 207 | |
90663171 | 208 | rc = xwdt_selftest(xdev); |
e9659e69 | 209 | if (rc == XWT_TIMER_FAILED) { |
27c766aa | 210 | pr_err("SelfTest routine error!\n"); |
f06cdfd1 | 211 | return rc; |
e9659e69 AC |
212 | } |
213 | ||
90663171 | 214 | rc = watchdog_register_device(xilinx_wdt_wdd); |
e9659e69 | 215 | if (rc) { |
d14fd964 | 216 | pr_err("cannot register watchdog (err=%d)\n", rc); |
f06cdfd1 | 217 | return rc; |
e9659e69 AC |
218 | } |
219 | ||
d14fd964 | 220 | dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n", |
90663171 MS |
221 | xdev->base, xilinx_wdt_wdd->timeout); |
222 | ||
223 | platform_set_drvdata(pdev, xdev); | |
e9659e69 AC |
224 | |
225 | return 0; | |
e9659e69 AC |
226 | } |
227 | ||
90663171 | 228 | static int xwdt_remove(struct platform_device *pdev) |
e9659e69 | 229 | { |
90663171 MS |
230 | struct xwdt_device *xdev = platform_get_drvdata(pdev); |
231 | ||
232 | watchdog_unregister_device(&xdev->xilinx_wdt_wdd); | |
e9659e69 AC |
233 | |
234 | return 0; | |
235 | } | |
236 | ||
237 | /* Match table for of_platform binding */ | |
1d131368 | 238 | static struct of_device_id xwdt_of_match[] = { |
8fce9b36 | 239 | { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
e9659e69 AC |
240 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
241 | {}, | |
242 | }; | |
243 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
244 | ||
245 | static struct platform_driver xwdt_driver = { | |
246 | .probe = xwdt_probe, | |
82268714 | 247 | .remove = xwdt_remove, |
e9659e69 AC |
248 | .driver = { |
249 | .owner = THIS_MODULE, | |
250 | .name = WATCHDOG_NAME, | |
251 | .of_match_table = xwdt_of_match, | |
252 | }, | |
253 | }; | |
254 | ||
b8ec6118 | 255 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
256 | |
257 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
258 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
9419c07c | 259 | MODULE_LICENSE("GPL v2"); |