Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
49b1f4b4 | 2 | * Frame buffer driver for Trident TGUI, Blade and Image series |
1da177e4 | 3 | * |
245a2c2c | 4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> |
ddb53d48 | 5 | * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl> |
1da177e4 LT |
6 | * |
7 | * CREDITS:(in order of appearance) | |
245a2c2c KH |
8 | * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video |
9 | * Special thanks ;) to Mattia Crivellini <tia@mclink.it> | |
10 | * much inspired by the XFree86 4.x Trident driver sources | |
11 | * by Alan Hourihane the FreeVGA project | |
12 | * Francesco Salvestrini <salvestrini@users.sf.net> XP support, | |
13 | * code, suggestions | |
1da177e4 | 14 | * TODO: |
245a2c2c | 15 | * timing value tweaking so it looks good on every monitor in every mode |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/fb.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/pci.h> | |
22 | ||
23 | #include <linux/delay.h> | |
10172ed6 | 24 | #include <video/vga.h> |
1da177e4 LT |
25 | #include <video/trident.h> |
26 | ||
1da177e4 | 27 | struct tridentfb_par { |
245a2c2c | 28 | void __iomem *io_virt; /* iospace virtual memory address */ |
ea8ee55c | 29 | u32 pseudo_pal[16]; |
122e8ad3 | 30 | int chip_id; |
6eed8e1e | 31 | int flatpanel; |
d9cad04b KH |
32 | void (*init_accel) (struct tridentfb_par *, int, int); |
33 | void (*wait_engine) (struct tridentfb_par *); | |
34 | void (*fill_rect) | |
35 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
36 | void (*copy_rect) | |
37 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
0292be4a KH |
38 | void (*image_blit) |
39 | (struct tridentfb_par *par, const char*, | |
40 | u32, u32, u32, u32, u32, u32); | |
5cf13845 | 41 | unsigned char eng_oper; /* engine operation... */ |
1da177e4 LT |
42 | }; |
43 | ||
1da177e4 | 44 | static struct fb_fix_screeninfo tridentfb_fix = { |
245a2c2c | 45 | .id = "Trident", |
1da177e4 LT |
46 | .type = FB_TYPE_PACKED_PIXELS, |
47 | .ypanstep = 1, | |
48 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
49 | .accel = FB_ACCEL_NONE, | |
50 | }; | |
51 | ||
1da177e4 LT |
52 | /* defaults which are normally overriden by user values */ |
53 | ||
54 | /* video mode */ | |
5cf13845 | 55 | static char *mode_option __devinitdata = "640x480-8@60"; |
6eed8e1e | 56 | static int bpp __devinitdata = 8; |
1da177e4 | 57 | |
6eed8e1e | 58 | static int noaccel __devinitdata; |
1da177e4 LT |
59 | |
60 | static int center; | |
61 | static int stretch; | |
62 | ||
6eed8e1e KH |
63 | static int fp __devinitdata; |
64 | static int crt __devinitdata; | |
1da177e4 | 65 | |
6eed8e1e KH |
66 | static int memsize __devinitdata; |
67 | static int memdiff __devinitdata; | |
1da177e4 LT |
68 | static int nativex; |
69 | ||
07f41e45 KH |
70 | module_param(mode_option, charp, 0); |
71 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | |
9e3f0ca8 KH |
72 | module_param_named(mode, mode_option, charp, 0); |
73 | MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); | |
1da177e4 LT |
74 | module_param(bpp, int, 0); |
75 | module_param(center, int, 0); | |
76 | module_param(stretch, int, 0); | |
77 | module_param(noaccel, int, 0); | |
78 | module_param(memsize, int, 0); | |
79 | module_param(memdiff, int, 0); | |
80 | module_param(nativex, int, 0); | |
81 | module_param(fp, int, 0); | |
6eed8e1e | 82 | MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); |
1da177e4 | 83 | module_param(crt, int, 0); |
6eed8e1e | 84 | MODULE_PARM_DESC(crt, "Define if CRT is connected"); |
1da177e4 | 85 | |
5cf13845 | 86 | static inline int is_oldclock(int id) |
6bdf1035 | 87 | { |
a0d92256 KH |
88 | return (id == TGUI9440) || |
89 | (id == TGUI9660) || | |
0e73a47f KH |
90 | (id == CYBER9320); |
91 | } | |
92 | ||
5cf13845 | 93 | static inline int is_oldprotect(int id) |
0e73a47f | 94 | { |
5cf13845 | 95 | return is_oldclock(id) || |
0e73a47f | 96 | (id == PROVIDIA9685) || |
0e73a47f KH |
97 | (id == CYBER9382) || |
98 | (id == CYBER9385); | |
6bdf1035 KH |
99 | } |
100 | ||
5cf13845 | 101 | static inline int is_blade(int id) |
e0759a5f KH |
102 | { |
103 | return (id == BLADE3D) || | |
104 | (id == CYBERBLADEE4) || | |
105 | (id == CYBERBLADEi7) || | |
106 | (id == CYBERBLADEi7D) || | |
107 | (id == CYBERBLADEi1) || | |
108 | (id == CYBERBLADEi1D) || | |
109 | (id == CYBERBLADEAi1) || | |
110 | (id == CYBERBLADEAi1D); | |
111 | } | |
112 | ||
5cf13845 | 113 | static inline int is_xp(int id) |
e0759a5f KH |
114 | { |
115 | return (id == CYBERBLADEXPAi1) || | |
116 | (id == CYBERBLADEXPm8) || | |
117 | (id == CYBERBLADEXPm16); | |
118 | } | |
119 | ||
5cf13845 | 120 | static inline int is3Dchip(int id) |
1da177e4 | 121 | { |
5cf13845 | 122 | return is_blade(id) || is_xp(id) || |
245a2c2c KH |
123 | (id == CYBER9397) || (id == CYBER9397DVD) || |
124 | (id == CYBER9520) || (id == CYBER9525DVD) || | |
5cf13845 | 125 | (id == IMAGE975) || (id == IMAGE985); |
1da177e4 LT |
126 | } |
127 | ||
5cf13845 | 128 | static inline int iscyber(int id) |
1da177e4 LT |
129 | { |
130 | switch (id) { | |
245a2c2c KH |
131 | case CYBER9388: |
132 | case CYBER9382: | |
133 | case CYBER9385: | |
134 | case CYBER9397: | |
135 | case CYBER9397DVD: | |
136 | case CYBER9520: | |
137 | case CYBER9525DVD: | |
138 | case CYBERBLADEE4: | |
139 | case CYBERBLADEi7D: | |
140 | case CYBERBLADEi1: | |
141 | case CYBERBLADEi1D: | |
142 | case CYBERBLADEAi1: | |
143 | case CYBERBLADEAi1D: | |
144 | case CYBERBLADEXPAi1: | |
145 | return 1; | |
1da177e4 | 146 | |
245a2c2c | 147 | case CYBER9320: |
245a2c2c | 148 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ |
245a2c2c KH |
149 | default: |
150 | /* case CYBERBLDAEXPm8: Strange */ | |
151 | /* case CYBERBLDAEXPm16: Strange */ | |
152 | return 0; | |
1da177e4 LT |
153 | } |
154 | } | |
155 | ||
306fa6f6 KH |
156 | static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) |
157 | { | |
158 | fb_writeb(val, p->io_virt + reg); | |
159 | } | |
1da177e4 | 160 | |
306fa6f6 KH |
161 | static inline u8 t_inb(struct tridentfb_par *p, u16 reg) |
162 | { | |
163 | return fb_readb(p->io_virt + reg); | |
164 | } | |
1da177e4 | 165 | |
306fa6f6 KH |
166 | static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) |
167 | { | |
168 | fb_writel(v, par->io_virt + r); | |
169 | } | |
170 | ||
171 | static inline u32 readmmr(struct tridentfb_par *par, u16 r) | |
172 | { | |
173 | return fb_readl(par->io_virt + r); | |
174 | } | |
1da177e4 | 175 | |
1da177e4 LT |
176 | /* |
177 | * Blade specific acceleration. | |
178 | */ | |
179 | ||
245a2c2c | 180 | #define point(x, y) ((y) << 16 | (x)) |
1da177e4 | 181 | |
306fa6f6 | 182 | static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 183 | { |
245a2c2c | 184 | int v1 = (pitch >> 3) << 20; |
49b1f4b4 KH |
185 | int tmp = bpp == 24 ? 2 : (bpp >> 4); |
186 | int v2 = v1 | (tmp << 29); | |
187 | ||
306fa6f6 KH |
188 | writemmr(par, 0x21C0, v2); |
189 | writemmr(par, 0x21C4, v2); | |
190 | writemmr(par, 0x21B8, v2); | |
191 | writemmr(par, 0x21BC, v2); | |
192 | writemmr(par, 0x21D0, v1); | |
193 | writemmr(par, 0x21D4, v1); | |
194 | writemmr(par, 0x21C8, v1); | |
195 | writemmr(par, 0x21CC, v1); | |
196 | writemmr(par, 0x216C, 0); | |
1da177e4 LT |
197 | } |
198 | ||
306fa6f6 | 199 | static void blade_wait_engine(struct tridentfb_par *par) |
1da177e4 | 200 | { |
49b1f4b4 KH |
201 | while (readmmr(par, STATUS) & 0xFA800000) |
202 | cpu_relax(); | |
1da177e4 LT |
203 | } |
204 | ||
306fa6f6 KH |
205 | static void blade_fill_rect(struct tridentfb_par *par, |
206 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 207 | { |
49b1f4b4 KH |
208 | writemmr(par, COLOR, c); |
209 | writemmr(par, ROP, rop ? ROP_X : ROP_S); | |
306fa6f6 | 210 | writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); |
1da177e4 | 211 | |
49b1f4b4 KH |
212 | writemmr(par, DST1, point(x, y)); |
213 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
1da177e4 LT |
214 | } |
215 | ||
0292be4a KH |
216 | static void blade_image_blit(struct tridentfb_par *par, const char *data, |
217 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 b) | |
218 | { | |
219 | unsigned size = ((w + 31) >> 5) * h; | |
220 | ||
221 | writemmr(par, COLOR, c); | |
222 | writemmr(par, BGCOLOR, b); | |
223 | writemmr(par, CMD, 0xa0000000 | 3 << 19); | |
224 | ||
225 | writemmr(par, DST1, point(x, y)); | |
226 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
227 | ||
228 | memcpy(par->io_virt + 0x10000, data, 4 * size); | |
229 | } | |
230 | ||
306fa6f6 KH |
231 | static void blade_copy_rect(struct tridentfb_par *par, |
232 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 233 | { |
1da177e4 | 234 | int direction = 2; |
49b1f4b4 KH |
235 | u32 s1 = point(x1, y1); |
236 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
237 | u32 d1 = point(x2, y2); | |
238 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 LT |
239 | |
240 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | |
245a2c2c | 241 | direction = 0; |
1da177e4 | 242 | |
306fa6f6 KH |
243 | writemmr(par, ROP, ROP_S); |
244 | writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); | |
1da177e4 | 245 | |
49b1f4b4 KH |
246 | writemmr(par, SRC1, direction ? s2 : s1); |
247 | writemmr(par, SRC2, direction ? s1 : s2); | |
248 | writemmr(par, DST1, direction ? d2 : d1); | |
249 | writemmr(par, DST2, direction ? d1 : d2); | |
1da177e4 LT |
250 | } |
251 | ||
1da177e4 LT |
252 | /* |
253 | * BladeXP specific acceleration functions | |
254 | */ | |
255 | ||
306fa6f6 | 256 | static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 257 | { |
49b1f4b4 KH |
258 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
259 | int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); | |
1da177e4 LT |
260 | |
261 | switch (pitch << (bpp >> 3)) { | |
245a2c2c KH |
262 | case 8192: |
263 | case 512: | |
264 | x |= 0x00; | |
265 | break; | |
266 | case 1024: | |
267 | x |= 0x04; | |
268 | break; | |
269 | case 2048: | |
270 | x |= 0x08; | |
271 | break; | |
272 | case 4096: | |
273 | x |= 0x0C; | |
274 | break; | |
1da177e4 LT |
275 | } |
276 | ||
306fa6f6 | 277 | t_outb(par, x, 0x2125); |
1da177e4 | 278 | |
5cf13845 | 279 | par->eng_oper = x | 0x40; |
1da177e4 | 280 | |
306fa6f6 KH |
281 | writemmr(par, 0x2154, v1); |
282 | writemmr(par, 0x2150, v1); | |
283 | t_outb(par, 3, 0x2126); | |
1da177e4 LT |
284 | } |
285 | ||
306fa6f6 | 286 | static void xp_wait_engine(struct tridentfb_par *par) |
1da177e4 | 287 | { |
5cf13845 KH |
288 | int count = 0; |
289 | int timeout = 0; | |
1da177e4 | 290 | |
49b1f4b4 | 291 | while (t_inb(par, STATUS) & 0x80) { |
1da177e4 LT |
292 | count++; |
293 | if (count == 10000000) { | |
294 | /* Timeout */ | |
295 | count = 9990000; | |
296 | timeout++; | |
297 | if (timeout == 8) { | |
298 | /* Reset engine */ | |
49b1f4b4 | 299 | t_outb(par, 0x00, STATUS); |
1da177e4 LT |
300 | return; |
301 | } | |
302 | } | |
49b1f4b4 | 303 | cpu_relax(); |
1da177e4 LT |
304 | } |
305 | } | |
306 | ||
306fa6f6 KH |
307 | static void xp_fill_rect(struct tridentfb_par *par, |
308 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 309 | { |
306fa6f6 KH |
310 | writemmr(par, 0x2127, ROP_P); |
311 | writemmr(par, 0x2158, c); | |
49b1f4b4 KH |
312 | writemmr(par, DRAWFL, 0x4000); |
313 | writemmr(par, OLDDIM, point(h, w)); | |
314 | writemmr(par, OLDDST, point(y, x)); | |
315 | t_outb(par, 0x01, OLDCMD); | |
5cf13845 | 316 | t_outb(par, par->eng_oper, 0x2125); |
1da177e4 LT |
317 | } |
318 | ||
306fa6f6 KH |
319 | static void xp_copy_rect(struct tridentfb_par *par, |
320 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 321 | { |
245a2c2c | 322 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; |
5cf13845 | 323 | int direction = 0x0004; |
245a2c2c | 324 | |
1da177e4 LT |
325 | if ((x1 < x2) && (y1 == y2)) { |
326 | direction |= 0x0200; | |
327 | x1_tmp = x1 + w - 1; | |
328 | x2_tmp = x2 + w - 1; | |
329 | } else { | |
330 | x1_tmp = x1; | |
331 | x2_tmp = x2; | |
332 | } | |
245a2c2c | 333 | |
1da177e4 LT |
334 | if (y1 < y2) { |
335 | direction |= 0x0100; | |
336 | y1_tmp = y1 + h - 1; | |
337 | y2_tmp = y2 + h - 1; | |
245a2c2c | 338 | } else { |
1da177e4 LT |
339 | y1_tmp = y1; |
340 | y2_tmp = y2; | |
341 | } | |
342 | ||
49b1f4b4 | 343 | writemmr(par, DRAWFL, direction); |
306fa6f6 | 344 | t_outb(par, ROP_S, 0x2127); |
49b1f4b4 KH |
345 | writemmr(par, OLDSRC, point(y1_tmp, x1_tmp)); |
346 | writemmr(par, OLDDST, point(y2_tmp, x2_tmp)); | |
347 | writemmr(par, OLDDIM, point(h, w)); | |
348 | t_outb(par, 0x01, OLDCMD); | |
1da177e4 LT |
349 | } |
350 | ||
1da177e4 LT |
351 | /* |
352 | * Image specific acceleration functions | |
353 | */ | |
306fa6f6 | 354 | static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 355 | { |
49b1f4b4 KH |
356 | int tmp = bpp == 24 ? 2: (bpp >> 4); |
357 | ||
306fa6f6 KH |
358 | writemmr(par, 0x2120, 0xF0000000); |
359 | writemmr(par, 0x2120, 0x40000000 | tmp); | |
360 | writemmr(par, 0x2120, 0x80000000); | |
361 | writemmr(par, 0x2144, 0x00000000); | |
362 | writemmr(par, 0x2148, 0x00000000); | |
363 | writemmr(par, 0x2150, 0x00000000); | |
364 | writemmr(par, 0x2154, 0x00000000); | |
365 | writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); | |
366 | writemmr(par, 0x216C, 0x00000000); | |
367 | writemmr(par, 0x2170, 0x00000000); | |
368 | writemmr(par, 0x217C, 0x00000000); | |
369 | writemmr(par, 0x2120, 0x10000000); | |
370 | writemmr(par, 0x2130, (2047 << 16) | 2047); | |
1da177e4 LT |
371 | } |
372 | ||
306fa6f6 | 373 | static void image_wait_engine(struct tridentfb_par *par) |
1da177e4 | 374 | { |
49b1f4b4 KH |
375 | while (readmmr(par, 0x2164) & 0xF0000000) |
376 | cpu_relax(); | |
1da177e4 LT |
377 | } |
378 | ||
306fa6f6 KH |
379 | static void image_fill_rect(struct tridentfb_par *par, |
380 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 381 | { |
306fa6f6 KH |
382 | writemmr(par, 0x2120, 0x80000000); |
383 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
1da177e4 | 384 | |
306fa6f6 | 385 | writemmr(par, 0x2144, c); |
1da177e4 | 386 | |
49b1f4b4 KH |
387 | writemmr(par, DST1, point(x, y)); |
388 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
1da177e4 | 389 | |
306fa6f6 | 390 | writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); |
1da177e4 LT |
391 | } |
392 | ||
306fa6f6 KH |
393 | static void image_copy_rect(struct tridentfb_par *par, |
394 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 395 | { |
2c86a0c2 | 396 | int direction = 0x4; |
49b1f4b4 KH |
397 | u32 s1 = point(x1, y1); |
398 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
399 | u32 d1 = point(x2, y2); | |
400 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 | 401 | |
245a2c2c KH |
402 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) |
403 | direction = 0; | |
404 | ||
306fa6f6 KH |
405 | writemmr(par, 0x2120, 0x80000000); |
406 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
245a2c2c | 407 | |
49b1f4b4 KH |
408 | writemmr(par, SRC1, direction ? s2 : s1); |
409 | writemmr(par, SRC2, direction ? s1 : s2); | |
410 | writemmr(par, DST1, direction ? d2 : d1); | |
411 | writemmr(par, DST2, direction ? d1 : d2); | |
306fa6f6 KH |
412 | writemmr(par, 0x2124, |
413 | 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | |
245a2c2c | 414 | } |
1da177e4 | 415 | |
bcac2d5f KH |
416 | /* |
417 | * TGUI 9440/96XX acceleration | |
418 | */ | |
419 | ||
420 | static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
421 | { | |
49b1f4b4 | 422 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
bcac2d5f KH |
423 | |
424 | /* disable clipping */ | |
425 | writemmr(par, 0x2148, 0); | |
426 | writemmr(par, 0x214C, point(4095, 2047)); | |
427 | ||
bcac2d5f KH |
428 | switch ((pitch * bpp) / 8) { |
429 | case 8192: | |
430 | case 512: | |
431 | x |= 0x00; | |
432 | break; | |
433 | case 1024: | |
434 | x |= 0x04; | |
435 | break; | |
436 | case 2048: | |
437 | x |= 0x08; | |
438 | break; | |
439 | case 4096: | |
440 | x |= 0x0C; | |
441 | break; | |
442 | } | |
443 | ||
444 | fb_writew(x, par->io_virt + 0x2122); | |
445 | } | |
446 | ||
447 | static void tgui_fill_rect(struct tridentfb_par *par, | |
448 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
449 | { | |
450 | t_outb(par, ROP_P, 0x2127); | |
49b1f4b4 KH |
451 | writemmr(par, OLDCLR, c); |
452 | writemmr(par, DRAWFL, 0x4020); | |
453 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
454 | writemmr(par, OLDDST, point(x, y)); | |
455 | t_outb(par, 1, OLDCMD); | |
bcac2d5f KH |
456 | } |
457 | ||
458 | static void tgui_copy_rect(struct tridentfb_par *par, | |
459 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
460 | { | |
461 | int flags = 0; | |
462 | u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | |
463 | ||
464 | if ((x1 < x2) && (y1 == y2)) { | |
465 | flags |= 0x0200; | |
466 | x1_tmp = x1 + w - 1; | |
467 | x2_tmp = x2 + w - 1; | |
468 | } else { | |
469 | x1_tmp = x1; | |
470 | x2_tmp = x2; | |
471 | } | |
472 | ||
473 | if (y1 < y2) { | |
474 | flags |= 0x0100; | |
475 | y1_tmp = y1 + h - 1; | |
476 | y2_tmp = y2 + h - 1; | |
477 | } else { | |
478 | y1_tmp = y1; | |
479 | y2_tmp = y2; | |
480 | } | |
481 | ||
49b1f4b4 | 482 | writemmr(par, DRAWFL, 0x4 | flags); |
bcac2d5f | 483 | t_outb(par, ROP_S, 0x2127); |
49b1f4b4 KH |
484 | writemmr(par, OLDSRC, point(x1_tmp, y1_tmp)); |
485 | writemmr(par, OLDDST, point(x2_tmp, y2_tmp)); | |
486 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
487 | t_outb(par, 1, OLDCMD); | |
bcac2d5f KH |
488 | } |
489 | ||
1da177e4 LT |
490 | /* |
491 | * Accel functions called by the upper layers | |
492 | */ | |
245a2c2c KH |
493 | static void tridentfb_fillrect(struct fb_info *info, |
494 | const struct fb_fillrect *fr) | |
1da177e4 | 495 | { |
306fa6f6 | 496 | struct tridentfb_par *par = info->par; |
49b1f4b4 | 497 | int col; |
245a2c2c | 498 | |
01a2d9ed KH |
499 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
500 | cfb_fillrect(info, fr); | |
501 | return; | |
502 | } | |
49b1f4b4 KH |
503 | if (info->var.bits_per_pixel == 8) { |
504 | col = fr->color; | |
245a2c2c KH |
505 | col |= col << 8; |
506 | col |= col << 16; | |
49b1f4b4 | 507 | } else |
245a2c2c | 508 | col = ((u32 *)(info->pseudo_palette))[fr->color]; |
245a2c2c | 509 | |
49b1f4b4 | 510 | par->wait_engine(par); |
d9cad04b | 511 | par->fill_rect(par, fr->dx, fr->dy, fr->width, |
306fa6f6 | 512 | fr->height, col, fr->rop); |
1da177e4 | 513 | } |
49b1f4b4 | 514 | |
0292be4a KH |
515 | static void tridentfb_imageblit(struct fb_info *info, |
516 | const struct fb_image *img) | |
517 | { | |
518 | struct tridentfb_par *par = info->par; | |
519 | int col, bgcol; | |
520 | ||
521 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) { | |
522 | cfb_imageblit(info, img); | |
523 | return; | |
524 | } | |
525 | if (info->var.bits_per_pixel == 8) { | |
526 | col = img->fg_color; | |
527 | col |= col << 8; | |
528 | col |= col << 16; | |
529 | bgcol = img->bg_color; | |
530 | bgcol |= bgcol << 8; | |
531 | bgcol |= bgcol << 16; | |
532 | } else { | |
533 | col = ((u32 *)(info->pseudo_palette))[img->fg_color]; | |
534 | bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color]; | |
535 | } | |
536 | ||
537 | par->wait_engine(par); | |
538 | if (par->image_blit) | |
539 | par->image_blit(par, img->data, img->dx, img->dy, | |
540 | img->width, img->height, col, bgcol); | |
541 | else | |
542 | cfb_imageblit(info, img); | |
543 | } | |
544 | ||
245a2c2c KH |
545 | static void tridentfb_copyarea(struct fb_info *info, |
546 | const struct fb_copyarea *ca) | |
1da177e4 | 547 | { |
306fa6f6 KH |
548 | struct tridentfb_par *par = info->par; |
549 | ||
01a2d9ed KH |
550 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
551 | cfb_copyarea(info, ca); | |
552 | return; | |
553 | } | |
49b1f4b4 | 554 | par->wait_engine(par); |
d9cad04b | 555 | par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, |
306fa6f6 | 556 | ca->width, ca->height); |
49b1f4b4 KH |
557 | } |
558 | ||
559 | static int tridentfb_sync(struct fb_info *info) | |
560 | { | |
561 | struct tridentfb_par *par = info->par; | |
562 | ||
01a2d9ed KH |
563 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) |
564 | par->wait_engine(par); | |
49b1f4b4 | 565 | return 0; |
1da177e4 | 566 | } |
1da177e4 | 567 | |
1da177e4 LT |
568 | /* |
569 | * Hardware access functions | |
570 | */ | |
571 | ||
306fa6f6 | 572 | static inline unsigned char read3X4(struct tridentfb_par *par, int reg) |
1da177e4 | 573 | { |
10172ed6 | 574 | return vga_mm_rcrt(par->io_virt, reg); |
1da177e4 LT |
575 | } |
576 | ||
306fa6f6 KH |
577 | static inline void write3X4(struct tridentfb_par *par, int reg, |
578 | unsigned char val) | |
1da177e4 | 579 | { |
10172ed6 | 580 | vga_mm_wcrt(par->io_virt, reg, val); |
1da177e4 LT |
581 | } |
582 | ||
10172ed6 KH |
583 | static inline unsigned char read3CE(struct tridentfb_par *par, |
584 | unsigned char reg) | |
1da177e4 | 585 | { |
10172ed6 | 586 | return vga_mm_rgfx(par->io_virt, reg); |
1da177e4 LT |
587 | } |
588 | ||
306fa6f6 KH |
589 | static inline void writeAttr(struct tridentfb_par *par, int reg, |
590 | unsigned char val) | |
1da177e4 | 591 | { |
10172ed6 KH |
592 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
593 | vga_mm_wattr(par->io_virt, reg, val); | |
1da177e4 LT |
594 | } |
595 | ||
306fa6f6 KH |
596 | static inline void write3CE(struct tridentfb_par *par, int reg, |
597 | unsigned char val) | |
1da177e4 | 598 | { |
10172ed6 | 599 | vga_mm_wgfx(par->io_virt, reg, val); |
1da177e4 LT |
600 | } |
601 | ||
13b0de49 | 602 | static void enable_mmio(struct tridentfb_par *par) |
1da177e4 LT |
603 | { |
604 | /* Goto New Mode */ | |
10172ed6 | 605 | vga_io_rseq(0x0B); |
1da177e4 LT |
606 | |
607 | /* Unprotect registers */ | |
10172ed6 | 608 | vga_io_wseq(NewMode1, 0x80); |
13b0de49 KH |
609 | if (!is_oldprotect(par->chip_id)) |
610 | vga_io_wseq(Protection, 0x92); | |
245a2c2c | 611 | |
1da177e4 | 612 | /* Enable MMIO */ |
245a2c2c | 613 | outb(PCIReg, 0x3D4); |
1da177e4 | 614 | outb(inb(0x3D5) | 0x01, 0x3D5); |
e8ed857c KH |
615 | } |
616 | ||
306fa6f6 | 617 | static void disable_mmio(struct tridentfb_par *par) |
e8ed857c | 618 | { |
e8ed857c | 619 | /* Goto New Mode */ |
10172ed6 | 620 | vga_mm_rseq(par->io_virt, 0x0B); |
e8ed857c KH |
621 | |
622 | /* Unprotect registers */ | |
10172ed6 | 623 | vga_mm_wseq(par->io_virt, NewMode1, 0x80); |
13b0de49 KH |
624 | if (!is_oldprotect(par->chip_id)) |
625 | vga_mm_wseq(par->io_virt, Protection, 0x92); | |
e8ed857c KH |
626 | |
627 | /* Disable MMIO */ | |
306fa6f6 KH |
628 | t_outb(par, PCIReg, 0x3D4); |
629 | t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); | |
1da177e4 LT |
630 | } |
631 | ||
5cf13845 | 632 | static inline void crtc_unlock(struct tridentfb_par *par) |
306fa6f6 | 633 | { |
10172ed6 KH |
634 | write3X4(par, VGA_CRTC_V_SYNC_END, |
635 | read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); | |
306fa6f6 | 636 | } |
1da177e4 LT |
637 | |
638 | /* Return flat panel's maximum x resolution */ | |
306fa6f6 | 639 | static int __devinit get_nativex(struct tridentfb_par *par) |
1da177e4 | 640 | { |
245a2c2c | 641 | int x, y, tmp; |
1da177e4 LT |
642 | |
643 | if (nativex) | |
644 | return nativex; | |
645 | ||
306fa6f6 | 646 | tmp = (read3CE(par, VertStretch) >> 4) & 3; |
1da177e4 LT |
647 | |
648 | switch (tmp) { | |
245a2c2c KH |
649 | case 0: |
650 | x = 1280; y = 1024; | |
651 | break; | |
652 | case 2: | |
653 | x = 1024; y = 768; | |
654 | break; | |
655 | case 3: | |
656 | x = 800; y = 600; | |
657 | break; | |
658 | case 4: | |
659 | x = 1400; y = 1050; | |
660 | break; | |
661 | case 1: | |
662 | default: | |
663 | x = 640; y = 480; | |
664 | break; | |
1da177e4 LT |
665 | } |
666 | ||
667 | output("%dx%d flat panel found\n", x, y); | |
668 | return x; | |
669 | } | |
670 | ||
671 | /* Set pitch */ | |
5cf13845 | 672 | static inline void set_lwidth(struct tridentfb_par *par, int width) |
1da177e4 | 673 | { |
10172ed6 | 674 | write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); |
306fa6f6 KH |
675 | write3X4(par, AddColReg, |
676 | (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); | |
1da177e4 LT |
677 | } |
678 | ||
679 | /* For resolutions smaller than FP resolution stretch */ | |
306fa6f6 | 680 | static void screen_stretch(struct tridentfb_par *par) |
1da177e4 | 681 | { |
122e8ad3 | 682 | if (par->chip_id != CYBERBLADEXPAi1) |
306fa6f6 | 683 | write3CE(par, BiosReg, 0); |
245a2c2c | 684 | else |
306fa6f6 KH |
685 | write3CE(par, BiosReg, 8); |
686 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); | |
687 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); | |
1da177e4 LT |
688 | } |
689 | ||
690 | /* For resolutions smaller than FP resolution center */ | |
5cf13845 | 691 | static inline void screen_center(struct tridentfb_par *par) |
1da177e4 | 692 | { |
306fa6f6 KH |
693 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); |
694 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); | |
1da177e4 LT |
695 | } |
696 | ||
697 | /* Address of first shown pixel in display memory */ | |
306fa6f6 | 698 | static void set_screen_start(struct tridentfb_par *par, int base) |
1da177e4 | 699 | { |
306fa6f6 | 700 | u8 tmp; |
10172ed6 KH |
701 | write3X4(par, VGA_CRTC_START_LO, base & 0xFF); |
702 | write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); | |
306fa6f6 KH |
703 | tmp = read3X4(par, CRTCModuleTest) & 0xDF; |
704 | write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); | |
705 | tmp = read3X4(par, CRTHiOrd) & 0xF8; | |
706 | write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); | |
1da177e4 LT |
707 | } |
708 | ||
1da177e4 | 709 | /* Set dotclock frequency */ |
306fa6f6 | 710 | static void set_vclk(struct tridentfb_par *par, unsigned long freq) |
1da177e4 | 711 | { |
245a2c2c | 712 | int m, n, k; |
6bdf1035 KH |
713 | unsigned long fi, d, di; |
714 | unsigned char best_m = 0, best_n = 0, best_k = 0; | |
715 | unsigned char hi, lo; | |
6280fd4f | 716 | unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1; |
1da177e4 | 717 | |
3f275ea3 | 718 | d = 20000; |
6280fd4f KH |
719 | for (k = shift; k >= 0; k--) |
720 | for (m = 1; m < 32; m++) { | |
721 | n = ((m + 2) << shift) - 8; | |
34dec243 | 722 | for (n = (n < 0 ? 0 : n); n < 122; n++) { |
3f275ea3 | 723 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; |
34dec243 | 724 | di = abs(fi - freq); |
6280fd4f | 725 | if (di < d || (di == d && k == best_k)) { |
245a2c2c | 726 | d = di; |
6bdf1035 KH |
727 | best_n = n; |
728 | best_m = m; | |
729 | best_k = k; | |
245a2c2c | 730 | } |
3f275ea3 KH |
731 | if (fi > freq) |
732 | break; | |
245a2c2c | 733 | } |
34dec243 | 734 | } |
6bdf1035 KH |
735 | |
736 | if (is_oldclock(par->chip_id)) { | |
737 | lo = best_n | (best_m << 7); | |
738 | hi = (best_m >> 1) | (best_k << 4); | |
739 | } else { | |
740 | lo = best_n; | |
741 | hi = best_m | (best_k << 6); | |
742 | } | |
743 | ||
122e8ad3 | 744 | if (is3Dchip(par->chip_id)) { |
10172ed6 KH |
745 | vga_mm_wseq(par->io_virt, ClockHigh, hi); |
746 | vga_mm_wseq(par->io_virt, ClockLow, lo); | |
1da177e4 | 747 | } else { |
c1724fec KH |
748 | t_outb(par, lo, 0x43C8); |
749 | t_outb(par, hi, 0x43C9); | |
1da177e4 | 750 | } |
245a2c2c | 751 | debug("VCLK = %X %X\n", hi, lo); |
1da177e4 LT |
752 | } |
753 | ||
754 | /* Set number of lines for flat panels*/ | |
306fa6f6 | 755 | static void set_number_of_lines(struct tridentfb_par *par, int lines) |
1da177e4 | 756 | { |
306fa6f6 | 757 | int tmp = read3CE(par, CyberEnhance) & 0x8F; |
1da177e4 LT |
758 | if (lines > 1024) |
759 | tmp |= 0x50; | |
760 | else if (lines > 768) | |
761 | tmp |= 0x30; | |
762 | else if (lines > 600) | |
763 | tmp |= 0x20; | |
764 | else if (lines > 480) | |
765 | tmp |= 0x10; | |
306fa6f6 | 766 | write3CE(par, CyberEnhance, tmp); |
1da177e4 LT |
767 | } |
768 | ||
769 | /* | |
770 | * If we see that FP is active we assume we have one. | |
6eed8e1e | 771 | * Otherwise we have a CRT display. User can override. |
1da177e4 | 772 | */ |
6eed8e1e | 773 | static int __devinit is_flatpanel(struct tridentfb_par *par) |
1da177e4 LT |
774 | { |
775 | if (fp) | |
6eed8e1e | 776 | return 1; |
122e8ad3 | 777 | if (crt || !iscyber(par->chip_id)) |
6eed8e1e KH |
778 | return 0; |
779 | return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; | |
1da177e4 LT |
780 | } |
781 | ||
782 | /* Try detecting the video memory size */ | |
306fa6f6 | 783 | static unsigned int __devinit get_memsize(struct tridentfb_par *par) |
1da177e4 LT |
784 | { |
785 | unsigned char tmp, tmp2; | |
786 | unsigned int k; | |
787 | ||
788 | /* If memory size provided by user */ | |
789 | if (memsize) | |
790 | k = memsize * Kb; | |
791 | else | |
122e8ad3 | 792 | switch (par->chip_id) { |
245a2c2c KH |
793 | case CYBER9525DVD: |
794 | k = 2560 * Kb; | |
795 | break; | |
1da177e4 | 796 | default: |
306fa6f6 | 797 | tmp = read3X4(par, SPR) & 0x0F; |
1da177e4 LT |
798 | switch (tmp) { |
799 | ||
245a2c2c | 800 | case 0x01: |
b614ce8b | 801 | k = 512 * Kb; |
245a2c2c KH |
802 | break; |
803 | case 0x02: | |
804 | k = 6 * Mb; /* XP */ | |
805 | break; | |
806 | case 0x03: | |
807 | k = 1 * Mb; | |
808 | break; | |
809 | case 0x04: | |
810 | k = 8 * Mb; | |
811 | break; | |
812 | case 0x06: | |
813 | k = 10 * Mb; /* XP */ | |
814 | break; | |
815 | case 0x07: | |
816 | k = 2 * Mb; | |
817 | break; | |
818 | case 0x08: | |
819 | k = 12 * Mb; /* XP */ | |
820 | break; | |
821 | case 0x0A: | |
822 | k = 14 * Mb; /* XP */ | |
823 | break; | |
824 | case 0x0C: | |
825 | k = 16 * Mb; /* XP */ | |
826 | break; | |
827 | case 0x0E: /* XP */ | |
828 | ||
10172ed6 | 829 | tmp2 = vga_mm_rseq(par->io_virt, 0xC1); |
245a2c2c KH |
830 | switch (tmp2) { |
831 | case 0x00: | |
832 | k = 20 * Mb; | |
833 | break; | |
834 | case 0x01: | |
835 | k = 24 * Mb; | |
836 | break; | |
837 | case 0x10: | |
838 | k = 28 * Mb; | |
839 | break; | |
840 | case 0x11: | |
841 | k = 32 * Mb; | |
842 | break; | |
843 | default: | |
844 | k = 1 * Mb; | |
845 | break; | |
846 | } | |
847 | break; | |
848 | ||
849 | case 0x0F: | |
850 | k = 4 * Mb; | |
851 | break; | |
852 | default: | |
853 | k = 1 * Mb; | |
1da177e4 | 854 | break; |
1da177e4 | 855 | } |
245a2c2c | 856 | } |
1da177e4 LT |
857 | |
858 | k -= memdiff * Kb; | |
245a2c2c | 859 | output("framebuffer size = %d Kb\n", k / Kb); |
1da177e4 LT |
860 | return k; |
861 | } | |
862 | ||
863 | /* See if we can handle the video mode described in var */ | |
245a2c2c KH |
864 | static int tridentfb_check_var(struct fb_var_screeninfo *var, |
865 | struct fb_info *info) | |
1da177e4 | 866 | { |
6eed8e1e | 867 | struct tridentfb_par *par = info->par; |
1da177e4 | 868 | int bpp = var->bits_per_pixel; |
bcac2d5f | 869 | int line_length; |
74a933fe | 870 | int ramdac = 230000; /* 230MHz for most 3D chips */ |
1da177e4 LT |
871 | debug("enter\n"); |
872 | ||
873 | /* check color depth */ | |
245a2c2c | 874 | if (bpp == 24) |
1da177e4 | 875 | bpp = var->bits_per_pixel = 32; |
49b1f4b4 KH |
876 | if (bpp != 8 && bpp != 16 && bpp != 32) |
877 | return -EINVAL; | |
54f019e5 KH |
878 | if (par->chip_id == TGUI9440 && bpp == 32) |
879 | return -EINVAL; | |
245a2c2c | 880 | /* check whether resolution fits on panel and in memory */ |
6eed8e1e | 881 | if (par->flatpanel && nativex && var->xres > nativex) |
1da177e4 | 882 | return -EINVAL; |
74a933fe KH |
883 | /* various resolution checks */ |
884 | var->xres = (var->xres + 7) & ~0x7; | |
49b1f4b4 | 885 | if (var->xres > var->xres_virtual) |
74a933fe | 886 | var->xres_virtual = var->xres; |
49b1f4b4 KH |
887 | if (var->yres > var->yres_virtual) |
888 | var->yres_virtual = var->yres; | |
889 | if (var->xres_virtual > 4095 || var->yres > 2048) | |
890 | return -EINVAL; | |
891 | /* prevent from position overflow for acceleration */ | |
892 | if (var->yres_virtual > 0xffff) | |
893 | return -EINVAL; | |
bcac2d5f | 894 | line_length = var->xres_virtual * bpp / 8; |
01a2d9ed KH |
895 | |
896 | if (!is3Dchip(par->chip_id) && | |
897 | !(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
bcac2d5f KH |
898 | /* acceleration requires line length to be power of 2 */ |
899 | if (line_length <= 512) | |
900 | var->xres_virtual = 512 * 8 / bpp; | |
901 | else if (line_length <= 1024) | |
902 | var->xres_virtual = 1024 * 8 / bpp; | |
903 | else if (line_length <= 2048) | |
904 | var->xres_virtual = 2048 * 8 / bpp; | |
905 | else if (line_length <= 4096) | |
906 | var->xres_virtual = 4096 * 8 / bpp; | |
907 | else if (line_length <= 8192) | |
908 | var->xres_virtual = 8192 * 8 / bpp; | |
49b1f4b4 KH |
909 | else |
910 | return -EINVAL; | |
bcac2d5f KH |
911 | |
912 | line_length = var->xres_virtual * bpp / 8; | |
913 | } | |
01a2d9ed | 914 | |
f330c4b1 KH |
915 | /* datasheet specifies how to set panning only up to 4 MB */ |
916 | if (line_length * (var->yres_virtual - var->yres) > (4 << 20)) | |
917 | var->yres_virtual = ((4 << 20) / line_length) + var->yres; | |
918 | ||
bcac2d5f | 919 | if (line_length * var->yres_virtual > info->fix.smem_len) |
1da177e4 LT |
920 | return -EINVAL; |
921 | ||
922 | switch (bpp) { | |
245a2c2c KH |
923 | case 8: |
924 | var->red.offset = 0; | |
a4af1798 KH |
925 | var->red.length = 8; |
926 | var->green = var->red; | |
927 | var->blue = var->red; | |
245a2c2c KH |
928 | break; |
929 | case 16: | |
930 | var->red.offset = 11; | |
931 | var->green.offset = 5; | |
932 | var->blue.offset = 0; | |
933 | var->red.length = 5; | |
934 | var->green.length = 6; | |
935 | var->blue.length = 5; | |
936 | break; | |
937 | case 32: | |
938 | var->red.offset = 16; | |
939 | var->green.offset = 8; | |
940 | var->blue.offset = 0; | |
941 | var->red.length = 8; | |
942 | var->green.length = 8; | |
943 | var->blue.length = 8; | |
944 | break; | |
945 | default: | |
946 | return -EINVAL; | |
1da177e4 | 947 | } |
74a933fe KH |
948 | |
949 | if (is_xp(par->chip_id)) | |
950 | ramdac = 350000; | |
951 | ||
952 | switch (par->chip_id) { | |
953 | case TGUI9440: | |
54f019e5 | 954 | ramdac = (bpp >= 16) ? 45000 : 90000; |
74a933fe KH |
955 | break; |
956 | case CYBER9320: | |
957 | case TGUI9660: | |
958 | ramdac = 135000; | |
959 | break; | |
960 | case PROVIDIA9685: | |
961 | case CYBER9388: | |
962 | case CYBER9382: | |
963 | case CYBER9385: | |
964 | ramdac = 170000; | |
965 | break; | |
966 | } | |
967 | ||
968 | /* The clock is doubled for 32 bpp */ | |
969 | if (bpp == 32) | |
970 | ramdac /= 2; | |
971 | ||
972 | if (PICOS2KHZ(var->pixclock) > ramdac) | |
973 | return -EINVAL; | |
974 | ||
1da177e4 LT |
975 | debug("exit\n"); |
976 | ||
977 | return 0; | |
978 | ||
979 | } | |
245a2c2c | 980 | |
1da177e4 LT |
981 | /* Pan the display */ |
982 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, | |
245a2c2c | 983 | struct fb_info *info) |
1da177e4 | 984 | { |
306fa6f6 | 985 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
986 | unsigned int offset; |
987 | ||
988 | debug("enter\n"); | |
bcac2d5f | 989 | offset = (var->xoffset + (var->yoffset * var->xres_virtual)) |
245a2c2c | 990 | * var->bits_per_pixel / 32; |
306fa6f6 | 991 | set_screen_start(par, offset); |
1da177e4 LT |
992 | debug("exit\n"); |
993 | return 0; | |
994 | } | |
995 | ||
5cf13845 | 996 | static inline void shadowmode_on(struct tridentfb_par *par) |
306fa6f6 KH |
997 | { |
998 | write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); | |
999 | } | |
1000 | ||
5cf13845 | 1001 | static inline void shadowmode_off(struct tridentfb_par *par) |
306fa6f6 KH |
1002 | { |
1003 | write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); | |
1004 | } | |
1da177e4 LT |
1005 | |
1006 | /* Set the hardware to the requested video mode */ | |
1007 | static int tridentfb_set_par(struct fb_info *info) | |
1008 | { | |
5cf13845 | 1009 | struct tridentfb_par *par = info->par; |
245a2c2c KH |
1010 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; |
1011 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; | |
1012 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 LT |
1013 | int bpp = var->bits_per_pixel; |
1014 | unsigned char tmp; | |
3f275ea3 KH |
1015 | unsigned long vclk; |
1016 | ||
1da177e4 | 1017 | debug("enter\n"); |
245a2c2c | 1018 | hdispend = var->xres / 8 - 1; |
34dec243 KH |
1019 | hsyncstart = (var->xres + var->right_margin) / 8; |
1020 | hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8; | |
7f762d23 KH |
1021 | htotal = (var->xres + var->left_margin + var->right_margin + |
1022 | var->hsync_len) / 8 - 5; | |
0e73a47f | 1023 | hblankstart = hdispend + 1; |
7f762d23 | 1024 | hblankend = htotal + 3; |
1da177e4 | 1025 | |
1da177e4 LT |
1026 | vdispend = var->yres - 1; |
1027 | vsyncstart = var->yres + var->lower_margin; | |
7f762d23 KH |
1028 | vsyncend = vsyncstart + var->vsync_len; |
1029 | vtotal = var->upper_margin + vsyncend - 2; | |
0e73a47f | 1030 | vblankstart = vdispend + 1; |
7f762d23 | 1031 | vblankend = vtotal; |
1da177e4 | 1032 | |
34dec243 KH |
1033 | if (info->var.vmode & FB_VMODE_INTERLACED) { |
1034 | vtotal /= 2; | |
1035 | vdispend /= 2; | |
1036 | vsyncstart /= 2; | |
1037 | vsyncend /= 2; | |
1038 | vblankstart /= 2; | |
1039 | vblankend /= 2; | |
1040 | } | |
1041 | ||
13b0de49 | 1042 | enable_mmio(par); |
306fa6f6 KH |
1043 | crtc_unlock(par); |
1044 | write3CE(par, CyberControl, 8); | |
34dec243 KH |
1045 | tmp = 0xEB; |
1046 | if (var->sync & FB_SYNC_HOR_HIGH_ACT) | |
1047 | tmp &= ~0x40; | |
1048 | if (var->sync & FB_SYNC_VERT_HIGH_ACT) | |
1049 | tmp &= ~0x80; | |
1da177e4 | 1050 | |
6eed8e1e | 1051 | if (par->flatpanel && var->xres < nativex) { |
1da177e4 LT |
1052 | /* |
1053 | * on flat panels with native size larger | |
1054 | * than requested resolution decide whether | |
1055 | * we stretch or center | |
1056 | */ | |
34dec243 | 1057 | t_outb(par, tmp | 0xC0, VGA_MIS_W); |
1da177e4 | 1058 | |
306fa6f6 | 1059 | shadowmode_on(par); |
1da177e4 | 1060 | |
245a2c2c | 1061 | if (center) |
306fa6f6 | 1062 | screen_center(par); |
1da177e4 | 1063 | else if (stretch) |
306fa6f6 | 1064 | screen_stretch(par); |
1da177e4 LT |
1065 | |
1066 | } else { | |
34dec243 | 1067 | t_outb(par, tmp, VGA_MIS_W); |
306fa6f6 | 1068 | write3CE(par, CyberControl, 8); |
1da177e4 LT |
1069 | } |
1070 | ||
1071 | /* vertical timing values */ | |
10172ed6 KH |
1072 | write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); |
1073 | write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); | |
1074 | write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); | |
1075 | write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); | |
1076 | write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); | |
7f762d23 | 1077 | write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); |
1da177e4 LT |
1078 | |
1079 | /* horizontal timing values */ | |
10172ed6 KH |
1080 | write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); |
1081 | write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); | |
1082 | write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); | |
1083 | write3X4(par, VGA_CRTC_H_SYNC_END, | |
306fa6f6 | 1084 | (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); |
10172ed6 | 1085 | write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); |
7f762d23 | 1086 | write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); |
1da177e4 LT |
1087 | |
1088 | /* higher bits of vertical timing values */ | |
1089 | tmp = 0x10; | |
1090 | if (vtotal & 0x100) tmp |= 0x01; | |
1091 | if (vdispend & 0x100) tmp |= 0x02; | |
1092 | if (vsyncstart & 0x100) tmp |= 0x04; | |
1093 | if (vblankstart & 0x100) tmp |= 0x08; | |
1094 | ||
1095 | if (vtotal & 0x200) tmp |= 0x20; | |
1096 | if (vdispend & 0x200) tmp |= 0x40; | |
1097 | if (vsyncstart & 0x200) tmp |= 0x80; | |
10172ed6 | 1098 | write3X4(par, VGA_CRTC_OVERFLOW, tmp); |
1da177e4 | 1099 | |
7f762d23 KH |
1100 | tmp = read3X4(par, CRTHiOrd) & 0x07; |
1101 | tmp |= 0x08; /* line compare bit 10 */ | |
1da177e4 LT |
1102 | if (vtotal & 0x400) tmp |= 0x80; |
1103 | if (vblankstart & 0x400) tmp |= 0x40; | |
1104 | if (vsyncstart & 0x400) tmp |= 0x20; | |
1105 | if (vdispend & 0x400) tmp |= 0x10; | |
306fa6f6 | 1106 | write3X4(par, CRTHiOrd, tmp); |
1da177e4 | 1107 | |
7f762d23 KH |
1108 | tmp = (htotal >> 8) & 0x01; |
1109 | tmp |= (hdispend >> 7) & 0x02; | |
1110 | tmp |= (hsyncstart >> 5) & 0x08; | |
1111 | tmp |= (hblankstart >> 4) & 0x10; | |
306fa6f6 | 1112 | write3X4(par, HorizOverflow, tmp); |
245a2c2c | 1113 | |
1da177e4 LT |
1114 | tmp = 0x40; |
1115 | if (vblankstart & 0x200) tmp |= 0x20; | |
245a2c2c | 1116 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ |
10172ed6 | 1117 | write3X4(par, VGA_CRTC_MAX_SCAN, tmp); |
1da177e4 | 1118 | |
10172ed6 KH |
1119 | write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); |
1120 | write3X4(par, VGA_CRTC_PRESET_ROW, 0); | |
1121 | write3X4(par, VGA_CRTC_MODE, 0xC3); | |
1da177e4 | 1122 | |
306fa6f6 | 1123 | write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ |
1da177e4 | 1124 | |
245a2c2c | 1125 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; |
306fa6f6 KH |
1126 | /* enable access extended memory */ |
1127 | write3X4(par, CRTCModuleTest, tmp); | |
34dec243 KH |
1128 | tmp = read3CE(par, MiscIntContReg) & ~0x4; |
1129 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
1130 | tmp |= 0x4; | |
1131 | write3CE(par, MiscIntContReg, tmp); | |
1da177e4 | 1132 | |
306fa6f6 KH |
1133 | /* enable GE for text acceleration */ |
1134 | write3X4(par, GraphEngReg, 0x80); | |
1da177e4 | 1135 | |
1da177e4 | 1136 | switch (bpp) { |
245a2c2c KH |
1137 | case 8: |
1138 | tmp = 0x00; | |
1139 | break; | |
1140 | case 16: | |
1141 | tmp = 0x05; | |
1142 | break; | |
1143 | case 24: | |
1144 | tmp = 0x29; | |
1145 | break; | |
1146 | case 32: | |
1147 | tmp = 0x09; | |
1148 | break; | |
1da177e4 LT |
1149 | } |
1150 | ||
306fa6f6 | 1151 | write3X4(par, PixelBusReg, tmp); |
1da177e4 | 1152 | |
0e73a47f KH |
1153 | tmp = read3X4(par, DRAMControl); |
1154 | if (!is_oldprotect(par->chip_id)) | |
1155 | tmp |= 0x10; | |
122e8ad3 | 1156 | if (iscyber(par->chip_id)) |
245a2c2c | 1157 | tmp |= 0x20; |
306fa6f6 | 1158 | write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ |
1da177e4 | 1159 | |
306fa6f6 | 1160 | write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); |
0e73a47f KH |
1161 | if (!is_xp(par->chip_id)) |
1162 | write3X4(par, Performance, read3X4(par, Performance) | 0x10); | |
306fa6f6 | 1163 | /* MMIO & PCI read and write burst enable */ |
13b0de49 | 1164 | if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975) |
a0d92256 | 1165 | write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); |
1da177e4 | 1166 | |
10172ed6 KH |
1167 | vga_mm_wseq(par->io_virt, 0, 3); |
1168 | vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ | |
306fa6f6 | 1169 | /* enable 4 maps because needed in chain4 mode */ |
10172ed6 KH |
1170 | vga_mm_wseq(par->io_virt, 2, 0x0F); |
1171 | vga_mm_wseq(par->io_virt, 3, 0); | |
1172 | vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ | |
1da177e4 | 1173 | |
54f019e5 KH |
1174 | /* convert from picoseconds to kHz */ |
1175 | vclk = PICOS2KHZ(info->var.pixclock); | |
1176 | ||
306fa6f6 | 1177 | /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ |
65e93e03 | 1178 | tmp = read3CE(par, MiscExtFunc) & 0xF0; |
54f019e5 | 1179 | if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { |
65e93e03 | 1180 | tmp |= 8; |
54f019e5 KH |
1181 | vclk *= 2; |
1182 | } | |
1183 | set_vclk(par, vclk); | |
65e93e03 | 1184 | write3CE(par, MiscExtFunc, tmp | 0x12); |
306fa6f6 KH |
1185 | write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ |
1186 | write3CE(par, 0x6, 0x05); /* graphics mode */ | |
1187 | write3CE(par, 0x7, 0x0F); /* planes? */ | |
1da177e4 | 1188 | |
306fa6f6 KH |
1189 | /* graphics mode and support 256 color modes */ |
1190 | writeAttr(par, 0x10, 0x41); | |
1191 | writeAttr(par, 0x12, 0x0F); /* planes */ | |
1192 | writeAttr(par, 0x13, 0); /* horizontal pel panning */ | |
1da177e4 | 1193 | |
245a2c2c KH |
1194 | /* colors */ |
1195 | for (tmp = 0; tmp < 0x10; tmp++) | |
306fa6f6 | 1196 | writeAttr(par, tmp, tmp); |
10172ed6 KH |
1197 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
1198 | t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ | |
1da177e4 LT |
1199 | |
1200 | switch (bpp) { | |
245a2c2c KH |
1201 | case 8: |
1202 | tmp = 0; | |
1203 | break; | |
245a2c2c KH |
1204 | case 16: |
1205 | tmp = 0x30; | |
1206 | break; | |
1207 | case 24: | |
1208 | case 32: | |
1209 | tmp = 0xD0; | |
1210 | break; | |
1da177e4 LT |
1211 | } |
1212 | ||
10172ed6 KH |
1213 | t_inb(par, VGA_PEL_IW); |
1214 | t_inb(par, VGA_PEL_MSK); | |
1215 | t_inb(par, VGA_PEL_MSK); | |
1216 | t_inb(par, VGA_PEL_MSK); | |
1217 | t_inb(par, VGA_PEL_MSK); | |
1218 | t_outb(par, tmp, VGA_PEL_MSK); | |
1219 | t_inb(par, VGA_PEL_IW); | |
1da177e4 | 1220 | |
6eed8e1e | 1221 | if (par->flatpanel) |
306fa6f6 | 1222 | set_number_of_lines(par, info->var.yres); |
bcac2d5f KH |
1223 | info->fix.line_length = info->var.xres_virtual * bpp / 8; |
1224 | set_lwidth(par, info->fix.line_length / 8); | |
01a2d9ed KH |
1225 | |
1226 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1227 | par->init_accel(par, info->var.xres_virtual, bpp); | |
2c86a0c2 | 1228 | |
1da177e4 | 1229 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
245a2c2c | 1230 | info->cmap.len = (bpp == 8) ? 256 : 16; |
1da177e4 LT |
1231 | debug("exit\n"); |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | /* Set one color register */ | |
1236 | static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
245a2c2c KH |
1237 | unsigned blue, unsigned transp, |
1238 | struct fb_info *info) | |
1da177e4 LT |
1239 | { |
1240 | int bpp = info->var.bits_per_pixel; | |
306fa6f6 | 1241 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1242 | |
1243 | if (regno >= info->cmap.len) | |
1244 | return 1; | |
1245 | ||
973d9ab2 | 1246 | if (bpp == 8) { |
10172ed6 KH |
1247 | t_outb(par, 0xFF, VGA_PEL_MSK); |
1248 | t_outb(par, regno, VGA_PEL_IW); | |
1da177e4 | 1249 | |
10172ed6 KH |
1250 | t_outb(par, red >> 10, VGA_PEL_D); |
1251 | t_outb(par, green >> 10, VGA_PEL_D); | |
1252 | t_outb(par, blue >> 10, VGA_PEL_D); | |
1da177e4 | 1253 | |
973d9ab2 AD |
1254 | } else if (regno < 16) { |
1255 | if (bpp == 16) { /* RGB 565 */ | |
1256 | u32 col; | |
1257 | ||
1258 | col = (red & 0xF800) | ((green & 0xFC00) >> 5) | | |
1259 | ((blue & 0xF800) >> 11); | |
1260 | col |= col << 16; | |
1261 | ((u32 *)(info->pseudo_palette))[regno] = col; | |
1262 | } else if (bpp == 32) /* ARGB 8888 */ | |
5cf13845 | 1263 | ((u32 *)info->pseudo_palette)[regno] = |
245a2c2c KH |
1264 | ((transp & 0xFF00) << 16) | |
1265 | ((red & 0xFF00) << 8) | | |
973d9ab2 | 1266 | ((green & 0xFF00)) | |
245a2c2c | 1267 | ((blue & 0xFF00) >> 8); |
973d9ab2 | 1268 | } |
1da177e4 | 1269 | |
1da177e4 LT |
1270 | return 0; |
1271 | } | |
1272 | ||
5cf13845 | 1273 | /* Try blanking the screen. For flat panels it does nothing */ |
1da177e4 LT |
1274 | static int tridentfb_blank(int blank_mode, struct fb_info *info) |
1275 | { | |
245a2c2c | 1276 | unsigned char PMCont, DPMSCont; |
306fa6f6 | 1277 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1278 | |
1279 | debug("enter\n"); | |
6eed8e1e | 1280 | if (par->flatpanel) |
1da177e4 | 1281 | return 0; |
306fa6f6 KH |
1282 | t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ |
1283 | PMCont = t_inb(par, 0x83C6) & 0xFC; | |
1284 | DPMSCont = read3CE(par, PowerStatus) & 0xFC; | |
245a2c2c | 1285 | switch (blank_mode) { |
1da177e4 LT |
1286 | case FB_BLANK_UNBLANK: |
1287 | /* Screen: On, HSync: On, VSync: On */ | |
1288 | case FB_BLANK_NORMAL: | |
1289 | /* Screen: Off, HSync: On, VSync: On */ | |
1290 | PMCont |= 0x03; | |
1291 | DPMSCont |= 0x00; | |
1292 | break; | |
1293 | case FB_BLANK_HSYNC_SUSPEND: | |
1294 | /* Screen: Off, HSync: Off, VSync: On */ | |
1295 | PMCont |= 0x02; | |
1296 | DPMSCont |= 0x01; | |
1297 | break; | |
1298 | case FB_BLANK_VSYNC_SUSPEND: | |
1299 | /* Screen: Off, HSync: On, VSync: Off */ | |
1300 | PMCont |= 0x02; | |
1301 | DPMSCont |= 0x02; | |
1302 | break; | |
1303 | case FB_BLANK_POWERDOWN: | |
1304 | /* Screen: Off, HSync: Off, VSync: Off */ | |
1305 | PMCont |= 0x00; | |
1306 | DPMSCont |= 0x03; | |
1307 | break; | |
245a2c2c | 1308 | } |
1da177e4 | 1309 | |
306fa6f6 KH |
1310 | write3CE(par, PowerStatus, DPMSCont); |
1311 | t_outb(par, 4, 0x83C8); | |
1312 | t_outb(par, PMCont, 0x83C6); | |
1da177e4 LT |
1313 | |
1314 | debug("exit\n"); | |
1315 | ||
1316 | /* let fbcon do a softblank for us */ | |
1317 | return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; | |
1318 | } | |
1319 | ||
245a2c2c KH |
1320 | static struct fb_ops tridentfb_ops = { |
1321 | .owner = THIS_MODULE, | |
1322 | .fb_setcolreg = tridentfb_setcolreg, | |
1323 | .fb_pan_display = tridentfb_pan_display, | |
1324 | .fb_blank = tridentfb_blank, | |
1325 | .fb_check_var = tridentfb_check_var, | |
1326 | .fb_set_par = tridentfb_set_par, | |
1327 | .fb_fillrect = tridentfb_fillrect, | |
1328 | .fb_copyarea = tridentfb_copyarea, | |
0292be4a | 1329 | .fb_imageblit = tridentfb_imageblit, |
49b1f4b4 | 1330 | .fb_sync = tridentfb_sync, |
245a2c2c KH |
1331 | }; |
1332 | ||
e09ed099 KH |
1333 | static int __devinit trident_pci_probe(struct pci_dev *dev, |
1334 | const struct pci_device_id *id) | |
1da177e4 LT |
1335 | { |
1336 | int err; | |
1337 | unsigned char revision; | |
e09ed099 KH |
1338 | struct fb_info *info; |
1339 | struct tridentfb_par *default_par; | |
122e8ad3 KH |
1340 | int chip3D; |
1341 | int chip_id; | |
1da177e4 LT |
1342 | |
1343 | err = pci_enable_device(dev); | |
1344 | if (err) | |
1345 | return err; | |
1346 | ||
e09ed099 KH |
1347 | info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); |
1348 | if (!info) | |
1349 | return -ENOMEM; | |
1350 | default_par = info->par; | |
1351 | ||
1da177e4 LT |
1352 | chip_id = id->device; |
1353 | ||
1354 | /* If PCI id is 0x9660 then further detect chip type */ | |
245a2c2c | 1355 | |
1da177e4 | 1356 | if (chip_id == TGUI9660) { |
10172ed6 | 1357 | revision = vga_io_rseq(RevisionID); |
245a2c2c | 1358 | |
1da177e4 | 1359 | switch (revision) { |
0e73a47f KH |
1360 | case 0x21: |
1361 | chip_id = PROVIDIA9685; | |
1362 | break; | |
245a2c2c KH |
1363 | case 0x22: |
1364 | case 0x23: | |
1365 | chip_id = CYBER9397; | |
1366 | break; | |
1367 | case 0x2A: | |
1368 | chip_id = CYBER9397DVD; | |
1369 | break; | |
1370 | case 0x30: | |
1371 | case 0x33: | |
1372 | case 0x34: | |
1373 | case 0x35: | |
1374 | case 0x38: | |
1375 | case 0x3A: | |
1376 | case 0xB3: | |
1377 | chip_id = CYBER9385; | |
1378 | break; | |
1379 | case 0x40 ... 0x43: | |
1380 | chip_id = CYBER9382; | |
1381 | break; | |
1382 | case 0x4A: | |
1383 | chip_id = CYBER9388; | |
1384 | break; | |
1385 | default: | |
1386 | break; | |
1da177e4 LT |
1387 | } |
1388 | } | |
1389 | ||
1390 | chip3D = is3Dchip(chip_id); | |
1da177e4 LT |
1391 | |
1392 | if (is_xp(chip_id)) { | |
d9cad04b KH |
1393 | default_par->init_accel = xp_init_accel; |
1394 | default_par->wait_engine = xp_wait_engine; | |
1395 | default_par->fill_rect = xp_fill_rect; | |
1396 | default_par->copy_rect = xp_copy_rect; | |
01a2d9ed | 1397 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP; |
245a2c2c | 1398 | } else if (is_blade(chip_id)) { |
d9cad04b KH |
1399 | default_par->init_accel = blade_init_accel; |
1400 | default_par->wait_engine = blade_wait_engine; | |
1401 | default_par->fill_rect = blade_fill_rect; | |
1402 | default_par->copy_rect = blade_copy_rect; | |
0292be4a | 1403 | default_par->image_blit = blade_image_blit; |
01a2d9ed | 1404 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D; |
bcac2d5f | 1405 | } else if (chip3D) { /* 3DImage family left */ |
d9cad04b KH |
1406 | default_par->init_accel = image_init_accel; |
1407 | default_par->wait_engine = image_wait_engine; | |
1408 | default_par->fill_rect = image_fill_rect; | |
1409 | default_par->copy_rect = image_copy_rect; | |
01a2d9ed | 1410 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE; |
bcac2d5f KH |
1411 | } else { /* TGUI 9440/96XX family */ |
1412 | default_par->init_accel = tgui_init_accel; | |
1413 | default_par->wait_engine = xp_wait_engine; | |
1414 | default_par->fill_rect = tgui_fill_rect; | |
1415 | default_par->copy_rect = tgui_copy_rect; | |
01a2d9ed | 1416 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI; |
1da177e4 LT |
1417 | } |
1418 | ||
122e8ad3 KH |
1419 | default_par->chip_id = chip_id; |
1420 | ||
1da177e4 | 1421 | /* setup MMIO region */ |
245a2c2c | 1422 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); |
5cf13845 | 1423 | tridentfb_fix.mmio_len = pci_resource_len(dev, 1); |
1da177e4 | 1424 | |
5cf13845 KH |
1425 | if (!request_mem_region(tridentfb_fix.mmio_start, |
1426 | tridentfb_fix.mmio_len, "tridentfb")) { | |
1da177e4 | 1427 | debug("request_region failed!\n"); |
3876ae8b | 1428 | framebuffer_release(info); |
1da177e4 LT |
1429 | return -1; |
1430 | } | |
1431 | ||
e09ed099 KH |
1432 | default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, |
1433 | tridentfb_fix.mmio_len); | |
1da177e4 | 1434 | |
e09ed099 | 1435 | if (!default_par->io_virt) { |
1da177e4 | 1436 | debug("ioremap failed\n"); |
e8ed857c KH |
1437 | err = -1; |
1438 | goto out_unmap1; | |
1da177e4 LT |
1439 | } |
1440 | ||
13b0de49 | 1441 | enable_mmio(default_par); |
bcac2d5f | 1442 | |
1da177e4 | 1443 | /* setup framebuffer memory */ |
245a2c2c | 1444 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); |
e09ed099 | 1445 | tridentfb_fix.smem_len = get_memsize(default_par); |
245a2c2c | 1446 | |
5cf13845 KH |
1447 | if (!request_mem_region(tridentfb_fix.smem_start, |
1448 | tridentfb_fix.smem_len, "tridentfb")) { | |
1da177e4 | 1449 | debug("request_mem_region failed!\n"); |
e09ed099 | 1450 | disable_mmio(info->par); |
a02f6402 | 1451 | err = -1; |
e8ed857c | 1452 | goto out_unmap1; |
1da177e4 LT |
1453 | } |
1454 | ||
e09ed099 KH |
1455 | info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, |
1456 | tridentfb_fix.smem_len); | |
1da177e4 | 1457 | |
e09ed099 | 1458 | if (!info->screen_base) { |
1da177e4 | 1459 | debug("ioremap failed\n"); |
a02f6402 | 1460 | err = -1; |
e8ed857c | 1461 | goto out_unmap2; |
1da177e4 LT |
1462 | } |
1463 | ||
6eed8e1e | 1464 | default_par->flatpanel = is_flatpanel(default_par); |
1da177e4 | 1465 | |
6eed8e1e | 1466 | if (default_par->flatpanel) |
e09ed099 | 1467 | nativex = get_nativex(default_par); |
1da177e4 | 1468 | |
e09ed099 KH |
1469 | info->fix = tridentfb_fix; |
1470 | info->fbops = &tridentfb_ops; | |
aa0aa8ab | 1471 | info->pseudo_palette = default_par->pseudo_pal; |
1da177e4 | 1472 | |
e09ed099 | 1473 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
01a2d9ed KH |
1474 | if (!noaccel && default_par->init_accel) { |
1475 | info->flags &= ~FBINFO_HWACCEL_DISABLED; | |
1476 | info->flags |= FBINFO_HWACCEL_COPYAREA; | |
1477 | info->flags |= FBINFO_HWACCEL_FILLRECT; | |
1478 | } else | |
1479 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1480 | ||
ddb53d48 KH |
1481 | if (is_blade(chip_id) && chip_id != BLADE3D) |
1482 | info->flags |= FBINFO_READS_FAST; | |
1483 | ||
0292be4a KH |
1484 | info->pixmap.addr = kmalloc(4096, GFP_KERNEL); |
1485 | if (!info->pixmap.addr) { | |
1486 | err = -ENOMEM; | |
1487 | goto out_unmap2; | |
1488 | } | |
1489 | ||
1490 | info->pixmap.size = 4096; | |
1491 | info->pixmap.buf_align = 4; | |
1492 | info->pixmap.scan_align = 1; | |
1493 | info->pixmap.access_align = 32; | |
1494 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
1495 | ||
1496 | if (default_par->image_blit) { | |
1497 | info->flags |= FBINFO_HWACCEL_IMAGEBLIT; | |
1498 | info->pixmap.scan_align = 4; | |
1499 | } | |
1500 | ||
1501 | if (noaccel) { | |
1502 | printk(KERN_DEBUG "disabling acceleration\n"); | |
1503 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1504 | info->pixmap.scan_align = 1; | |
1505 | } | |
1506 | ||
ea8ee55c | 1507 | if (!fb_find_mode(&info->var, info, |
07f41e45 | 1508 | mode_option, NULL, 0, NULL, bpp)) { |
a02f6402 | 1509 | err = -EINVAL; |
e8ed857c | 1510 | goto out_unmap2; |
a02f6402 | 1511 | } |
e09ed099 | 1512 | err = fb_alloc_cmap(&info->cmap, 256, 0); |
e8ed857c KH |
1513 | if (err < 0) |
1514 | goto out_unmap2; | |
1515 | ||
ea8ee55c | 1516 | info->var.activate |= FB_ACTIVATE_NOW; |
e09ed099 KH |
1517 | info->device = &dev->dev; |
1518 | if (register_framebuffer(info) < 0) { | |
5cf13845 | 1519 | printk(KERN_ERR "tridentfb: could not register framebuffer\n"); |
e09ed099 | 1520 | fb_dealloc_cmap(&info->cmap); |
a02f6402 | 1521 | err = -EINVAL; |
e8ed857c | 1522 | goto out_unmap2; |
1da177e4 LT |
1523 | } |
1524 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", | |
ea8ee55c KH |
1525 | info->node, info->fix.id, info->var.xres, |
1526 | info->var.yres, info->var.bits_per_pixel); | |
e09ed099 KH |
1527 | |
1528 | pci_set_drvdata(dev, info); | |
1da177e4 | 1529 | return 0; |
a02f6402 | 1530 | |
e8ed857c | 1531 | out_unmap2: |
0292be4a | 1532 | kfree(info->pixmap.addr); |
e09ed099 KH |
1533 | if (info->screen_base) |
1534 | iounmap(info->screen_base); | |
e8ed857c | 1535 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e09ed099 | 1536 | disable_mmio(info->par); |
e8ed857c | 1537 | out_unmap1: |
e09ed099 KH |
1538 | if (default_par->io_virt) |
1539 | iounmap(default_par->io_virt); | |
e8ed857c | 1540 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 | 1541 | framebuffer_release(info); |
a02f6402 | 1542 | return err; |
1da177e4 LT |
1543 | } |
1544 | ||
245a2c2c | 1545 | static void __devexit trident_pci_remove(struct pci_dev *dev) |
1da177e4 | 1546 | { |
e09ed099 KH |
1547 | struct fb_info *info = pci_get_drvdata(dev); |
1548 | struct tridentfb_par *par = info->par; | |
1549 | ||
1550 | unregister_framebuffer(info); | |
1da177e4 | 1551 | iounmap(par->io_virt); |
e09ed099 | 1552 | iounmap(info->screen_base); |
1da177e4 | 1553 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e8ed857c | 1554 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 | 1555 | pci_set_drvdata(dev, NULL); |
0292be4a | 1556 | kfree(info->pixmap.addr); |
07b39b49 | 1557 | fb_dealloc_cmap(&info->cmap); |
e09ed099 | 1558 | framebuffer_release(info); |
1da177e4 LT |
1559 | } |
1560 | ||
1561 | /* List of boards that we are trying to support */ | |
1562 | static struct pci_device_id trident_devices[] = { | |
245a2c2c KH |
1563 | {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1564 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1565 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1566 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1567 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1568 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1569 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1570 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
a0d92256 | 1571 | {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
245a2c2c KH |
1572 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1573 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1574 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1575 | {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1576 | {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1577 | {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1578 | {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1579 | {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1580 | {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1581 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1582 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1583 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1da177e4 | 1584 | {0,} |
245a2c2c KH |
1585 | }; |
1586 | ||
1587 | MODULE_DEVICE_TABLE(pci, trident_devices); | |
1da177e4 LT |
1588 | |
1589 | static struct pci_driver tridentfb_pci_driver = { | |
245a2c2c KH |
1590 | .name = "tridentfb", |
1591 | .id_table = trident_devices, | |
1592 | .probe = trident_pci_probe, | |
1593 | .remove = __devexit_p(trident_pci_remove) | |
1da177e4 LT |
1594 | }; |
1595 | ||
1596 | /* | |
1597 | * Parse user specified options (`video=trident:') | |
1598 | * example: | |
245a2c2c | 1599 | * video=trident:800x600,bpp=16,noaccel |
1da177e4 LT |
1600 | */ |
1601 | #ifndef MODULE | |
07f41e45 | 1602 | static int __init tridentfb_setup(char *options) |
1da177e4 | 1603 | { |
245a2c2c | 1604 | char *opt; |
1da177e4 LT |
1605 | if (!options || !*options) |
1606 | return 0; | |
245a2c2c KH |
1607 | while ((opt = strsep(&options, ",")) != NULL) { |
1608 | if (!*opt) | |
1609 | continue; | |
1610 | if (!strncmp(opt, "noaccel", 7)) | |
1da177e4 | 1611 | noaccel = 1; |
245a2c2c | 1612 | else if (!strncmp(opt, "fp", 2)) |
6eed8e1e | 1613 | fp = 1; |
245a2c2c | 1614 | else if (!strncmp(opt, "crt", 3)) |
6eed8e1e | 1615 | fp = 0; |
245a2c2c KH |
1616 | else if (!strncmp(opt, "bpp=", 4)) |
1617 | bpp = simple_strtoul(opt + 4, NULL, 0); | |
1618 | else if (!strncmp(opt, "center", 6)) | |
1da177e4 | 1619 | center = 1; |
245a2c2c | 1620 | else if (!strncmp(opt, "stretch", 7)) |
1da177e4 | 1621 | stretch = 1; |
245a2c2c KH |
1622 | else if (!strncmp(opt, "memsize=", 8)) |
1623 | memsize = simple_strtoul(opt + 8, NULL, 0); | |
1624 | else if (!strncmp(opt, "memdiff=", 8)) | |
1625 | memdiff = simple_strtoul(opt + 8, NULL, 0); | |
1626 | else if (!strncmp(opt, "nativex=", 8)) | |
1627 | nativex = simple_strtoul(opt + 8, NULL, 0); | |
1da177e4 | 1628 | else |
07f41e45 | 1629 | mode_option = opt; |
1da177e4 LT |
1630 | } |
1631 | return 0; | |
1632 | } | |
1633 | #endif | |
1634 | ||
1635 | static int __init tridentfb_init(void) | |
1636 | { | |
1637 | #ifndef MODULE | |
1638 | char *option = NULL; | |
1639 | ||
1640 | if (fb_get_options("tridentfb", &option)) | |
1641 | return -ENODEV; | |
1642 | tridentfb_setup(option); | |
1643 | #endif | |
1da177e4 LT |
1644 | return pci_register_driver(&tridentfb_pci_driver); |
1645 | } | |
1646 | ||
1647 | static void __exit tridentfb_exit(void) | |
1648 | { | |
1649 | pci_unregister_driver(&tridentfb_pci_driver); | |
1650 | } | |
1651 | ||
1da177e4 LT |
1652 | module_init(tridentfb_init); |
1653 | module_exit(tridentfb_exit); | |
1654 | ||
1655 | MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); | |
1656 | MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); | |
1657 | MODULE_LICENSE("GPL"); | |
ddb53d48 | 1658 | MODULE_ALIAS("cyblafb"); |
1da177e4 | 1659 |