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pm2fb: memclock setting corrections
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / svgalib.c
CommitLineData
a268422d
OZ		 1/*
2 * Common utility functions for VGA-based graphics cards.
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/fb.h>
17#include <linux/svga.h>
18#include <linux/slab.h>
19#include <asm/types.h>
20#include <asm/io.h>
21
22
23/* Write a CRT register value spread across multiple registers */
24void svga_wcrt_multi(const struct vga_regset *regset, u32 value) {
25
26 u8 regval, bitval, bitnum;
27
28 while (regset->regnum != VGA_REGSET_END_VAL) {
29 regval = vga_rcrt(NULL, regset->regnum);
30 bitnum = regset->lowbit;
31 while (bitnum <= regset->highbit) {
32 bitval = 1 << bitnum;
33 regval = regval & ~bitval;
34 if (value & 1) regval = regval | bitval;
35 bitnum ++;
36 value = value >> 1;
37 }
38 vga_wcrt(NULL, regset->regnum, regval);
39 regset ++;
40 }
41}
42
43/* Write a sequencer register value spread across multiple registers */
44void svga_wseq_multi(const struct vga_regset *regset, u32 value) {
45
46 u8 regval, bitval, bitnum;
47
48 while (regset->regnum != VGA_REGSET_END_VAL) {
49 regval = vga_rseq(NULL, regset->regnum);
50 bitnum = regset->lowbit;
51 while (bitnum <= regset->highbit) {
52 bitval = 1 << bitnum;
53 regval = regval & ~bitval;
54 if (value & 1) regval = regval | bitval;
55 bitnum ++;
56 value = value >> 1;
57 }
58 vga_wseq(NULL, regset->regnum, regval);
59 regset ++;
60 }
61}
62
63static unsigned int svga_regset_size(const struct vga_regset *regset)
64{
65 u8 count = 0;
66
67 while (regset->regnum != VGA_REGSET_END_VAL) {
68 count += regset->highbit - regset->lowbit + 1;
69 regset ++;
70 }
71 return 1 << count;
72}
73
74
75/* ------------------------------------------------------------------------- */
76
77
78/* Set graphics controller registers to sane values */
79void svga_set_default_gfx_regs(void)
80{
81 /* All standard GFX registers (GR00 - GR08) */
82 vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00);
83 vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00);
84 vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00);
85 vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00);
86 vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00);
87 vga_wgfx(NULL, VGA_GFX_MODE, 0x00);
88/* vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */
89/* vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */
90 vga_wgfx(NULL, VGA_GFX_MISC, 0x05);
91/* vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */
92 vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F);
93 vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF);
94}
95
96/* Set attribute controller registers to sane values */
97void svga_set_default_atc_regs(void)
98{
99 u8 count;
100
101 vga_r(NULL, 0x3DA);
102 vga_w(NULL, VGA_ATT_W, 0x00);
103
104 /* All standard ATC registers (AR00 - AR14) */
105 for (count = 0; count <= 0xF; count ++)
106 svga_wattr(count, count);
107
108 svga_wattr(VGA_ATC_MODE, 0x01);
109/* svga_wattr(VGA_ATC_MODE, 0x41); */
110 svga_wattr(VGA_ATC_OVERSCAN, 0x00);
111 svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F);
112 svga_wattr(VGA_ATC_PEL, 0x00);
113 svga_wattr(VGA_ATC_COLOR_PAGE, 0x00);
114
115 vga_r(NULL, 0x3DA);
116 vga_w(NULL, VGA_ATT_W, 0x20);
117}
118
119/* Set sequencer registers to sane values */
120void svga_set_default_seq_regs(void)
121{
122 /* Standard sequencer registers (SR01 - SR04), SR00 is not set */
123 vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
124 vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
125 vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00);
126/* vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
127 vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
128}
129
130/* Set CRTC registers to sane values */
131void svga_set_default_crt_regs(void)
132{
133 /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
134 svga_wcrt_mask(0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */
135 vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0);
136 svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F);
137 vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0);
138 vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3);
139}
140
141void svga_set_textmode_vga_regs(void)
142{
143 /* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
144 vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
145 vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03);
146
147 vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
148 vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f);
149 svga_wcrt_mask(VGA_CRTC_MODE, 0x23, 0x7f);
150
151 vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d);
152 vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e);
153 vga_wcrt(NULL, VGA_CRTC_CURSOR_HI, 0x00);
154 vga_wcrt(NULL, VGA_CRTC_CURSOR_LO, 0x00);
155
156 vga_wgfx(NULL, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
157 vga_wgfx(NULL, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
158 vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x00);
159
160 vga_r(NULL, 0x3DA);
161 vga_w(NULL, VGA_ATT_W, 0x00);
162
163 svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */
164 svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */
165
166 vga_r(NULL, 0x3DA);
167 vga_w(NULL, VGA_ATT_W, 0x20);
168}
169
170#if 0
171void svga_dump_var(struct fb_var_screeninfo *var, int node)
172{
173 pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode);
174 pr_debug("fb%d: var.xres : %d\n", node, var->xres);
175 pr_debug("fb%d: var.yres : %d\n", node, var->yres);
176 pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
177 pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual);
178 pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual);
179 pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin);
180 pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin);
181 pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin);
182 pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin);
183 pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len);
184 pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len);
185 pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync);
186 pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock);
187}
188#endif /* 0 */
189
190
191/* ------------------------------------------------------------------------- */
192
193
194void svga_settile(struct fb_info *info, struct fb_tilemap *map)
195{
196 const u8 *font = map->data;
78494dd3 197 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
a268422d
OZ		 198 int i, c;
199
200 if ((map->width != 8) || (map->height != 16) ||
201 (map->depth != 1) || (map->length != 256)) {
202 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
203 info->node, map->width, map->height, map->depth, map->length);
204 return;
205 }
206
207 fb += 2;
208 for (c = 0; c < map->length; c++) {
209 for (i = 0; i < map->height; i++) {
78494dd3
AD		 210 fb_writeb(font[i], fb + i * 4);
211// fb[i * 4] = font[i];
a268422d
OZ		 212 }
213 fb += 128;
214 font += map->height;
215 }
216}
217
218/* Copy area in text (tileblit) mode */
219void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
220{
221 int dx, dy;
222 /* colstride is halved in this function because u16 are used */
223 int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
224 int rowstride = colstride * (info->var.xres_virtual / 8);
78494dd3
AD		 225 u16 __iomem *fb = (u16 __iomem *) info->screen_base;
226 u16 __iomem *src, *dst;
a268422d
OZ		 227
228 if ((area->sy > area->dy) ||
229 ((area->sy == area->dy) && (area->sx > area->dx))) {
230 src = fb + area->sx * colstride + area->sy * rowstride;
231 dst = fb + area->dx * colstride + area->dy * rowstride;
232 } else {
233 src = fb + (area->sx + area->width - 1) * colstride
234 + (area->sy + area->height - 1) * rowstride;
235 dst = fb + (area->dx + area->width - 1) * colstride
236 + (area->dy + area->height - 1) * rowstride;
237
238 colstride = -colstride;
239 rowstride = -rowstride;
240 }
241
242 for (dy = 0; dy < area->height; dy++) {
78494dd3
AD		 243 u16 __iomem *src2 = src;
244 u16 __iomem *dst2 = dst;
a268422d 245 for (dx = 0; dx < area->width; dx++) {
78494dd3
AD		 246 fb_writew(fb_readw(src2), dst2);
247// *dst2 = *src2;
a268422d
OZ		 248 src2 += colstride;
249 dst2 += colstride;
250 }
251 src += rowstride;
252 dst += rowstride;
253 }
254}
255
256/* Fill area in text (tileblit) mode */
257void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
258{
259 int dx, dy;
260 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
261 int rowstride = colstride * (info->var.xres_virtual / 8);
262 int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
78494dd3 263 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
a268422d
OZ		 264 fb += rect->sx * colstride + rect->sy * rowstride;
265
266 for (dy = 0; dy < rect->height; dy++) {
78494dd3 267 u8 __iomem *fb2 = fb;
a268422d 268 for (dx = 0; dx < rect->width; dx++) {
78494dd3
AD		 269 fb_writeb(rect->index, fb2);
270 fb_writeb(attr, fb2 + 1);
a268422d
OZ		 271 fb2 += colstride;
272 }
273 fb += rowstride;
274 }
275}
276
277/* Write text in text (tileblit) mode */
278void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
279{
280 int dx, dy, i;
281 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
282 int rowstride = colstride * (info->var.xres_virtual / 8);
283 int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
78494dd3 284 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
a268422d
OZ		 285 fb += blit->sx * colstride + blit->sy * rowstride;
286
287 i=0;
288 for (dy=0; dy < blit->height; dy ++) {
78494dd3 289 u8 __iomem *fb2 = fb;
a268422d 290 for (dx = 0; dx < blit->width; dx ++) {
78494dd3
AD		 291 fb_writeb(blit->indices[i], fb2);
292 fb_writeb(attr, fb2 + 1);
a268422d
OZ		 293 fb2 += colstride;
294 i ++;
295 if (i == blit->length) return;
296 }
297 fb += rowstride;
298 }
299
300}
301
302/* Set cursor in text (tileblit) mode */
303void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
304{
305 u8 cs = 0x0d;
306 u8 ce = 0x0e;
307 u16 pos = cursor->sx + (info->var.xoffset / 8)
308 + (cursor->sy + (info->var.yoffset / 16))
309 * (info->var.xres_virtual / 8);
310
311 if (! cursor -> mode)
312 return;
313
314 svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */
315
316 if (cursor -> shape == FB_TILE_CURSOR_NONE)
317 return;
318
319 switch (cursor -> shape) {
320 case FB_TILE_CURSOR_UNDERLINE:
321 cs = 0x0d;
322 break;
323 case FB_TILE_CURSOR_LOWER_THIRD:
324 cs = 0x09;
325 break;
326 case FB_TILE_CURSOR_LOWER_HALF:
327 cs = 0x07;
328 break;
329 case FB_TILE_CURSOR_TWO_THIRDS:
330 cs = 0x05;
331 break;
332 case FB_TILE_CURSOR_BLOCK:
333 cs = 0x01;
334 break;
335 }
336
337 /* set cursor position */
338 vga_wcrt(NULL, 0x0E, pos >> 8);
339 vga_wcrt(NULL, 0x0F, pos & 0xFF);
340
341 vga_wcrt(NULL, 0x0B, ce); /* set cursor end */
342 vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */
343}
344
345
346/* ------------------------------------------------------------------------- */
347
348
349/*
350 * Compute PLL settings (M, N, R)
351 * F_VCO = (F_BASE * M) / N
352 * F_OUT = F_VCO / (2^R)
353 */
354
355static inline u32 abs_diff(u32 a, u32 b)
356{
357 return (a > b) ? (a - b) : (b - a);
358}
359
360int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
361{
362 u16 am, an, ar;
363 u32 f_vco, f_current, delta_current, delta_best;
364
365 pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted);
366
367 ar = pll->r_max;
368 f_vco = f_wanted << ar;
369
370 /* overflow check */
371 if ((f_vco >> ar) != f_wanted)
372 return -EINVAL;
373
374 /* It is usually better to have greater VCO clock
375 because of better frequency stability.
376 So first try r_max, then r smaller. */
377 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
378 ar--;
379 f_vco = f_vco >> 1;
380 }
381
382 /* VCO bounds check */
383 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
384 return -EINVAL;
385
386 delta_best = 0xFFFFFFFF;
387 *m = 0;
388 *n = 0;
389 *r = ar;
390
391 am = pll->m_min;
392 an = pll->n_min;
393
394 while ((am <= pll->m_max) && (an <= pll->n_max)) {
395 f_current = (pll->f_base * am) / an;
396 delta_current = abs_diff (f_current, f_vco);
397
398 if (delta_current < delta_best) {
399 delta_best = delta_current;
400 *m = am;
401 *n = an;
402 }
403
404 if (f_current <= f_vco) {
405 am ++;
406 } else {
407 an ++;
408 }
409 }
410
411 f_current = (pll->f_base * *m) / *n;
412 pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current);
413 pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r);
414 return 0;
415}
416
417
418/* ------------------------------------------------------------------------- */
419
420
421/* Check CRT timing values */
422int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
423{
424 u32 value;
425
426 var->xres = (var->xres+7)&~7;
427 var->left_margin = (var->left_margin+7)&~7;
428 var->right_margin = (var->right_margin+7)&~7;
429 var->hsync_len = (var->hsync_len+7)&~7;
430
431 /* Check horizontal total */
432 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
433 if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs))
434 return -EINVAL;
435
436 /* Check horizontal display and blank start */
437 value = var->xres;
438 if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs))
439 return -EINVAL;
440 if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs))
441 return -EINVAL;
442
443 /* Check horizontal sync start */
444 value = var->xres + var->right_margin;
445 if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs))
446 return -EINVAL;
447
448 /* Check horizontal blank end (or length) */
449 value = var->left_margin + var->right_margin + var->hsync_len;
450 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs)))
451 return -EINVAL;
452
453 /* Check horizontal sync end (or length) */
454 value = var->hsync_len;
455 if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs)))
456 return -EINVAL;
457
458 /* Check vertical total */
459 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
460 if ((value - 1) >= svga_regset_size(tm->v_total_regs))
461 return -EINVAL;
462
463 /* Check vertical display and blank start */
464 value = var->yres;
465 if ((value - 1) >= svga_regset_size(tm->v_display_regs))
466 return -EINVAL;
467 if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
468 return -EINVAL;
469
470 /* Check vertical sync start */
471 value = var->yres + var->lower_margin;
472 if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
473 return -EINVAL;
474
475 /* Check vertical blank end (or length) */
476 value = var->upper_margin + var->lower_margin + var->vsync_len;
477 if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs)))
478 return -EINVAL;
479
480 /* Check vertical sync end (or length) */
481 value = var->vsync_len;
482 if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs)))
483 return -EINVAL;
484
485 return 0;
486}
487
488/* Set CRT timing registers */
489void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var,
490 u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
491{
492 u8 regval;
493 u32 value;
494
495 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
496 value = (value * hmul) / hdiv;
497 pr_debug("fb%d: horizontal total : %d\n", node, value);
498 svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5);
499
500 value = var->xres;
501 value = (value * hmul) / hdiv;
502 pr_debug("fb%d: horizontal display : %d\n", node, value);
503 svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1);
504
505 value = var->xres;
506 value = (value * hmul) / hdiv;
507 pr_debug("fb%d: horizontal blank start: %d\n", node, value);
508 svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder);
509
510 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
511 value = (value * hmul) / hdiv;
512 pr_debug("fb%d: horizontal blank end : %d\n", node, value);
513 svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder);
514
515 value = var->xres + var->right_margin;
516 value = (value * hmul) / hdiv;
517 pr_debug("fb%d: horizontal sync start : %d\n", node, value);
518 svga_wcrt_multi(tm->h_sync_start_regs, (value / 8));
519
520 value = var->xres + var->right_margin + var->hsync_len;
521 value = (value * hmul) / hdiv;
522 pr_debug("fb%d: horizontal sync end : %d\n", node, value);
523 svga_wcrt_multi(tm->h_sync_end_regs, (value / 8));
524
525 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
526 value = (value * vmul) / vdiv;
527 pr_debug("fb%d: vertical total : %d\n", node, value);
528 svga_wcrt_multi(tm->v_total_regs, value - 2);
529
530 value = var->yres;
531 value = (value * vmul) / vdiv;
532 pr_debug("fb%d: vertical display : %d\n", node, value);
533 svga_wcrt_multi(tm->v_display_regs, value - 1);
534
535 value = var->yres;
536 value = (value * vmul) / vdiv;
537 pr_debug("fb%d: vertical blank start : %d\n", node, value);
538 svga_wcrt_multi(tm->v_blank_start_regs, value);
539
540 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
541 value = (value * vmul) / vdiv;
542 pr_debug("fb%d: vertical blank end : %d\n", node, value);
543 svga_wcrt_multi(tm->v_blank_end_regs, value - 2);
544
545 value = var->yres + var->lower_margin;
546 value = (value * vmul) / vdiv;
547 pr_debug("fb%d: vertical sync start : %d\n", node, value);
548 svga_wcrt_multi(tm->v_sync_start_regs, value);
549
550 value = var->yres + var->lower_margin + var->vsync_len;
551 value = (value * vmul) / vdiv;
552 pr_debug("fb%d: vertical sync end : %d\n", node, value);
553 svga_wcrt_multi(tm->v_sync_end_regs, value);
554
555 /* Set horizontal and vertical sync pulse polarity in misc register */
556
557 regval = vga_r(NULL, VGA_MIS_R);
558 if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
559 pr_debug("fb%d: positive horizontal sync\n", node);
560 regval = regval & ~0x80;
561 } else {
562 pr_debug("fb%d: negative horizontal sync\n", node);
563 regval = regval | 0x80;
564 }
565 if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
566 pr_debug("fb%d: positive vertical sync\n", node);
567 regval = regval & ~0x40;
568 } else {
569 pr_debug("fb%d: negative vertical sync\n\n", node);
570 regval = regval | 0x40;
571 }
572 vga_w(NULL, VGA_MIS_W, regval);
573}
574
575
576/* ------------------------------------------------------------------------- */
577
578
579int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix)
580{
581 int i = 0;
582
583 while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL)
584 {
585 if ((var->bits_per_pixel == frm->bits_per_pixel) &&
586 (var->red.length <= frm->red.length) &&
587 (var->green.length <= frm->green.length) &&
588 (var->blue.length <= frm->blue.length) &&
589 (var->transp.length <= frm->transp.length) &&
590 (var->nonstd == frm->nonstd)) {
591 var->bits_per_pixel = frm->bits_per_pixel;
592 var->red = frm->red;
593 var->green = frm->green;
594 var->blue = frm->blue;
595 var->transp = frm->transp;
596 var->nonstd = frm->nonstd;
597 if (fix != NULL) {
598 fix->type = frm->type;
599 fix->type_aux = frm->type_aux;
600 fix->visual = frm->visual;
601 fix->xpanstep = frm->xpanstep;
602 }
603 return i;
604 }
605 i++;
606 frm++;
607 }
608 return -EINVAL;
609}
610
611
612EXPORT_SYMBOL(svga_wcrt_multi);
613EXPORT_SYMBOL(svga_wseq_multi);
614
615EXPORT_SYMBOL(svga_set_default_gfx_regs);
616EXPORT_SYMBOL(svga_set_default_atc_regs);
617EXPORT_SYMBOL(svga_set_default_seq_regs);
618EXPORT_SYMBOL(svga_set_default_crt_regs);
619EXPORT_SYMBOL(svga_set_textmode_vga_regs);
620
621EXPORT_SYMBOL(svga_settile);
622EXPORT_SYMBOL(svga_tilecopy);
623EXPORT_SYMBOL(svga_tilefill);
624EXPORT_SYMBOL(svga_tileblit);
625EXPORT_SYMBOL(svga_tilecursor);
626
627EXPORT_SYMBOL(svga_compute_pll);
628EXPORT_SYMBOL(svga_check_timings);
629EXPORT_SYMBOL(svga_set_timings);
630EXPORT_SYMBOL(svga_match_format);
631
632MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>");
633MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
634MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)