[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mobile_lcdcfb.c

/*
 * SuperH Mobile LCDC Framebuffer
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <video/sh_mobile_lcdc.h>

#define PALETTE_NR 16

struct sh_mobile_lcdc_priv;
struct sh_mobile_lcdc_chan {
	struct sh_mobile_lcdc_priv *lcdc;
	unsigned long *reg_offs;
	unsigned long ldmt1r_value;
	unsigned long enabled; /* ME and SE in LDCNT2R */
	struct sh_mobile_lcdc_chan_cfg cfg;
	u32 pseudo_palette[PALETTE_NR];
	struct fb_info info;
	dma_addr_t dma_handle;
};

struct sh_mobile_lcdc_priv {
	void __iomem *base;
#ifdef CONFIG_HAVE_CLK
	struct clk *clk;
#endif
	unsigned long lddckr;
	struct sh_mobile_lcdc_chan ch[2];
};

/* shared registers */
#define _LDDCKR 0x410
#define _LDDCKSTPR 0x414
#define _LDINTR 0x468
#define _LDSR 0x46c
#define _LDCNT1R 0x470
#define _LDCNT2R 0x474
#define _LDDDSR 0x47c
#define _LDDWD0R 0x800
#define _LDDRDR 0x840
#define _LDDWAR 0x900
#define _LDDRAR 0x904

/* per-channel registers */
enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
       LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };

static unsigned long lcdc_offs_mainlcd[] = {
	[LDDCKPAT1R] = 0x400,
	[LDDCKPAT2R] = 0x404,
	[LDMT1R] = 0x418,
	[LDMT2R] = 0x41c,
	[LDMT3R] = 0x420,
	[LDDFR] = 0x424,
	[LDSM1R] = 0x428,
	[LDSA1R] = 0x430,
	[LDMLSR] = 0x438,
	[LDHCNR] = 0x448,
	[LDHSYNR] = 0x44c,
	[LDVLNR] = 0x450,
	[LDVSYNR] = 0x454,
	[LDPMR] = 0x460,
};

static unsigned long lcdc_offs_sublcd[] = {
	[LDDCKPAT1R] = 0x408,
	[LDDCKPAT2R] = 0x40c,
	[LDMT1R] = 0x600,
	[LDMT2R] = 0x604,
	[LDMT3R] = 0x608,
	[LDDFR] = 0x60c,
	[LDSM1R] = 0x610,
	[LDSA1R] = 0x618,
	[LDMLSR] = 0x620,
	[LDHCNR] = 0x624,
	[LDHSYNR] = 0x628,
	[LDVLNR] = 0x62c,
	[LDVSYNR] = 0x630,
	[LDPMR] = 0x63c,
};

#define START_LCDC	0x00000001
#define LCDC_RESET	0x00000100
#define DISPLAY_BEU	0x00000008
#define LCDC_ENABLE	0x00000001

static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
			    int reg_nr, unsigned long data)
{
	iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
}

static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
				    int reg_nr)
{
	return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
}

static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
		       unsigned long reg_offs, unsigned long data)
{
	iowrite32(data, priv->base + reg_offs);
}

static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
			       unsigned long reg_offs)
{
	return ioread32(priv->base + reg_offs);
}

static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
			  unsigned long reg_offs,
			  unsigned long mask, unsigned long until)
{
	while ((lcdc_read(priv, reg_offs) & mask) != until)
		cpu_relax();
}

static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
{
	return chan->cfg.chan == LCDC_CHAN_SUBLCD;
}

static void lcdc_sys_write_index(void *handle, unsigned long data)
{
	struct sh_mobile_lcdc_chan *ch = handle;

	lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
	lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
}

static void lcdc_sys_write_data(void *handle, unsigned long data)
{
	struct sh_mobile_lcdc_chan *ch = handle;

	lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
	lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
}

static unsigned long lcdc_sys_read_data(void *handle)
{
	struct sh_mobile_lcdc_chan *ch = handle;

	lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
	lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
	udelay(1);

	return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
}

struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
	lcdc_sys_write_index,
	lcdc_sys_write_data,
	lcdc_sys_read_data,
};

static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
				      int start)
{
	unsigned long tmp = lcdc_read(priv, _LDCNT2R);
	int k;

	/* start or stop the lcdc */
	if (start)
		lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
	else
		lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);

	/* wait until power is applied/stopped on all channels */
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
		if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
			while (1) {
				tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
				if (start && tmp == 3)
					break;
				if (!start && tmp == 0)
					break;
				cpu_relax();
			}

	if (!start)
		lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
}

static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
{
	struct sh_mobile_lcdc_chan *ch;
	struct fb_videomode *lcd_cfg;
	struct sh_mobile_lcdc_board_cfg	*board_cfg;
	unsigned long tmp;
	int k, m;
	int ret = 0;

	/* reset */
	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
	lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);

	/* enable LCDC channels */
	tmp = lcdc_read(priv, _LDCNT2R);
	tmp |= priv->ch[0].enabled;
	tmp |= priv->ch[1].enabled;
	lcdc_write(priv, _LDCNT2R, tmp);

	/* read data from external memory, avoid using the BEU for now */
	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);

	/* stop the lcdc first */
	sh_mobile_lcdc_start_stop(priv, 0);

	/* configure clocks */
	tmp = priv->lddckr;
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];

		if (!priv->ch[k].enabled)
			continue;

		m = ch->cfg.clock_divider;
		if (!m)
			continue;

		if (m == 1)
			m = 1 << 6;
		tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);

		lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
		lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
	}

	lcdc_write(priv, _LDDCKR, tmp);

	/* start dotclock again */
	lcdc_write(priv, _LDDCKSTPR, 0);
	lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);

	/* interrupts are disabled */
	lcdc_write(priv, _LDINTR, 0);

	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];
		lcd_cfg = &ch->cfg.lcd_cfg;

		if (!ch->enabled)
			continue;

		tmp = ch->ldmt1r_value;
		tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
		tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
		lcdc_write_chan(ch, LDMT1R, tmp);

		/* setup SYS bus */
		lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
		lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);

		/* horizontal configuration */
		tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
		tmp += lcd_cfg->left_margin;
		tmp += lcd_cfg->right_margin;
		tmp /= 8; /* HTCN */
		tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
		lcdc_write_chan(ch, LDHCNR, tmp);

		tmp = lcd_cfg->xres;
		tmp += lcd_cfg->right_margin;
		tmp /= 8; /* HSYNP */
		tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
		lcdc_write_chan(ch, LDHSYNR, tmp);

		/* power supply */
		lcdc_write_chan(ch, LDPMR, 0);

		/* vertical configuration */
		tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
		tmp += lcd_cfg->upper_margin;
		tmp += lcd_cfg->lower_margin; /* VTLN */
		tmp |= lcd_cfg->yres << 16; /* VDLN */
		lcdc_write_chan(ch, LDVLNR, tmp);

		tmp = lcd_cfg->yres;
		tmp += lcd_cfg->lower_margin; /* VSYNP */
		tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
		lcdc_write_chan(ch, LDVSYNR, tmp);

		board_cfg = &ch->cfg.board_cfg;
		if (board_cfg->setup_sys)
			ret = board_cfg->setup_sys(board_cfg->board_data, ch,
						   &sh_mobile_lcdc_sys_bus_ops);
		if (ret)
			return ret;
	}

	/* --- display_lcdc_data() --- */
	lcdc_write(priv, _LDINTR, 0x00000f00);

	/* word and long word swap */
	lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);

	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];

		if (!priv->ch[k].enabled)
			continue;

		/* set bpp format in PKF[4:0] */
		tmp = lcdc_read_chan(ch, LDDFR);
		tmp &= ~(0x0001001f);
		tmp |= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
		lcdc_write_chan(ch, LDDFR, tmp);

		/* point out our frame buffer */
		lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);

		/* set line size */
		lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);

		/* continuous read mode */
		lcdc_write_chan(ch, LDSM1R, 0);
	}

	/* display output */
	lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);

	/* start the lcdc */
	sh_mobile_lcdc_start_stop(priv, 1);

	/* tell the board code to enable the panel */
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];
		board_cfg = &ch->cfg.board_cfg;
		if (board_cfg->display_on)
			board_cfg->display_on(board_cfg->board_data);
	}

	return 0;
}

static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
{
	struct sh_mobile_lcdc_chan *ch;
	struct sh_mobile_lcdc_board_cfg	*board_cfg;
	int k;

	/* tell the board code to disable the panel */
	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
		ch = &priv->ch[k];
		board_cfg = &ch->cfg.board_cfg;
		if (board_cfg->display_off)
			board_cfg->display_off(board_cfg->board_data);
	}

	/* stop the lcdc */
	sh_mobile_lcdc_start_stop(priv, 0);
}

static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
{
	int ifm, miftyp;

	switch (ch->cfg.interface_type) {
	case RGB8: ifm = 0; miftyp = 0; break;
	case RGB9: ifm = 0; miftyp = 4; break;
	case RGB12A: ifm = 0; miftyp = 5; break;
	case RGB12B: ifm = 0; miftyp = 6; break;
	case RGB16: ifm = 0; miftyp = 7; break;
	case RGB18: ifm = 0; miftyp = 10; break;
	case RGB24: ifm = 0; miftyp = 11; break;
	case SYS8A: ifm = 1; miftyp = 0; break;
	case SYS8B: ifm = 1; miftyp = 1; break;
	case SYS8C: ifm = 1; miftyp = 2; break;
	case SYS8D: ifm = 1; miftyp = 3; break;
	case SYS9: ifm = 1; miftyp = 4; break;
	case SYS12: ifm = 1; miftyp = 5; break;
	case SYS16A: ifm = 1; miftyp = 7; break;
	case SYS16B: ifm = 1; miftyp = 8; break;
	case SYS16C: ifm = 1; miftyp = 9; break;
	case SYS18: ifm = 1; miftyp = 10; break;
	case SYS24: ifm = 1; miftyp = 11; break;
	default: goto bad;
	}

	/* SUBLCD only supports SYS interface */
	if (lcdc_chan_is_sublcd(ch)) {
		if (ifm == 0)
			goto bad;
		else
			ifm = 0;
	}

	ch->ldmt1r_value = (ifm << 12) | miftyp;
	return 0;
 bad:
	return -EINVAL;
}

static int sh_mobile_lcdc_setup_clocks(struct device *dev, int clock_source,
				       struct sh_mobile_lcdc_priv *priv)
{
	char *str;
	int icksel;

	switch (clock_source) {
	case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
	case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
	case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
	default:
		return -EINVAL;
	}

	priv->lddckr = icksel << 16;

#ifdef CONFIG_HAVE_CLK
	if (str) {
		priv->clk = clk_get(dev, str);
		if (IS_ERR(priv->clk)) {
			dev_err(dev, "cannot get clock %s\n", str);
			return PTR_ERR(priv->clk);
		}

		clk_enable(priv->clk);
	}
#endif

	return 0;
}

static int sh_mobile_lcdc_setcolreg(u_int regno,
				    u_int red, u_int green, u_int blue,
				    u_int transp, struct fb_info *info)
{
	u32 *palette = info->pseudo_palette;

	if (regno >= PALETTE_NR)
		return -EINVAL;

	/* only FB_VISUAL_TRUECOLOR supported */

	red >>= 16 - info->var.red.length;
	green >>= 16 - info->var.green.length;
	blue >>= 16 - info->var.blue.length;
	transp >>= 16 - info->var.transp.length;

	palette[regno] = (red << info->var.red.offset) |
	  (green << info->var.green.offset) |
	  (blue << info->var.blue.offset) |
	  (transp << info->var.transp.offset);

	return 0;
}

static struct fb_fix_screeninfo sh_mobile_lcdc_fix  = {
	.id =		"SH Mobile LCDC",
	.type =		FB_TYPE_PACKED_PIXELS,
	.visual =	FB_VISUAL_TRUECOLOR,
	.accel =	FB_ACCEL_NONE,
};

static struct fb_ops sh_mobile_lcdc_ops = {
	.fb_setcolreg	= sh_mobile_lcdc_setcolreg,
	.fb_fillrect	= cfb_fillrect,
	.fb_copyarea	= cfb_copyarea,
	.fb_imageblit	= cfb_imageblit,
};

static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
{
	switch (bpp) {
	case 16: /* PKF[4:0] = 00011 - RGB 565 */
		var->red.offset = 11;
		var->red.length = 5;
		var->green.offset = 5;
		var->green.length = 6;
		var->blue.offset = 0;
		var->blue.length = 5;
		var->transp.offset = 0;
		var->transp.length = 0;
		break;

	case 32: /* PKF[4:0] = 00000 - RGB 888
		  * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
		  * this may be because LDDDSR has word swap enabled..
		  */
		var->red.offset = 0;
		var->red.length = 8;
		var->green.offset = 24;
		var->green.length = 8;
		var->blue.offset = 16;
		var->blue.length = 8;
		var->transp.offset = 0;
		var->transp.length = 0;
		break;
	default:
		return -EINVAL;
	}
	var->bits_per_pixel = bpp;
	var->red.msb_right = 0;
	var->green.msb_right = 0;
	var->blue.msb_right = 0;
	var->transp.msb_right = 0;
	return 0;
}

static int sh_mobile_lcdc_remove(struct platform_device *pdev);

static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
{
	struct fb_info *info;
	struct sh_mobile_lcdc_priv *priv;
	struct sh_mobile_lcdc_info *pdata;
	struct sh_mobile_lcdc_chan_cfg *cfg;
	struct resource *res;
	int error;
	void *buf;
	int i, j;

	if (!pdev->dev.platform_data) {
		dev_err(&pdev->dev, "no platform data defined\n");
		error = -EINVAL;
		goto err0;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&pdev->dev, "cannot find IO resource\n");
		error = -ENOENT;
		goto err0;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "cannot allocate device data\n");
		error = -ENOMEM;
		goto err0;
	}

	platform_set_drvdata(pdev, priv);
	pdata = pdev->dev.platform_data;

	j = 0;
	for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
		priv->ch[j].lcdc = priv;
		memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));

		error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
		if (error) {
			dev_err(&pdev->dev, "unsupported interface type\n");
			goto err1;
		}

		switch (pdata->ch[i].chan) {
		case LCDC_CHAN_MAINLCD:
			priv->ch[j].enabled = 1 << 1;
			priv->ch[j].reg_offs = lcdc_offs_mainlcd;
			j++;
			break;
		case LCDC_CHAN_SUBLCD:
			priv->ch[j].enabled = 1 << 2;
			priv->ch[j].reg_offs = lcdc_offs_sublcd;
			j++;
			break;
		}
	}

	if (!j) {
		dev_err(&pdev->dev, "no channels defined\n");
		error = -EINVAL;
		goto err1;
	}

	error = sh_mobile_lcdc_setup_clocks(&pdev->dev,
					    pdata->clock_source, priv);
	if (error) {
		dev_err(&pdev->dev, "unable to setup clocks\n");
		goto err1;
	}

	priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);

	for (i = 0; i < j; i++) {
		info = &priv->ch[i].info;
		cfg = &priv->ch[i].cfg;

		info->fbops = &sh_mobile_lcdc_ops;
		info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
		info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
		info->var.width = cfg->lcd_size_cfg.width;
		info->var.height = cfg->lcd_size_cfg.height;
		info->var.activate = FB_ACTIVATE_NOW;
		error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
		if (error)
			break;

		info->fix = sh_mobile_lcdc_fix;
		info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
		info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;

		buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
					 &priv->ch[i].dma_handle, GFP_KERNEL);
		if (!buf) {
			dev_err(&pdev->dev, "unable to allocate buffer\n");
			error = -ENOMEM;
			break;
		}

		info->pseudo_palette = &priv->ch[i].pseudo_palette;
		info->flags = FBINFO_FLAG_DEFAULT;

		error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
		if (error < 0) {
			dev_err(&pdev->dev, "unable to allocate cmap\n");
			dma_free_coherent(&pdev->dev, info->fix.smem_len,
					  buf, priv->ch[i].dma_handle);
			break;
		}

		memset(buf, 0, info->fix.smem_len);
		info->fix.smem_start = priv->ch[i].dma_handle;
		info->screen_base = buf;
		info->device = &pdev->dev;
	}

	if (error)
		goto err1;

	error = sh_mobile_lcdc_start(priv);
	if (error) {
		dev_err(&pdev->dev, "unable to start hardware\n");
		goto err1;
	}

	for (i = 0; i < j; i++) {
		error = register_framebuffer(&priv->ch[i].info);
		if (error < 0)
			goto err1;
	}

	for (i = 0; i < j; i++) {
		info = &priv->ch[i].info;
		dev_info(info->dev,
			 "registered %s/%s as %dx%d %dbpp.\n",
			 pdev->name,
			 (priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
			 "mainlcd" : "sublcd",
			 (int) priv->ch[i].cfg.lcd_cfg.xres,
			 (int) priv->ch[i].cfg.lcd_cfg.yres,
			 priv->ch[i].cfg.bpp);
	}

	return 0;
 err1:
	sh_mobile_lcdc_remove(pdev);
 err0:
	return error;
}

static int sh_mobile_lcdc_remove(struct platform_device *pdev)
{
	struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
	struct fb_info *info;
	int i;

	for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
		if (priv->ch[i].info.dev)
			unregister_framebuffer(&priv->ch[i].info);

	sh_mobile_lcdc_stop(priv);

	for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
		info = &priv->ch[i].info;

		if (!info->device)
			continue;

		dma_free_coherent(&pdev->dev, info->fix.smem_len,
				  info->screen_base, priv->ch[i].dma_handle);
		fb_dealloc_cmap(&info->cmap);
	}

#ifdef CONFIG_HAVE_CLK
	if (priv->clk) {
		clk_disable(priv->clk);
		clk_put(priv->clk);
	}
#endif

	if (priv->base)
		iounmap(priv->base);

	kfree(priv);
	return 0;
}

static struct platform_driver sh_mobile_lcdc_driver = {
	.driver		= {
		.name		= "sh_mobile_lcdc_fb",
		.owner		= THIS_MODULE,
	},
	.probe		= sh_mobile_lcdc_probe,
	.remove		= sh_mobile_lcdc_remove,
};

static int __init sh_mobile_lcdc_init(void)
{
	return platform_driver_register(&sh_mobile_lcdc_driver);
}

static void __exit sh_mobile_lcdc_exit(void)
{
	platform_driver_unregister(&sh_mobile_lcdc_driver);
}

module_init(sh_mobile_lcdc_init);
module_exit(sh_mobile_lcdc_exit);

MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
cfb4f5d1 MD	1	/*
	2	* SuperH Mobile LCDC Framebuffer
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/delay.h>
	14	#include <linux/mm.h>
	15	#include <linux/fb.h>
	16	#include <linux/clk.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/dma-mapping.h>
225c9a8d	19	#include <video/sh_mobile_lcdc.h>
cfb4f5d1 MD	20
	21	#define PALETTE_NR 16
	22
	23	struct sh_mobile_lcdc_priv;
	24	struct sh_mobile_lcdc_chan {
	25	struct sh_mobile_lcdc_priv *lcdc;
	26	unsigned long *reg_offs;
	27	unsigned long ldmt1r_value;
	28	unsigned long enabled; /* ME and SE in LDCNT2R */
	29	struct sh_mobile_lcdc_chan_cfg cfg;
	30	u32 pseudo_palette[PALETTE_NR];
	31	struct fb_info info;
	32	dma_addr_t dma_handle;
	33	};
	34
	35	struct sh_mobile_lcdc_priv {
	36	void __iomem *base;
225c9a8d	37	#ifdef CONFIG_HAVE_CLK
cfb4f5d1	38	struct clk *clk;
225c9a8d	39	#endif
cfb4f5d1 MD	40	unsigned long lddckr;
	41	struct sh_mobile_lcdc_chan ch[2];
	42	};
	43
	44	/* shared registers */
	45	#define _LDDCKR 0x410
	46	#define _LDDCKSTPR 0x414
	47	#define _LDINTR 0x468
	48	#define _LDSR 0x46c
	49	#define _LDCNT1R 0x470
	50	#define _LDCNT2R 0x474
	51	#define _LDDDSR 0x47c
	52	#define _LDDWD0R 0x800
	53	#define _LDDRDR 0x840
	54	#define _LDDWAR 0x900
	55	#define _LDDRAR 0x904
	56
	57	/* per-channel registers */
	58	enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
	59	LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
	60
	61	static unsigned long lcdc_offs_mainlcd[] = {
	62	[LDDCKPAT1R] = 0x400,
	63	[LDDCKPAT2R] = 0x404,
	64	[LDMT1R] = 0x418,
	65	[LDMT2R] = 0x41c,
	66	[LDMT3R] = 0x420,
	67	[LDDFR] = 0x424,
	68	[LDSM1R] = 0x428,
	69	[LDSA1R] = 0x430,
	70	[LDMLSR] = 0x438,
	71	[LDHCNR] = 0x448,
	72	[LDHSYNR] = 0x44c,
	73	[LDVLNR] = 0x450,
	74	[LDVSYNR] = 0x454,
	75	[LDPMR] = 0x460,
	76	};
	77
	78	static unsigned long lcdc_offs_sublcd[] = {
	79	[LDDCKPAT1R] = 0x408,
	80	[LDDCKPAT2R] = 0x40c,
	81	[LDMT1R] = 0x600,
	82	[LDMT2R] = 0x604,
	83	[LDMT3R] = 0x608,
	84	[LDDFR] = 0x60c,
	85	[LDSM1R] = 0x610,
	86	[LDSA1R] = 0x618,
	87	[LDMLSR] = 0x620,
	88	[LDHCNR] = 0x624,
	89	[LDHSYNR] = 0x628,
	90	[LDVLNR] = 0x62c,
	91	[LDVSYNR] = 0x630,
	92	[LDPMR] = 0x63c,
	93	};
	94
	95	#define START_LCDC 0x00000001
	96	#define LCDC_RESET 0x00000100
	97	#define DISPLAY_BEU 0x00000008
	98	#define LCDC_ENABLE 0x00000001
	99
	100	static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
	101	int reg_nr, unsigned long data)
	102	{
	103	iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
104	}
105
106	static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
107	int reg_nr)
108	{
109	return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
110	}
111
112	static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
113	unsigned long reg_offs, unsigned long data)
114	{
115	iowrite32(data, priv->base + reg_offs);
116	}
117
118	static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
119	unsigned long reg_offs)
120	{
121	return ioread32(priv->base + reg_offs);
122	}
123
124	static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
125	unsigned long reg_offs,
126	unsigned long mask, unsigned long until)
127	{
128	while ((lcdc_read(priv, reg_offs) & mask) != until)
129	cpu_relax();
130	}
131
132	static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
133	{
134	return chan->cfg.chan == LCDC_CHAN_SUBLCD;
135	}
136
137	static void lcdc_sys_write_index(void *handle, unsigned long data)
138	{
139	struct sh_mobile_lcdc_chan *ch = handle;
140
141	lcdc_write(ch->lcdc, _LDDWD0R, data \| 0x10000000);
142	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
143	lcdc_write(ch->lcdc, _LDDWAR, 1 \| (lcdc_chan_is_sublcd(ch) ? 2 : 0));
144	}
145
146	static void lcdc_sys_write_data(void *handle, unsigned long data)
147	{
148	struct sh_mobile_lcdc_chan *ch = handle;
149
150	lcdc_write(ch->lcdc, _LDDWD0R, data \| 0x11000000);
151	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
152	lcdc_write(ch->lcdc, _LDDWAR, 1 \| (lcdc_chan_is_sublcd(ch) ? 2 : 0));
153	}
154
155	static unsigned long lcdc_sys_read_data(void *handle)
156	{
157	struct sh_mobile_lcdc_chan *ch = handle;
158
159	lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
160	lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
161	lcdc_write(ch->lcdc, _LDDRAR, 1 \| (lcdc_chan_is_sublcd(ch) ? 2 : 0));
162	udelay(1);
163
164	return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
165	}
166
167	struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
168	lcdc_sys_write_index,
169	lcdc_sys_write_data,
170	lcdc_sys_read_data,
171	};
172
173	static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
174	int start)
175	{
176	unsigned long tmp = lcdc_read(priv, _LDCNT2R);
177	int k;
178
179	/* start or stop the lcdc */
180	if (start)
181	lcdc_write(priv, _LDCNT2R, tmp \| START_LCDC);
182	else
183	lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
184
185	/* wait until power is applied/stopped on all channels */
186	for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
187	if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
188	while (1) {
189	tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
190	if (start && tmp == 3)
191	break;
192	if (!start && tmp == 0)
193	break;
194	cpu_relax();
195	}
196
197	if (!start)
198	lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
199	}
200
201	static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
202	{
203	struct sh_mobile_lcdc_chan *ch;
204	struct fb_videomode *lcd_cfg;
205	struct sh_mobile_lcdc_board_cfg *board_cfg;
206	unsigned long tmp;
207	int k, m;
208	int ret = 0;
209
210	/* reset */
211	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) \| LCDC_RESET);
212	lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
213
214	/* enable LCDC channels */
215	tmp = lcdc_read(priv, _LDCNT2R);
216	tmp \|= priv->ch[0].enabled;
217	tmp \|= priv->ch[1].enabled;
218	lcdc_write(priv, _LDCNT2R, tmp);
219
220	/* read data from external memory, avoid using the BEU for now */
221	lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
222
223	/* stop the lcdc first */
224	sh_mobile_lcdc_start_stop(priv, 0);
225
226	/* configure clocks */
227	tmp = priv->lddckr;
228	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
229	ch = &priv->ch[k];
230
231	if (!priv->ch[k].enabled)
232	continue;
233
234	m = ch->cfg.clock_divider;
235	if (!m)
236	continue;
237
238	if (m == 1)
239	m = 1 << 6;
240	tmp \|= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
241
242	lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
243	lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
244	}
245
246	lcdc_write(priv, _LDDCKR, tmp);
247
248	/* start dotclock again */
249	lcdc_write(priv, _LDDCKSTPR, 0);
250	lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
251
252	/* interrupts are disabled */
253	lcdc_write(priv, _LDINTR, 0);
254
255	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
256	ch = &priv->ch[k];
257	lcd_cfg = &ch->cfg.lcd_cfg;
258
259	if (!ch->enabled)
260	continue;
261
262	tmp = ch->ldmt1r_value;
263	tmp \|= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
264	tmp \|= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
265	lcdc_write_chan(ch, LDMT1R, tmp);
266
267	/* setup SYS bus */
268	lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
269	lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
270
271	/* horizontal configuration */
272	tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
273	tmp += lcd_cfg->left_margin;
274	tmp += lcd_cfg->right_margin;
275	tmp /= 8; /* HTCN */
276	tmp \|= (lcd_cfg->xres / 8) << 16; /* HDCN */
277	lcdc_write_chan(ch, LDHCNR, tmp);
278
279	tmp = lcd_cfg->xres;
280	tmp += lcd_cfg->right_margin;
281	tmp /= 8; /* HSYNP */
282	tmp \|= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
283	lcdc_write_chan(ch, LDHSYNR, tmp);
284
285	/* power supply */
286	lcdc_write_chan(ch, LDPMR, 0);
287
288	/* vertical configuration */
289	tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
290	tmp += lcd_cfg->upper_margin;
291	tmp += lcd_cfg->lower_margin; /* VTLN */
292	tmp \|= lcd_cfg->yres << 16; /* VDLN */
293	lcdc_write_chan(ch, LDVLNR, tmp);
294
295	tmp = lcd_cfg->yres;
296	tmp += lcd_cfg->lower_margin; /* VSYNP */
297	tmp \|= lcd_cfg->vsync_len << 16; /* VSYNW */
298	lcdc_write_chan(ch, LDVSYNR, tmp);
299
300	board_cfg = &ch->cfg.board_cfg;
301	if (board_cfg->setup_sys)
302	ret = board_cfg->setup_sys(board_cfg->board_data, ch,
303	&sh_mobile_lcdc_sys_bus_ops);
304	if (ret)
305	return ret;
306	}
307
308	/* --- display_lcdc_data() --- */
309	lcdc_write(priv, _LDINTR, 0x00000f00);
310
311	/* word and long word swap */
312	lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) \| 6);
313
314	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
315	ch = &priv->ch[k];
316
317	if (!priv->ch[k].enabled)
318	continue;
319
320	/* set bpp format in PKF[4:0] */
321	tmp = lcdc_read_chan(ch, LDDFR);
322	tmp &= ~(0x0001001f);
323	tmp \|= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
324	lcdc_write_chan(ch, LDDFR, tmp);
325
326	/* point out our frame buffer */
327	lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);
328
329	/* set line size */
330	lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
331
332	/* continuous read mode */
333	lcdc_write_chan(ch, LDSM1R, 0);
334	}
335
336	/* display output */
337	lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
338
339	/* start the lcdc */
340	sh_mobile_lcdc_start_stop(priv, 1);
341
342	/* tell the board code to enable the panel */
343	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
344	ch = &priv->ch[k];
345	board_cfg = &ch->cfg.board_cfg;
346	if (board_cfg->display_on)
347	board_cfg->display_on(board_cfg->board_data);
348	}
349
350	return 0;
351	}
352
353	static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
354	{
355	struct sh_mobile_lcdc_chan *ch;
356	struct sh_mobile_lcdc_board_cfg *board_cfg;
357	int k;
358
359	/* tell the board code to disable the panel */
360	for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
361	ch = &priv->ch[k];
362	board_cfg = &ch->cfg.board_cfg;
363	if (board_cfg->display_off)
364	board_cfg->display_off(board_cfg->board_data);
365	}
366
367	/* stop the lcdc */
368	sh_mobile_lcdc_start_stop(priv, 0);
369	}
370
371	static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
372	{
373	int ifm, miftyp;
374
375	switch (ch->cfg.interface_type) {
376	case RGB8: ifm = 0; miftyp = 0; break;
377	case RGB9: ifm = 0; miftyp = 4; break;
378	case RGB12A: ifm = 0; miftyp = 5; break;
379	case RGB12B: ifm = 0; miftyp = 6; break;
380	case RGB16: ifm = 0; miftyp = 7; break;
381	case RGB18: ifm = 0; miftyp = 10; break;
382	case RGB24: ifm = 0; miftyp = 11; break;
383	case SYS8A: ifm = 1; miftyp = 0; break;
384	case SYS8B: ifm = 1; miftyp = 1; break;
385	case SYS8C: ifm = 1; miftyp = 2; break;
386	case SYS8D: ifm = 1; miftyp = 3; break;
387	case SYS9: ifm = 1; miftyp = 4; break;
388	case SYS12: ifm = 1; miftyp = 5; break;
389	case SYS16A: ifm = 1; miftyp = 7; break;
390	case SYS16B: ifm = 1; miftyp = 8; break;
391	case SYS16C: ifm = 1; miftyp = 9; break;
392	case SYS18: ifm = 1; miftyp = 10; break;
393	case SYS24: ifm = 1; miftyp = 11; break;
394	default: goto bad;
395	}
396
397	/* SUBLCD only supports SYS interface */
398	if (lcdc_chan_is_sublcd(ch)) {
399	if (ifm == 0)
400	goto bad;
401	else
402	ifm = 0;
403	}
404
405	ch->ldmt1r_value = (ifm << 12) \| miftyp;
406	return 0;
407	bad:
408	return -EINVAL;
409	}
410
411	static int sh_mobile_lcdc_setup_clocks(struct device *dev, int clock_source,
412	struct sh_mobile_lcdc_priv *priv)
413	{
414	char *str;
415	int icksel;
416
417	switch (clock_source) {
418	case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
419	case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
420	case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
421	default:
422	return -EINVAL;
423	}
424
425	priv->lddckr = icksel << 16;
426
225c9a8d	427	#ifdef CONFIG_HAVE_CLK
cfb4f5d1 MD	428	if (str) {
	429	priv->clk = clk_get(dev, str);
	430	if (IS_ERR(priv->clk)) {
	431	dev_err(dev, "cannot get clock %s\n", str);
	432	return PTR_ERR(priv->clk);
	433	}
	434
	435	clk_enable(priv->clk);
	436	}
225c9a8d	437	#endif
cfb4f5d1 MD	438
	439	return 0;
	440	}
	441
	442	static int sh_mobile_lcdc_setcolreg(u_int regno,
	443	u_int red, u_int green, u_int blue,
	444	u_int transp, struct fb_info *info)
	445	{
	446	u32 *palette = info->pseudo_palette;
	447
	448	if (regno >= PALETTE_NR)
	449	return -EINVAL;
	450
	451	/* only FB_VISUAL_TRUECOLOR supported */
	452
	453	red >>= 16 - info->var.red.length;
	454	green >>= 16 - info->var.green.length;
	455	blue >>= 16 - info->var.blue.length;
	456	transp >>= 16 - info->var.transp.length;
	457
	458	palette[regno] = (red << info->var.red.offset) \|
	459	(green << info->var.green.offset) \|
	460	(blue << info->var.blue.offset) \|
	461	(transp << info->var.transp.offset);
	462
	463	return 0;
	464	}
	465
	466	static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
	467	.id = "SH Mobile LCDC",
	468	.type = FB_TYPE_PACKED_PIXELS,
	469	.visual = FB_VISUAL_TRUECOLOR,
	470	.accel = FB_ACCEL_NONE,
	471	};
	472
	473	static struct fb_ops sh_mobile_lcdc_ops = {
	474	.fb_setcolreg = sh_mobile_lcdc_setcolreg,
	475	.fb_fillrect = cfb_fillrect,
	476	.fb_copyarea = cfb_copyarea,
	477	.fb_imageblit = cfb_imageblit,
	478	};
	479
	480	static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
	481	{
	482	switch (bpp) {
	483	case 16: /* PKF[4:0] = 00011 - RGB 565 */
	484	var->red.offset = 11;
	485	var->red.length = 5;
	486	var->green.offset = 5;
	487	var->green.length = 6;
	488	var->blue.offset = 0;
	489	var->blue.length = 5;
	490	var->transp.offset = 0;
	491	var->transp.length = 0;
	492	break;
	493
	494	case 32: /* PKF[4:0] = 00000 - RGB 888
	495	* sh7722 pdf says 00RRGGBB but reality is GGBB00RR
	496	* this may be because LDDDSR has word swap enabled..
	497	*/
	498	var->red.offset = 0;
	499	var->red.length = 8;
	500	var->green.offset = 24;
	501	var->green.length = 8;
502	var->blue.offset = 16;
503	var->blue.length = 8;
504	var->transp.offset = 0;
505	var->transp.length = 0;
506	break;
507	default:
508	return -EINVAL;
509	}
510	var->bits_per_pixel = bpp;
511	var->red.msb_right = 0;
512	var->green.msb_right = 0;
513	var->blue.msb_right = 0;
514	var->transp.msb_right = 0;
515	return 0;
516	}
517
518	static int sh_mobile_lcdc_remove(struct platform_device *pdev);
519
520	static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
521	{
522	struct fb_info *info;
523	struct sh_mobile_lcdc_priv *priv;
524	struct sh_mobile_lcdc_info *pdata;
525	struct sh_mobile_lcdc_chan_cfg *cfg;
526	struct resource *res;
527	int error;
528	void *buf;
529	int i, j;
530
531	if (!pdev->dev.platform_data) {
532	dev_err(&pdev->dev, "no platform data defined\n");
533	error = -EINVAL;
534	goto err0;
535	}
536
537	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
538	if (res == NULL) {
539	dev_err(&pdev->dev, "cannot find IO resource\n");
540	error = -ENOENT;
541	goto err0;
542	}
543
544	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
545	if (!priv) {
546	dev_err(&pdev->dev, "cannot allocate device data\n");
547	error = -ENOMEM;
548	goto err0;
549	}
550
551	platform_set_drvdata(pdev, priv);
552	pdata = pdev->dev.platform_data;
553
554	j = 0;
555	for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
556	priv->ch[j].lcdc = priv;
557	memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
558
559	error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
560	if (error) {
561	dev_err(&pdev->dev, "unsupported interface type\n");
562	goto err1;
563	}
564
565	switch (pdata->ch[i].chan) {
566	case LCDC_CHAN_MAINLCD:
567	priv->ch[j].enabled = 1 << 1;
568	priv->ch[j].reg_offs = lcdc_offs_mainlcd;
569	j++;
570	break;
571	case LCDC_CHAN_SUBLCD:
572	priv->ch[j].enabled = 1 << 2;
573	priv->ch[j].reg_offs = lcdc_offs_sublcd;
574	j++;
575	break;
576	}
577	}
578
579	if (!j) {
580	dev_err(&pdev->dev, "no channels defined\n");
581	error = -EINVAL;
582	goto err1;
583	}
584
585	error = sh_mobile_lcdc_setup_clocks(&pdev->dev,
586	pdata->clock_source, priv);
587	if (error) {
588	dev_err(&pdev->dev, "unable to setup clocks\n");
589	goto err1;
590	}
591
cfb4f5d1 MD	592	priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
	593
	594	for (i = 0; i < j; i++) {
	595	info = &priv->ch[i].info;
	596	cfg = &priv->ch[i].cfg;
	597
	598	info->fbops = &sh_mobile_lcdc_ops;
	599	info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
	600	info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
ce9c008c MD	601	info->var.width = cfg->lcd_size_cfg.width;
ce9c008c MD	602	info->var.height = cfg->lcd_size_cfg.height;
cfb4f5d1 MD	603	info->var.activate = FB_ACTIVATE_NOW;
	604	error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
	605	if (error)
	606	break;
	607
	608	info->fix = sh_mobile_lcdc_fix;
	609	info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
	610	info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
	611
	612	buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
	613	&priv->ch[i].dma_handle, GFP_KERNEL);
	614	if (!buf) {
	615	dev_err(&pdev->dev, "unable to allocate buffer\n");
	616	error = -ENOMEM;
	617	break;
	618	}
	619
	620	info->pseudo_palette = &priv->ch[i].pseudo_palette;
	621	info->flags = FBINFO_FLAG_DEFAULT;
	622
	623	error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
	624	if (error < 0) {
	625	dev_err(&pdev->dev, "unable to allocate cmap\n");
	626	dma_free_coherent(&pdev->dev, info->fix.smem_len,
	627	buf, priv->ch[i].dma_handle);
	628	break;
	629	}
	630
	631	memset(buf, 0, info->fix.smem_len);
	632	info->fix.smem_start = priv->ch[i].dma_handle;
	633	info->screen_base = buf;
	634	info->device = &pdev->dev;
	635	}
	636
	637	if (error)
	638	goto err1;
	639
	640	error = sh_mobile_lcdc_start(priv);
	641	if (error) {
	642	dev_err(&pdev->dev, "unable to start hardware\n");
	643	goto err1;
	644	}
	645
	646	for (i = 0; i < j; i++) {
	647	error = register_framebuffer(&priv->ch[i].info);
	648	if (error < 0)
	649	goto err1;
	650	}
	651
	652	for (i = 0; i < j; i++) {
	653	info = &priv->ch[i].info;
	654	dev_info(info->dev,
	655	"registered %s/%s as %dx%d %dbpp.\n",
	656	pdev->name,
	657	(priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
	658	"mainlcd" : "sublcd",
	659	(int) priv->ch[i].cfg.lcd_cfg.xres,
	660	(int) priv->ch[i].cfg.lcd_cfg.yres,
	661	priv->ch[i].cfg.bpp);
	662	}
	663
	664	return 0;
	665	err1:
	666	sh_mobile_lcdc_remove(pdev);
667	err0:
668	return error;
669	}
670
671	static int sh_mobile_lcdc_remove(struct platform_device *pdev)
672	{
673	struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
674	struct fb_info *info;
675	int i;
676
677	for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
678	if (priv->ch[i].info.dev)
679	unregister_framebuffer(&priv->ch[i].info);
680
681	sh_mobile_lcdc_stop(priv);
682
683	for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
684	info = &priv->ch[i].info;
685
686	if (!info->device)
687	continue;
688
689	dma_free_coherent(&pdev->dev, info->fix.smem_len,
690	info->screen_base, priv->ch[i].dma_handle);
691	fb_dealloc_cmap(&info->cmap);
692	}
693
225c9a8d	694	#ifdef CONFIG_HAVE_CLK
cfb4f5d1 MD	695	if (priv->clk) {
	696	clk_disable(priv->clk);
	697	clk_put(priv->clk);
	698	}
225c9a8d	699	#endif
cfb4f5d1 MD	700
	701	if (priv->base)
	702	iounmap(priv->base);
	703
	704	kfree(priv);
	705	return 0;
	706	}
	707
	708	static struct platform_driver sh_mobile_lcdc_driver = {
	709	.driver = {
	710	.name = "sh_mobile_lcdc_fb",
	711	.owner = THIS_MODULE,
	712	},
	713	.probe = sh_mobile_lcdc_probe,
	714	.remove = sh_mobile_lcdc_remove,
	715	};
	716
	717	static int __init sh_mobile_lcdc_init(void)
	718	{
	719	return platform_driver_register(&sh_mobile_lcdc_driver);
	720	}
	721
	722	static void __exit sh_mobile_lcdc_exit(void)
	723	{
	724	platform_driver_unregister(&sh_mobile_lcdc_driver);
	725	}
	726
	727	module_init(sh_mobile_lcdc_init);
	728	module_exit(sh_mobile_lcdc_exit);
	729
	730	MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
	731	MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
	732	MODULE_LICENSE("GPL v2");