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fbdev: sh_mobile_lcdc: Create functions to turn the display on/off
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mobile_hdmi.c
CommitLineData
6011bdea
GL		 1/*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/slab.h>
23#include <linux/types.h>
24#include <linux/workqueue.h>
644a9845 25#include <sound/soc.h>
1d6be338
KM		 26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
6011bdea
GL		 28
29#include <video/sh_mobile_hdmi.h>
30#include <video/sh_mobile_lcdc.h>
31
6de9edd5
GL		 32#include "sh_mobile_lcdcfb.h"
33
6011bdea
GL		 34#define HDMI_SYSTEM_CTRL 0x00 /* System control */
35#define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
36 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
37#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
38#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
39#define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
40 bits 19..16 of Internal CTS */
41#define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
42#define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
43#define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
44#define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
45#define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
46#define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
47#define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
48#define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
49#define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
50#define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
51#define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
52#define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
53#define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
54#define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
55#define HDMI_CATEGORY_CODE 0x13 /* Category code */
56#define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
57#define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
58#define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
59#define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
60
61/* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
62#define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
63
64#define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
65#define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
66#define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
67#define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
68#define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
69#define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
70#define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
71#define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
72#define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
73#define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
74#define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
75#define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
76#define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
77#define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
78#define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
79#define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
80#define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
81#define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
82#define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
83#define HDMI_OUTPUT_OPTION 0x46 /* Output option */
84#define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
85#define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
86#define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
87#define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
88#define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
89#define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
90#define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
91#define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
92#define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
93#define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
94#define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
95#define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
96#define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
97#define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
98#define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
99#define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
100#define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
101#define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
102#define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
103#define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
104#define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
105#define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
106#define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
107#define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
108#define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
109#define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
110#define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
111#define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
112#define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
113#define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
114#define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
115#define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
116#define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
117#define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
118#define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
119#define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
120#define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
121#define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
122#define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
123#define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
124#define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
125#define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
126#define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
127#define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
128#define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
129#define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
130#define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
131#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
132#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
133#define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
134#define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
135#define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
136#define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
137#define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
138#define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
139#define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
140#define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
141#define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
142#define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
143#define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
144#define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
145#define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
146#define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
147#define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
148#define HDMI_SHA0 0xB9 /* sha0 */
149#define HDMI_SHA1 0xBA /* sha1 */
150#define HDMI_SHA2 0xBB /* sha2 */
151#define HDMI_SHA3 0xBC /* sha3 */
152#define HDMI_SHA4 0xBD /* sha4 */
153#define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
154#define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
155#define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
156#define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
157#define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
158#define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
159#define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
160#define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
161#define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
162#define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
163#define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
164#define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
165#define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
166#define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
167#define HDMI_AN_SEED 0xCC /* An seed */
168#define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
169#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
170#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
171#define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
172#define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
173#define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
174#define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
175#define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
176#define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
177#define HDMI_PJ 0xD7 /* Pj */
178#define HDMI_SHA_RD 0xD8 /* sha_rd */
179#define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
180#define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
181#define HDMI_PJ_SAVED 0xDB /* Pj saved */
182#define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
183#define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
184#define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
185#define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
186#define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
187#define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
188#define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
189#define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
190#define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
191#define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
192#define HDMI_AN_7_0 0xE8 /* An[7:0] */
193#define HDMI_AN_15_8 0xE9 /* An [15:8] */
194#define HDMI_AN_23_16 0xEA /* An [23:16] */
195#define HDMI_AN_31_24 0xEB /* An [31:24] */
196#define HDMI_AN_39_32 0xEC /* An [39:32] */
197#define HDMI_AN_47_40 0xED /* An [47:40] */
198#define HDMI_AN_55_48 0xEE /* An [55:48] */
199#define HDMI_AN_63_56 0xEF /* An [63:56] */
200#define HDMI_PRODUCT_ID 0xF0 /* Product ID */
201#define HDMI_REVISION_ID 0xF1 /* Revision ID */
202#define HDMI_TEST_MODE 0xFE /* Test mode */
203
204enum hotplug_state {
205 HDMI_HOTPLUG_DISCONNECTED,
206 HDMI_HOTPLUG_CONNECTED,
207 HDMI_HOTPLUG_EDID_DONE,
208};
209
210struct sh_hdmi {
211 void __iomem *base;
6aa966e6 212 enum hotplug_state hp_state; /* hot-plug status */
0ea2af1c
GL		 213 u8 preprogrammed_vic; /* use a pre-programmed VIC or
214 the external mode */
4232f607
GL		 215 u8 edid_block_addr;
216 u8 edid_segment_nr;
217 u8 edid_blocks;
6011bdea
GL		 218 struct clk *hdmi_clk;
219 struct device *dev;
220 struct fb_info *info;
6de9edd5 221 struct mutex mutex; /* Protect the info pointer */
6011bdea
GL		 222 struct delayed_work edid_work;
223 struct fb_var_screeninfo var;
afe417c0 224 struct fb_monspecs monspec;
eb0778bd 225 struct notifier_block notifier;
6011bdea
GL		 226};
227
228static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
229{
230 iowrite8(data, hdmi->base + reg);
231}
232
233static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
234{
235 return ioread8(hdmi->base + reg);
236}
237
f4363b7d
KM		 238/*
239 * HDMI sound
240 */
1d6be338
KM		 241static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
242 unsigned int reg)
243{
244 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
245
246 return hdmi_read(hdmi, reg);
247}
248
249static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
250 unsigned int reg,
251 unsigned int value)
252{
253 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
254
255 hdmi_write(hdmi, value, reg);
256 return 0;
257}
258
259static struct snd_soc_dai_driver sh_hdmi_dai = {
260 .name = "sh_mobile_hdmi-hifi",
261 .playback = {
262 .stream_name = "Playback",
17731f8d
KM		 263 .channels_min = 2,
264 .channels_max = 8,
265 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
266 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
267 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
268 SNDRV_PCM_RATE_192000,
1d6be338
KM		 269 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
270 },
271};
272
273static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
274{
275 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
276
277 return 0;
278}
279
280static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
281 .probe = sh_hdmi_snd_probe,
282 .read = sh_hdmi_snd_read,
283 .write = sh_hdmi_snd_write,
284};
285
f4363b7d
KM		 286/*
287 * HDMI video
288 */
1d6be338 289
6011bdea 290/* External video parameter settings */
6aa966e6 291static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
6011bdea
GL		 292{
293 struct fb_var_screeninfo *var = &hdmi->var;
294 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
295 u8 sync = 0;
296
297 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
298
299 hdelay = var->hsync_len + var->left_margin;
300 hblank = var->right_margin + hdelay;
301
302 /*
303 * Vertical timing looks a bit different in Figure 18,
304 * but let's try the same first by setting offset = 0
305 */
306 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
307
308 vdelay = var->vsync_len + var->upper_margin;
309 vblank = var->lower_margin + vdelay;
310 voffset = min(var->upper_margin / 2, 6U);
311
312 /*
313 * [3]: VSYNC polarity: Positive
314 * [2]: HSYNC polarity: Positive
315 * [1]: Interlace/Progressive: Progressive
316 * [0]: External video settings enable: used.
317 */
318 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
319 sync |= 4;
320 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
321 sync |= 8;
322
6aa966e6
GL		 323 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
324 htotal, hblank, hdelay, var->hsync_len,
325 vtotal, vblank, vdelay, var->vsync_len, sync);
6011bdea
GL		 326
327 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
328
329 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
330 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
331
332 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
333 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
334
335 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
336 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
337
338 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
339 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
340
341 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
342 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
343
344 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
345
346 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
347
348 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
349
89712699 350 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
0ea2af1c 351 if (!hdmi->preprogrammed_vic)
89712699
GL		 352 hdmi_write(hdmi, sync | 1 | (voffset << 4),
353 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
6011bdea
GL		 354}
355
356/**
357 * sh_hdmi_video_config()
358 */
359static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
360{
361 /*
362 * [7:4]: Audio sampling frequency: 48kHz
363 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
364 * [0]: Internal/External DE select: internal
365 */
366 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
367
368 /*
369 * [7:6]: Video output format: RGB 4:4:4
370 * [5:4]: Input video data width: 8 bit
371 * [3:1]: EAV/SAV location: channel 1
372 * [0]: Video input color space: RGB
373 */
374 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
375
376 /*
377 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
378 * left at 0 by default, this configures 24bpp and sets the Color Depth
379 * (CD) field in the General Control Packet
380 */
381 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
382}
383
384/**
385 * sh_hdmi_audio_config()
386 */
387static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
388{
6d865771
KM		 389 u8 data;
390 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
391
6011bdea
GL		 392 /*
393 * [7:4] L/R data swap control
394 * [3:0] appropriate N[19:16]
395 */
396 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
397 /* appropriate N[15:8] */
398 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
399 /* appropriate N[7:0] */
400 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
401
402 /* [7:4] 48 kHz SPDIF not used */
403 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
404
405 /*
406 * [6:5] set required down sampling rate if required
407 * [4:3] set required audio source
408 */
dec6aa49 409 switch (pdata->flags & HDMI_SND_SRC_MASK) {
6d865771 410 default:
f4363b7d 411 /* fall through */
dec6aa49
KM		 412 case HDMI_SND_SRC_I2S:
413 data = 0x0 << 3;
6d865771 414 break;
dec6aa49
KM		 415 case HDMI_SND_SRC_SPDIF:
416 data = 0x1 << 3;
6d865771 417 break;
dec6aa49
KM		 418 case HDMI_SND_SRC_DSD:
419 data = 0x2 << 3;
6d865771 420 break;
dec6aa49
KM		 421 case HDMI_SND_SRC_HBR:
422 data = 0x3 << 3;
6d865771
KM		 423 break;
424 }
425 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
6011bdea
GL		 426
427 /* [3:0] set sending channel number for channel status */
428 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
429
430 /*
431 * [5:2] set valid I2S source input pin
432 * [1:0] set input I2S source mode
433 */
434 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
435
436 /* [7:4] set valid DSD source input pin */
437 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
438
439 /* [7:0] set appropriate I2S input pin swap settings if required */
440 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
441
442 /*
443 * [7] set validity bit for channel status
444 * [3:0] set original sample frequency for channel status
445 */
446 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
447
448 /*
449 * [7] set value for channel status
450 * [6] set value for channel status
451 * [5] set copyright bit for channel status
452 * [4:2] set additional information for channel status
453 * [1:0] set clock accuracy for channel status
454 */
455 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
456
457 /* [7:0] set category code for channel status */
458 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
459
460 /*
461 * [7:4] set source number for channel status
462 * [3:0] set word length for channel status
463 */
464 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
465
466 /* [7:4] set sample frequency for channel status */
467 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
468}
469
470/**
6e45746c 471 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
6011bdea
GL		 472 */
473static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
474{
0ea2af1c
GL		 475 if (hdmi->var.pixclock < 10000) {
476 /* for 1080p8bit 148MHz */
477 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
478 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
479 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
480 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
481 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
482 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
483 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
484 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
485 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
486 } else if (hdmi->var.pixclock < 30000) {
6e45746c
GL		 487 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
488 /*
489 * [1:0] Speed_A
490 * [3:2] Speed_B
491 * [4] PLLA_Bypass
492 * [6] DRV_TEST_EN
493 * [7] DRV_TEST_IN
494 */
9289c475 495 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
6e45746c
GL		 496 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
497 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
498 /*
499 * [2:0] BGR_I_OFFSET
500 * [6:4] BGR_V_OFFSET
501 */
502 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
503 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
504 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
505 /*
506 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
507 * LPF capacitance, LPF resistance[1]
508 */
509 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
510 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
511 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
512 /*
513 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
514 * LPF capacitance, LPF resistance[1]
515 */
9289c475 516 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
6e45746c
GL		 517 /* DRV_CONFIG, PE_CONFIG */
518 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
519 /*
520 * [2:0] AMON_SEL (4 == LPF voltage)
521 * [4] PLLA_CONFIG[16]
522 * [5] PLLB_CONFIG[16]
523 */
524 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
525 } else {
526 /* for 480p8bit 27MHz */
527 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
528 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
529 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
530 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
531 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
532 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
533 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
534 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
535 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
536 }
6011bdea
GL		 537}
538
539/**
540 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
541 */
542static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
543{
6e45746c
GL		 544 u8 vic;
545
6011bdea
GL		 546 /* AVI InfoFrame */
547 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
548
549 /* Packet Type = 0x82 */
550 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
551
552 /* Version = 0x02 */
553 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
554
555 /* Length = 13 (0x0D) */
556 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
557
558 /* N. A. Checksum */
559 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
560
561 /*
562 * Y = RGB
563 * A0 = No Data
564 * B = Bar Data not valid
565 * S = No Data
566 */
567 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
568
569 /*
6aa966e6
GL		 570 * [7:6] C = Colorimetry: no data
571 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
572 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
6011bdea
GL		 573 */
574 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
575
576 /*
577 * ITC = No Data
578 * EC = xvYCC601
579 * Q = Default (depends on video format)
580 * SC = No Known non_uniform Scaling
581 */
582 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
583
584 /*
0ea2af1c
GL		 585 * VIC should be ignored if external config is used, so, we could just use 0,
586 * but play safe and use a valid value in any case just in case
6011bdea 587 */
0ea2af1c
GL		 588 if (hdmi->preprogrammed_vic)
589 vic = hdmi->preprogrammed_vic;
6e45746c
GL		 590 else
591 vic = 4;
592 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
6011bdea
GL		 593
594 /* PR = No Repetition */
595 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
596
597 /* Line Number of End of Top Bar (lower 8 bits) */
598 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
599
600 /* Line Number of End of Top Bar (upper 8 bits) */
601 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
602
603 /* Line Number of Start of Bottom Bar (lower 8 bits) */
604 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
605
606 /* Line Number of Start of Bottom Bar (upper 8 bits) */
607 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
608
609 /* Pixel Number of End of Left Bar (lower 8 bits) */
610 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
611
612 /* Pixel Number of End of Left Bar (upper 8 bits) */
613 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
614
615 /* Pixel Number of Start of Right Bar (lower 8 bits) */
616 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
617
618 /* Pixel Number of Start of Right Bar (upper 8 bits) */
619 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
620}
621
622/**
623 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
624 */
625static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
626{
627 /* Audio InfoFrame */
628 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
629
630 /* Packet Type = 0x84 */
631 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
632
633 /* Version Number = 0x01 */
634 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
635
636 /* 0 Length = 10 (0x0A) */
637 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
638
639 /* n. a. Checksum */
640 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
641
642 /* Audio Channel Count = Refer to Stream Header */
643 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
644
645 /* Refer to Stream Header */
646 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
647
648 /* Format depends on coding type (i.e. CT0...CT3) */
649 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
650
651 /* Speaker Channel Allocation = Front Right + Front Left */
652 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
653
654 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
655 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
656
657 /* Reserved (0) */
658 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
659 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
660 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
661 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
662 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
663}
664
6011bdea
GL		 665/**
666 * sh_hdmi_configure() - Initialise HDMI for output
667 */
668static void sh_hdmi_configure(struct sh_hdmi *hdmi)
669{
670 /* Configure video format */
671 sh_hdmi_video_config(hdmi);
672
673 /* Configure audio format */
674 sh_hdmi_audio_config(hdmi);
675
676 /* Configure PHY */
677 sh_hdmi_phy_config(hdmi);
678
679 /* Auxiliary Video Information (AVI) InfoFrame */
680 sh_hdmi_avi_infoframe_setup(hdmi);
681
682 /* Audio InfoFrame */
683 sh_hdmi_audio_infoframe_setup(hdmi);
684
6011bdea
GL		 685 /*
686 * Control packet auto send with VSYNC control: auto send
687 * General control, Gamut metadata, ISRC, and ACP packets
688 */
689 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
690
691 /* FIXME */
692 msleep(10);
693
694 /* PS mode b->d, reset PLLA and PLLB */
695 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
696
697 udelay(10);
698
699 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
700}
701
f1198d1e 702static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
c36940e6
GL		 703 const struct fb_videomode *mode,
704 unsigned long *hdmi_rate, unsigned long *parent_rate)
6011bdea 705{
c36940e6
GL		 706 unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
707 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
708
709 *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
710 if ((long)*hdmi_rate < 0)
711 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
712
713 rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
714 if (rate_error && pdata->clk_optimize_parent)
715 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
716 else if (clk_get_parent(hdmi->hdmi_clk))
717 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
f1198d1e
GL		 718
719 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
720 mode->left_margin, mode->xres,
721 mode->right_margin, mode->hsync_len,
722 mode->upper_margin, mode->yres,
723 mode->lower_margin, mode->vsync_len);
724
c36940e6
GL		 725 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
726 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
727 mode->refresh, *parent_rate);
f1198d1e
GL		 728
729 return rate_error;
730}
731
c36940e6
GL		 732static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
733 unsigned long *parent_rate)
6011bdea 734{
6ee48452 735 struct fb_var_screeninfo tmpvar;
6ee48452 736 struct fb_var_screeninfo *var = &tmpvar;
afe417c0 737 const struct fb_videomode *mode, *found = NULL;
f1198d1e
GL		 738 struct fb_info *info = hdmi->info;
739 struct fb_modelist *modelist = NULL;
740 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
741 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
c7321d6f 742 bool scanning = false, preferred_bad = false;
6011bdea 743 u8 edid[128];
f1198d1e
GL		 744 char *forced;
745 int i;
6011bdea
GL		 746
747 /* Read EDID */
6aa966e6 748 dev_dbg(hdmi->dev, "Read back EDID code:");
6011bdea
GL		 749 for (i = 0; i < 128; i++) {
750 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
751#ifdef DEBUG
752 if ((i % 16) == 0) {
753 printk(KERN_CONT "\n");
754 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
755 } else {
756 printk(KERN_CONT " %02X", edid[i]);
757 }
758#endif
759 }
760#ifdef DEBUG
761 printk(KERN_CONT "\n");
762#endif
afe417c0 763
4232f607
GL		 764 if (!hdmi->edid_blocks) {
765 fb_edid_to_monspecs(edid, &hdmi->monspec);
766 hdmi->edid_blocks = edid[126] + 1;
767
768 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
769 hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
770 } else {
771 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
772 edid[0], edid[2]);
773 fb_edid_add_monspecs(edid, &hdmi->monspec);
774 }
775
776 if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
777 (hdmi->edid_block_addr >> 7) + 1) {
778 /* More blocks to read */
779 if (hdmi->edid_block_addr) {
780 hdmi->edid_block_addr = 0;
781 hdmi->edid_segment_nr++;
782 } else {
783 hdmi->edid_block_addr = 0x80;
784 }
785 /* Set EDID word address */
786 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
787 /* Enable EDID interrupt */
788 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
789 /* Set EDID segment pointer - starts reading EDID */
790 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
791 return -EAGAIN;
792 }
793
794 /* All E-EDID blocks ready */
795 dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
afe417c0 796
f1198d1e
GL		 797 fb_get_options("sh_mobile_lcdc", &forced);
798 if (forced && *forced) {
799 /* Only primitive parsing so far */
800 i = sscanf(forced, "%ux%u@%u",
801 &f_width, &f_height, &f_refresh);
802 if (i < 2) {
803 f_width = 0;
804 f_height = 0;
c7321d6f
GL		 805 } else {
806 /* The user wants us to use the EDID data */
807 scanning = true;
f1198d1e
GL		 808 }
809 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
810 f_width, f_height, f_refresh);
811 }
812
813 /* Walk monitor modes to find the best or the exact match */
814 for (i = 0, mode = hdmi->monspec.modedb;
c7321d6f 815 i < hdmi->monspec.modedb_len && scanning;
afe417c0 816 i++, mode++) {
c36940e6 817 unsigned long rate_error;
f1198d1e 818
c7321d6f
GL		 819 if (!f_width && !f_height) {
820 /*
821 * A parameter string "video=sh_mobile_lcdc:0x0" means
822 * use the preferred EDID mode. If it is rejected by
823 * .fb_check_var(), keep looking, until an acceptable
824 * one is found.
825 */
826 if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
827 scanning = false;
828 else
829 continue;
830 } else if (f_width != mode->xres || f_height != mode->yres) {
831 /* No interest in unmatching modes */
f1198d1e 832 continue;
c7321d6f 833 }
c36940e6
GL		 834
835 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
836
c7321d6f
GL		 837 if (scanning) {
838 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
839 /*
840 * Exact match if either the refresh rate
841 * matches or it hasn't been specified and we've
842 * found a mode, for which we can configure the
843 * clock precisely
844 */
845 scanning = false;
846 else if (found && found_rate_error <= rate_error)
847 /*
848 * We otherwise search for the closest matching
849 * clock rate - either if no refresh rate has
850 * been specified or we cannot find an exactly
851 * matching one
852 */
853 continue;
854 }
f1198d1e
GL		 855
856 /* Check if supported: sufficient fb memory, supported clock-rate */
857 fb_videomode_to_var(var, mode);
858
c7321d6f
GL		 859 var->bits_per_pixel = info->var.bits_per_pixel;
860
f1198d1e
GL		 861 if (info && info->fbops->fb_check_var &&
862 info->fbops->fb_check_var(var, info)) {
c7321d6f
GL		 863 scanning = true;
864 preferred_bad = true;
f1198d1e 865 continue;
afe417c0 866 }
f1198d1e
GL		 867
868 found = mode;
869 found_rate_error = rate_error;
afe417c0
GL		 870 }
871
8c1ac08b
GL		 872 hdmi->var.width = hdmi->monspec.max_x * 10;
873 hdmi->var.height = hdmi->monspec.max_y * 10;
874
afe417c0 875 /*
f1198d1e
GL		 876 * TODO 1: if no ->info is present, postpone running the config until
877 * after ->info first gets registered.
878 * TODO 2: consider registering the HDMI platform device from the LCDC
879 * driver, and passing ->info with HDMI platform data.
afe417c0 880 */
f1198d1e 881 if (info && !found) {
0d7fa180
GL		 882 modelist = info->modelist.next &&
883 !list_empty(&info->modelist) ?
884 list_entry(info->modelist.next,
f1198d1e
GL		 885 struct fb_modelist, list) :
886 NULL;
887
888 if (modelist) {
889 found = &modelist->mode;
c36940e6 890 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
afe417c0
GL		 891 }
892 }
893
afe417c0
GL		 894 /* No cookie today */
895 if (!found)
896 return -ENXIO;
897
0ea2af1c
GL		 898 if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
899 hdmi->preprogrammed_vic = 1;
900 else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
901 hdmi->preprogrammed_vic = 2;
902 else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
903 hdmi->preprogrammed_vic = 17;
904 else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
905 hdmi->preprogrammed_vic = 4;
906 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
907 hdmi->preprogrammed_vic = 32;
908 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
909 hdmi->preprogrammed_vic = 31;
910 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
911 hdmi->preprogrammed_vic = 16;
89712699 912 else
0ea2af1c 913 hdmi->preprogrammed_vic = 0;
89712699 914
c36940e6 915 dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
0ea2af1c 916 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
c36940e6
GL		 917 found->xres, found->yres, found->refresh,
918 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
919
afe417c0 920 fb_videomode_to_var(&hdmi->var, found);
6aa966e6 921 sh_hdmi_external_video_param(hdmi);
afe417c0
GL		 922
923 return 0;
6011bdea
GL		 924}
925
926static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
927{
928 struct sh_hdmi *hdmi = dev_id;
929 u8 status1, status2, mask1, mask2;
930
931 /* mode_b and PLLA and PLLB reset */
932 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
933
934 /* How long shall reset be held? */
935 udelay(10);
936
937 /* mode_b and PLLA and PLLB reset release */
938 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
939
940 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
941 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
942
943 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
944 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
945
946 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
947 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
948 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
949
950 if (printk_ratelimit())
6aa966e6
GL		 951 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
952 irq, status1, mask1, status2, mask2);
6011bdea
GL		 953
954 if (!((status1 & mask1) | (status2 & mask2))) {
955 return IRQ_NONE;
956 } else if (status1 & 0xc0) {
957 u8 msens;
958
959 /* Datasheet specifies 10ms... */
960 udelay(500);
961
962 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
6aa966e6 963 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
6011bdea
GL		 964 /* Check, if hot plug & MSENS pin status are both high */
965 if ((msens & 0xC0) == 0xC0) {
966 /* Display plug in */
4232f607
GL		 967 hdmi->edid_segment_nr = 0;
968 hdmi->edid_block_addr = 0;
969 hdmi->edid_blocks = 0;
6011bdea
GL		 970 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
971
972 /* Set EDID word address */
973 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
6011bdea
GL		 974 /* Enable EDID interrupt */
975 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
4232f607
GL		 976 /* Set EDID segment pointer - starts reading EDID */
977 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
6011bdea
GL		 978 } else if (!(status1 & 0x80)) {
979 /* Display unplug, beware multiple interrupts */
4232f607
GL		 980 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
981 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6011bdea 982 schedule_delayed_work(&hdmi->edid_work, 0);
4232f607 983 }
6011bdea
GL		 984 /* display_off will switch back to mode_a */
985 }
986 } else if (status1 & 2) {
987 /* EDID error interrupt: retry */
988 /* Set EDID word address */
4232f607 989 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
6011bdea 990 /* Set EDID segment pointer */
4232f607 991 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
6011bdea
GL		 992 } else if (status1 & 4) {
993 /* Disable EDID interrupt */
994 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
6011bdea
GL		 995 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
996 }
997
998 return IRQ_HANDLED;
999}
1000
6de9edd5 1001/* locking: called with info->lock held, or before register_framebuffer() */
6aa966e6 1002static void sh_hdmi_display_on(void *arg, struct fb_info *info)
6011bdea 1003{
6de9edd5
GL		 1004 /*
1005 * info is guaranteed to be valid, when we are called, because our
1006 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
1007 */
6011bdea
GL		 1008 struct sh_hdmi *hdmi = arg;
1009 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 1010 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea 1011
6aa966e6
GL		 1012 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
1013 pdata->lcd_dev, info->state);
6de9edd5
GL		 1014
1015 /* No need to lock */
6011bdea 1016 hdmi->info = info;
6011bdea 1017
6011bdea 1018 /*
6aa966e6
GL		 1019 * hp_state can be set to
1020 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
1021 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
1022 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
6011bdea 1023 */
6011bdea
GL		 1024 switch (hdmi->hp_state) {
1025 case HDMI_HOTPLUG_EDID_DONE:
1026 /* PS mode d->e. All functions are active */
1027 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
6aa966e6 1028 dev_dbg(hdmi->dev, "HDMI running\n");
6011bdea
GL		 1029 break;
1030 case HDMI_HOTPLUG_DISCONNECTED:
1031 info->state = FBINFO_STATE_SUSPENDED;
1032 default:
1c120deb 1033 hdmi->var = ch->display_var;
6011bdea
GL		 1034 }
1035}
1036
6de9edd5 1037/* locking: called with info->lock held */
6aa966e6 1038static void sh_hdmi_display_off(void *arg)
6011bdea
GL		 1039{
1040 struct sh_hdmi *hdmi = arg;
1041 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1042
6aa966e6 1043 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
6011bdea
GL		 1044 /* PS mode e->a */
1045 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1046}
1047
afe417c0
GL		 1048static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1049{
1050 struct fb_info *info = hdmi->info;
1051 struct sh_mobile_lcdc_chan *ch = info->par;
1052 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1053 struct fb_videomode mode1, mode2;
1054
1055 fb_var_to_videomode(&mode1, old_var);
1056 fb_var_to_videomode(&mode2, new_var);
1057
1058 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1059 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1060
8c1ac08b
GL		 1061 if (fb_mode_is_equal(&mode1, &mode2)) {
1062 /* It can be a different monitor with an equal video-mode */
1063 old_var->width = new_var->width;
1064 old_var->height = new_var->height;
afe417c0 1065 return false;
8c1ac08b 1066 }
afe417c0
GL		 1067
1068 dev_dbg(info->dev, "Switching %u -> %u lines\n",
1069 mode1.yres, mode2.yres);
1070 *old_var = *new_var;
1071
1072 return true;
1073}
1074
1075/**
1076 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
c36940e6
GL		 1077 * @hdmi: driver context
1078 * @hdmi_rate: HDMI clock frequency in Hz
1079 * @parent_rate: if != 0 - set parent clock rate for optimal precision
1080 * return: configured positive rate if successful
1081 * 0 if couldn't set the rate, but managed to enable the
1082 * clock, negative error, if couldn't enable the clock
afe417c0 1083 */
c36940e6
GL		 1084static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1085 unsigned long parent_rate)
afe417c0 1086{
afe417c0
GL		 1087 int ret;
1088
c36940e6
GL		 1089 if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1090 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
afe417c0 1091 if (ret < 0) {
c36940e6
GL		 1092 dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1093 hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
afe417c0 1094 } else {
c36940e6 1095 dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
afe417c0 1096 }
afe417c0
GL		 1097 }
1098
c36940e6 1099 ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
afe417c0 1100 if (ret < 0) {
c36940e6
GL		 1101 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1102 hdmi_rate = 0;
1103 } else {
1104 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
afe417c0
GL		 1105 }
1106
c36940e6 1107 return hdmi_rate;
afe417c0
GL		 1108}
1109
6011bdea 1110/* Hotplug interrupt occurred, read EDID */
6aa966e6 1111static void sh_hdmi_edid_work_fn(struct work_struct *work)
6011bdea
GL		 1112{
1113 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
4a47a0e0 1114 struct fb_info *info;
6011bdea 1115 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 1116 struct sh_mobile_lcdc_chan *ch;
afe417c0 1117 int ret;
6011bdea 1118
6aa966e6
GL		 1119 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1120 pdata->lcd_dev, hdmi->hp_state);
6011bdea
GL		 1121
1122 if (!pdata->lcd_dev)
1123 return;
1124
6de9edd5
GL		 1125 mutex_lock(&hdmi->mutex);
1126
4a47a0e0
BP		 1127 info = hdmi->info;
1128
4232f607 1129 if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
c36940e6
GL		 1130 unsigned long parent_rate = 0, hdmi_rate;
1131
c36940e6 1132 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
d521dd94 1133 if (ret < 0)
afe417c0
GL		 1134 goto out;
1135
4232f607
GL		 1136 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1137
afe417c0 1138 /* Reconfigure the clock */
c36940e6 1139 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
d521dd94 1140 if (ret < 0)
afe417c0
GL		 1141 goto out;
1142
6011bdea
GL		 1143 msleep(10);
1144 sh_hdmi_configure(hdmi);
1145 /* Switched to another (d) power-save mode */
1146 msleep(10);
1147
0d7fa180 1148 if (!info)
6de9edd5 1149 goto out;
6011bdea 1150
0d7fa180 1151 ch = info->par;
6011bdea 1152
4a47a0e0
BP		 1153 if (lock_fb_info(info)) {
1154 console_lock();
6011bdea 1155
4a47a0e0
BP		 1156 /* HDMI plug in */
1157 if (!sh_hdmi_must_reconfigure(hdmi) &&
1158 info->state == FBINFO_STATE_RUNNING) {
1159 /*
1160 * First activation with the default monitor - just turn
1161 * on, if we run a resume here, the logo disappears
1162 */
8c1ac08b
GL		 1163 info->var.width = hdmi->var.width;
1164 info->var.height = hdmi->var.height;
1165 sh_hdmi_display_on(hdmi, info);
4a47a0e0
BP		 1166 } else {
1167 /* New monitor or have to wake up */
1168 fb_set_suspend(info, 0);
6de9edd5 1169 }
6011bdea 1170
4a47a0e0
BP		 1171 console_unlock();
1172 unlock_fb_info(info);
1173 }
6011bdea 1174 } else {
afe417c0 1175 ret = 0;
4a47a0e0 1176 if (!info)
6de9edd5 1177 goto out;
6011bdea 1178
91d63f8a
GL		 1179 hdmi->monspec.modedb_len = 0;
1180 fb_destroy_modedb(hdmi->monspec.modedb);
1181 hdmi->monspec.modedb = NULL;
1182
4a47a0e0
BP		 1183 if (lock_fb_info(info)) {
1184 console_lock();
6011bdea 1185
4a47a0e0
BP		 1186 /* HDMI disconnect */
1187 fb_set_suspend(info, 1);
6011bdea 1188
4a47a0e0
BP		 1189 console_unlock();
1190 unlock_fb_info(info);
1191 }
6011bdea
GL		 1192 }
1193
6de9edd5 1194out:
4232f607 1195 if (ret < 0 && ret != -EAGAIN)
afe417c0 1196 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6de9edd5
GL		 1197 mutex_unlock(&hdmi->mutex);
1198
6aa966e6 1199 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
6011bdea
GL		 1200}
1201
6de9edd5
GL		 1202static int sh_hdmi_notify(struct notifier_block *nb,
1203 unsigned long action, void *data)
1204{
1205 struct fb_event *event = data;
1206 struct fb_info *info = event->info;
1207 struct sh_mobile_lcdc_chan *ch = info->par;
1208 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1209 struct sh_hdmi *hdmi = board_cfg->board_data;
1210
eb0778bd 1211 if (!hdmi || nb != &hdmi->notifier || hdmi->info != info)
6de9edd5
GL		 1212 return NOTIFY_DONE;
1213
1214 switch(action) {
1215 case FB_EVENT_FB_REGISTERED:
6aa966e6 1216 /* Unneeded, activation taken care by sh_hdmi_display_on() */
6de9edd5
GL		 1217 break;
1218 case FB_EVENT_FB_UNREGISTERED:
1219 /*
1220 * We are called from unregister_framebuffer() with the
1221 * info->lock held. This is bad for us, because we can race with
1222 * the scheduled work, which has to call fb_set_suspend(), which
6aa966e6
GL		 1223 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1224 * cannot take and hold info->lock for the whole function
1225 * duration. Using an additional lock creates a classical AB-BA
1226 * lock up. Therefore, we have to release the info->lock
1227 * temporarily, synchronise with the work queue and re-acquire
1228 * the info->lock.
6de9edd5 1229 */
eb0778bd 1230 unlock_fb_info(info);
6de9edd5
GL		 1231 mutex_lock(&hdmi->mutex);
1232 hdmi->info = NULL;
1233 mutex_unlock(&hdmi->mutex);
eb0778bd 1234 lock_fb_info(info);
6de9edd5
GL		 1235 return NOTIFY_OK;
1236 }
1237 return NOTIFY_DONE;
6011bdea
GL		 1238}
1239
1240static int __init sh_hdmi_probe(struct platform_device *pdev)
1241{
1242 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1243 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1244 struct sh_mobile_lcdc_board_cfg *board_cfg;
6011bdea
GL		 1245 int irq = platform_get_irq(pdev, 0), ret;
1246 struct sh_hdmi *hdmi;
1247 long rate;
1248
1249 if (!res || !pdata || irq < 0)
1250 return -ENODEV;
1251
1252 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1253 if (!hdmi) {
1254 dev_err(&pdev->dev, "Cannot allocate device data\n");
1255 return -ENOMEM;
1256 }
1257
6de9edd5 1258 mutex_init(&hdmi->mutex);
1d6be338 1259
6011bdea
GL		 1260 hdmi->dev = &pdev->dev;
1261
1262 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1263 if (IS_ERR(hdmi->hdmi_clk)) {
1264 ret = PTR_ERR(hdmi->hdmi_clk);
1265 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1266 goto egetclk;
1267 }
1268
c36940e6
GL		 1269 /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1270 rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1271 if (rate > 0)
1272 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1273
6011bdea
GL		 1274 if (rate < 0) {
1275 ret = rate;
6011bdea
GL		 1276 goto erate;
1277 }
1278
c36940e6
GL		 1279 ret = clk_enable(hdmi->hdmi_clk);
1280 if (ret < 0) {
1281 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1282 goto erate;
1283 }
1284
afe417c0 1285 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
6011bdea
GL		 1286
1287 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1288 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1289 ret = -EBUSY;
1290 goto ereqreg;
1291 }
1292
1293 hdmi->base = ioremap(res->start, resource_size(res));
1294 if (!hdmi->base) {
1295 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1296 ret = -ENOMEM;
1297 goto emap;
1298 }
1299
1300 platform_set_drvdata(pdev, hdmi);
1301
6011bdea 1302 /* Set up LCDC callbacks */
6de9edd5
GL		 1303 board_cfg = &pdata->lcd_chan->board_cfg;
1304 board_cfg->owner = THIS_MODULE;
1305 board_cfg->board_data = hdmi;
6aa966e6
GL		 1306 board_cfg->display_on = sh_hdmi_display_on;
1307 board_cfg->display_off = sh_hdmi_display_off;
6011bdea 1308
6aa966e6 1309 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
6011bdea
GL		 1310
1311 pm_runtime_enable(&pdev->dev);
d521dd94 1312 pm_runtime_get_sync(&pdev->dev);
6011bdea 1313
c36940e6
GL		 1314 /* Product and revision IDs are 0 in sh-mobile version */
1315 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1316 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1317
6011bdea
GL		 1318 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1319 dev_name(&pdev->dev), hdmi);
1320 if (ret < 0) {
1321 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1322 goto ereqirq;
1323 }
1324
b3773301
RK		 1325 ret = snd_soc_register_codec(&pdev->dev,
1326 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1327 if (ret < 0) {
1328 dev_err(&pdev->dev, "codec registration failed\n");
1329 goto ecodec;
1330 }
1331
eb0778bd
GL		 1332 hdmi->notifier.notifier_call = sh_hdmi_notify;
1333 fb_register_client(&hdmi->notifier);
1334
6011bdea
GL		 1335 return 0;
1336
b3773301
RK		 1337ecodec:
1338 free_irq(irq, hdmi);
6011bdea 1339ereqirq:
d521dd94 1340 pm_runtime_put(&pdev->dev);
6011bdea
GL		 1341 pm_runtime_disable(&pdev->dev);
1342 iounmap(hdmi->base);
1343emap:
1344 release_mem_region(res->start, resource_size(res));
1345ereqreg:
1346 clk_disable(hdmi->hdmi_clk);
6011bdea
GL		 1347erate:
1348 clk_put(hdmi->hdmi_clk);
1349egetclk:
6de9edd5 1350 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1351 kfree(hdmi);
1352
1353 return ret;
1354}
1355
1356static int __exit sh_hdmi_remove(struct platform_device *pdev)
1357{
1358 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1359 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1360 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1361 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
6011bdea
GL		 1362 int irq = platform_get_irq(pdev, 0);
1363
1d6be338
KM		 1364 snd_soc_unregister_codec(&pdev->dev);
1365
eb0778bd
GL		 1366 fb_unregister_client(&hdmi->notifier);
1367
6de9edd5
GL		 1368 board_cfg->display_on = NULL;
1369 board_cfg->display_off = NULL;
1370 board_cfg->board_data = NULL;
1371 board_cfg->owner = NULL;
6011bdea 1372
6de9edd5 1373 /* No new work will be scheduled, wait for running ISR */
6011bdea 1374 free_irq(irq, hdmi);
6de9edd5 1375 /* Wait for already scheduled work */
6011bdea 1376 cancel_delayed_work_sync(&hdmi->edid_work);
d521dd94 1377 pm_runtime_put(&pdev->dev);
6de9edd5 1378 pm_runtime_disable(&pdev->dev);
6011bdea
GL		 1379 clk_disable(hdmi->hdmi_clk);
1380 clk_put(hdmi->hdmi_clk);
1381 iounmap(hdmi->base);
1382 release_mem_region(res->start, resource_size(res));
6de9edd5 1383 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1384 kfree(hdmi);
1385
1386 return 0;
1387}
1388
1389static struct platform_driver sh_hdmi_driver = {
1390 .remove = __exit_p(sh_hdmi_remove),
1391 .driver = {
1392 .name = "sh-mobile-hdmi",
1393 },
1394};
1395
1396static int __init sh_hdmi_init(void)
1397{
1398 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1399}
1400module_init(sh_hdmi_init);
1401
1402static void __exit sh_hdmi_exit(void)
1403{
1404 platform_driver_unregister(&sh_hdmi_driver);
1405}
1406module_exit(sh_hdmi_exit);
1407
1408MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1409MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1410MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)