[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/bitmap.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/module.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define VMLEN2		0x002c
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct platform_device *pdev;

	void	*next_board_data;
	void	(*next_display_on)(void *board_data, struct fb_info *info);
	void	(*next_display_off)(void *board_data);
};

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = platform_get_drvdata(pdev);

	sh_mipi_dsi_enable(mipi, false);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt, linelength, vmctr2;
	u32 tmp, top, bottom, delay, div;
	bool yuv;
	int bpp;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_cfg[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	if (!pdata->lane)
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on */
	iowrite32(0x03070001, base + PHYCTRL);

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 */
	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	tmp |= 0x00003700;
	iowrite32(tmp, base + SYSCONF);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) |
		  (pdata->clksrc << 16) | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);

	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	vmctr2 = 0;
	if (pdata->flags & SH_MIPI_DSI_VSEE)
		vmctr2 |= 1 << 23;
	if (pdata->flags & SH_MIPI_DSI_HSEE)
		vmctr2 |= 1 << 22;
	if (pdata->flags & SH_MIPI_DSI_HSAE)
		vmctr2 |= 1 << 21;
	if (pdata->flags & SH_MIPI_DSI_BL2E)
		vmctr2 |= 1 << 17;
	if (pdata->flags & SH_MIPI_DSI_HSABM)
		vmctr2 |= 1 << 5;
	if (pdata->flags & SH_MIPI_DSI_HBPBM)
		vmctr2 |= 1 << 4;
	if (pdata->flags & SH_MIPI_DSI_HFPBM)
		vmctr2 |= 1 << 3;
	iowrite32(vmctr2, mipi->linkbase + VMCTR2);

	/*
	 * VMLEN1 = RGBLEN | HSALEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top = linelength << 16; /* RGBLEN */
	bottom = 0x00000001;
	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
		bottom = (pdata->lane * ch->lcd_cfg[0].hsync_len) - 10;
	iowrite32(top | bottom , mipi->linkbase + VMLEN1);

	/*
	 * VMLEN2 = HBPLEN | HFPLEN
	 *
	 * see
	 *  Video mode - Blanking Packet setting
	 */
	top	= 0x00010000;
	bottom	= 0x00000001;
	delay	= 0;

	div = 1;	/* HSbyteCLK is calculation base
			 * HS4divCLK = HSbyteCLK/2
			 * HS6divCLK is not supported for now */
	if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
		div = 2;

	if (pdata->flags & SH_MIPI_DSI_HFPBM) {	/* HBPLEN */
		top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin;
		top = ((pdata->lane * top / div) - 10) << 16;
	}
	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
		bottom = ch->lcd_cfg[0].right_margin;
		bottom = (pdata->lane * bottom / div) - 12;
	}

	bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */
	if ((pdata->lane / div) > bpp) {
		tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */
		tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */
		delay = (pdata->lane * tmp);
	}

	iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);

	return 0;
}

static void mipi_display_on(void *arg, struct fb_info *info)
{
	struct sh_mipi *mipi = arg;
	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	int ret;

	pm_runtime_get_sync(&mipi->pdev->dev);

	ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
	if (ret < 0)
		goto mipi_display_on_fail1;

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto mipi_display_on_fail2;

	sh_mipi_dsi_enable(mipi, true);

	if (mipi->next_display_on)
		mipi->next_display_on(mipi->next_board_data, info);

	return;

mipi_display_on_fail1:
	pm_runtime_put_sync(&mipi->pdev->dev);
mipi_display_on_fail2:
	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
}

static void mipi_display_off(void *arg)
{
	struct sh_mipi *mipi = arg;
	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;

	if (mipi->next_display_off)
		mipi->next_display_off(mipi->next_board_data);

	sh_mipi_dsi_enable(mipi, false);

	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);

	pm_runtime_put_sync(&mipi->pdev->dev);
}

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	if (!pdata->set_dot_clock)
		return -EINVAL;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->pdev = pdev;

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	mipi_dsi[idx] = mipi;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, mipi);

	/* Save original LCDC callbacks */
	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;

	/* Set up LCDC callbacks */
	pdata->lcd_chan->board_cfg.board_data = mipi;
	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;

	return 0;

eclkton:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pdata->lcd_chan->board_cfg.owner = NULL;
	pdata->lcd_chan->board_cfg.display_on = NULL;
	pdata->lcd_chan->board_cfg.display_off = NULL;
	pdata->lcd_chan->board_cfg.board_data = NULL;

	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);

	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
26c3d7ac	11	#include <linux/bitmap.h>
9fd04fe3 GL	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/platform_device.h>
236782a5	17	#include <linux/pm_runtime.h>
9fd04fe3 GL	18	#include <linux/slab.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
355b200b	21	#include <linux/module.h>
9fd04fe3 GL	22
	23	#include <video/mipi_display.h>
	24	#include <video/sh_mipi_dsi.h>
	25	#include <video/sh_mobile_lcdc.h>
	26
71b146c8 MD	27	#define SYSCTRL 0x0000
	28	#define SYSCONF 0x0004
	29	#define TIMSET 0x0008
	30	#define RESREQSET0 0x0018
	31	#define RESREQSET1 0x001c
	32	#define HSTTOVSET 0x0020
	33	#define LPRTOVSET 0x0024
	34	#define TATOVSET 0x0028
	35	#define PRTOVSET 0x002c
	36	#define DSICTRL 0x0030
	37	#define DSIINTE 0x0060
	38	#define PHYCTRL 0x0070
	39
deaba190 MD	40	/* relative to linkbase */
	41	#define DTCTR 0x0000
	42	#define VMCTR1 0x0020
	43	#define VMCTR2 0x0024
	44	#define VMLEN1 0x0028
08750617	45	#define VMLEN2 0x002c
deaba190 MD	46	#define CMTSRTREQ 0x0070
deaba190 MD	47	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	48
	49	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	50	#define MAX_SH_MIPI_DSI 2
	51
	52	struct sh_mipi {
	53	void __iomem *base;
deaba190	54	void __iomem *linkbase;
9fd04fe3	55	struct clk *dsit_clk;
7d9f88b4	56	struct platform_device *pdev;
236782a5 GL	57
	58	void *next_board_data;
	59	void (next_display_on)(void board_data, struct fb_info *info);
	60	void (next_display_off)(void board_data);
9fd04fe3 GL	61	};
	62
	63	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	64
	65	/* Protect the above array */
	66	static DEFINE_MUTEX(array_lock);
	67
	68	static struct sh_mipi *sh_mipi_by_handle(int handle)
	69	{
	70	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	71	return NULL;
	72
	73	return mipi_dsi[handle];
	74	}
	75
	76	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	77	u8 cmd, u8 param)
	78	{
	79	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	80	int cnt = 100;
	81
	82	/* transmit a short packet to LCD panel */
deaba190 MD	83	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	84	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	85
deaba190	86	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	87	udelay(1);
	88
	89	return cnt ? 0 : -ETIMEDOUT;
	90	}
	91
	92	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	93	-EINVAL : (c) - 1)
	94
	95	static int sh_mipi_dcs(int handle, u8 cmd)
	96	{
	97	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	98	if (!mipi)
	99	return -ENODEV;
	100	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	101	}
	102
	103	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	104	{
	105	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	106	if (!mipi)
	107	return -ENODEV;
	108	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	109	param);
	110	}
	111
	112	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	113	{
	114	/*
	115	* enable LCDC data tx, transition to LPS after completion of each HS
	116	* packet
	117	*/
deaba190	118	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	119	}
	120
	121	static void sh_mipi_shutdown(struct platform_device *pdev)
	122	{
	123	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	124
	125	sh_mipi_dsi_enable(mipi, false);
	126	}
	127
9fd04fe3 GL	128	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	129	struct sh_mipi_dsi_info *pdata)
	130	{
	131	void __iomem *base = mipi->base;
	132	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
f832906a	133	u32 pctype, datatype, pixfmt, linelength, vmctr2;
a2e62971	134	u32 tmp, top, bottom, delay, div;
9fd04fe3	135	bool yuv;
08750617	136	int bpp;
9fd04fe3	137
44432407 GL	138	/*
	139	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	140	* the default videomode. If this ever becomes a problem, We'll have to
	141	* move this to mipi_display_on() above and use info->var.xres
	142	*/
9fd04fe3 GL	143	switch (pdata->data_format) {
	144	case MIPI_RGB888:
	145	pctype = 0;
	146	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	147	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	148	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	149	yuv = false;
	150	break;
	151	case MIPI_RGB565:
	152	pctype = 1;
	153	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	154	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	155	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	156	yuv = false;
	157	break;
	158	case MIPI_RGB666_LP:
	159	pctype = 2;
	160	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	161	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	162	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	163	yuv = false;
	164	break;
	165	case MIPI_RGB666:
	166	pctype = 3;
	167	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	168	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	169	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	170	yuv = false;
	171	break;
	172	case MIPI_BGR888:
	173	pctype = 8;
	174	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	175	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	176	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	177	yuv = false;
	178	break;
	179	case MIPI_BGR565:
	180	pctype = 9;
	181	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	182	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	183	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	184	yuv = false;
	185	break;
	186	case MIPI_BGR666_LP:
	187	pctype = 0xa;
	188	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	189	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	190	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	191	yuv = false;
	192	break;
	193	case MIPI_BGR666:
	194	pctype = 0xb;
	195	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	196	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	197	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	198	yuv = false;
	199	break;
	200	case MIPI_YUYV:
	201	pctype = 4;
	202	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	203	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	204	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	205	yuv = true;
	206	break;
	207	case MIPI_UYVY:
	208	pctype = 5;
	209	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	210	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	211	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	212	yuv = true;
	213	break;
	214	case MIPI_YUV420_L:
	215	pctype = 6;
	216	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	217	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
44432407	218	linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
9fd04fe3 GL	219	yuv = true;
	220	break;
	221	case MIPI_YUV420:
	222	pctype = 7;
	223	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	224	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	225	/* Length of U/V line */
44432407	226	linelength = (ch->lcd_cfg[0].xres + 1) / 2;
9fd04fe3 GL	227	yuv = true;
	228	break;
	229	default:
	230	return -EINVAL;
	231	}
	232
	233	if ((yuv && ch->interface_type != YUV422) \|\|
	234	(!yuv && ch->interface_type != RGB24))
	235	return -EINVAL;
	236
26c3d7ac KM	237	if (!pdata->lane)
	238	return -EINVAL;
	239
9fd04fe3	240	/* reset DSI link */
71b146c8	241	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	242	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	243	udelay(50);
71b146c8	244	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	245
	246	/* setup DSI link */
	247
9fd04fe3 GL	248	/*
	249	* T_wakeup = 0x7000
	250	* T_hs-trail = 3
	251	* T_hs-prepare = 3
	252	* T_clk-trail = 3
	253	* T_clk-prepare = 2
	254	*/
71b146c8	255	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	256	/* no responses requested */
71b146c8	257	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	258	/* request response to packets of type 0x28 */
71b146c8	259	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	260	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	261	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	262	/* LP reception timeout, default 0xffffffff */
71b146c8	263	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	264	/* Turn-around timeout, default 0xffffffff */
71b146c8	265	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	266	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	267	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3 GL	268	/* Interrupts not used, disable all */
	269	iowrite32(0, base + DSIINTE);
	270	/* DSI-Tx bias on */
71b146c8	271	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3	272	udelay(200);
5e47431a KM	273	/* Deassert resets, power on */
5e47431a KM	274	iowrite32(0x03070001, base + PHYCTRL);
9fd04fe3	275
a2065a36 KM	276	/*
	277	* Default = ULPS enable \|
	278	* Contention detection enabled \|
	279	* EoT packet transmission enable \|
	280	* CRC check enable \|
	281	* ECC check enable
	282	*/
	283	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	284	tmp \|= 0x00003700;
	285	iowrite32(tmp, base + SYSCONF);
	286
9fd04fe3 GL	287	/* setup l-bridge */
	288
	289	/*
	290	* Enable transmission of all packets,
	291	* transmit LPS after each HS packet completion
	292	*/
deaba190	293	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	294	/* VSYNC width = 2 (<< 17) */
14bbb7c6 GL	295	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) \|
14bbb7c6 GL	296	(pdata->clksrc << 16) \| (pctype << 12) \| datatype,
deaba190	297	mipi->linkbase + VMCTR1);
14bbb7c6	298
9fd04fe3 GL	299	/*
	300	* Non-burst mode with sync pulses: VSE and HSE are output,
	301	* HSA period allowed, no commands in LP
	302	*/
f832906a KM	303	vmctr2 = 0;
	304	if (pdata->flags & SH_MIPI_DSI_VSEE)
	305	vmctr2 \|= 1 << 23;
	306	if (pdata->flags & SH_MIPI_DSI_HSEE)
	307	vmctr2 \|= 1 << 22;
	308	if (pdata->flags & SH_MIPI_DSI_HSAE)
	309	vmctr2 \|= 1 << 21;
d07a9d2a KM	310	if (pdata->flags & SH_MIPI_DSI_BL2E)
d07a9d2a KM	311	vmctr2 \|= 1 << 17;
14bbb7c6	312	if (pdata->flags & SH_MIPI_DSI_HSABM)
3c2a6599	313	vmctr2 \|= 1 << 5;
32ba95c6	314	if (pdata->flags & SH_MIPI_DSI_HBPBM)
3c2a6599	315	vmctr2 \|= 1 << 4;
f7b0af68 KM	316	if (pdata->flags & SH_MIPI_DSI_HFPBM)
f7b0af68 KM	317	vmctr2 \|= 1 << 3;
14bbb7c6 GL	318	iowrite32(vmctr2, mipi->linkbase + VMCTR2);
14bbb7c6 GL	319
9fd04fe3	320	/*
08750617 KM	321	* VMLEN1 = RGBLEN \| HSALEN
	322	*
	323	* see
	324	* Video mode - Blanking Packet setting
9fd04fe3	325	*/
08750617 KM	326	top = linelength << 16; /* RGBLEN */
	327	bottom = 0x00000001;
	328	if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
	329	bottom = (pdata->lane * ch->lcd_cfg[0].hsync_len) - 10;
	330	iowrite32(top \| bottom , mipi->linkbase + VMLEN1);
	331
	332	/*
	333	* VMLEN2 = HBPLEN \| HFPLEN
	334	*
	335	* see
	336	* Video mode - Blanking Packet setting
	337	*/
	338	top = 0x00010000;
	339	bottom = 0x00000001;
	340	delay = 0;
	341
a2e62971 KM	342	div = 1; /* HSbyteCLK is calculation base
	343	* HS4divCLK = HSbyteCLK/2
	344	* HS6divCLK is not supported for now */
	345	if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
	346	div = 2;
	347
08750617 KM	348	if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
08750617 KM	349	top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin;
a2e62971	350	top = ((pdata->lane * top / div) - 10) << 16;
08750617 KM	351	}
	352	if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
	353	bottom = ch->lcd_cfg[0].right_margin;
a2e62971	354	bottom = (pdata->lane * bottom / div) - 12;
08750617 KM	355	}
	356
	357	bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */
a2e62971	358	if ((pdata->lane / div) > bpp) {
08750617 KM	359	tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */
	360	tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */
	361	delay = (pdata->lane * tmp);
	362	}
	363
	364	iowrite32(top \| (bottom + delay) , mipi->linkbase + VMLEN2);
9fd04fe3 GL	365
	366	msleep(5);
	367
	368	/* setup LCD panel */
	369
	370	/* cf. drivers/video/omap/lcd_mipid.c */
	371	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	372	msleep(120);
	373	/*
	374	* [7] - Page Address Mode
	375	* [6] - Column Address Mode
	376	* [5] - Page / Column Address Mode
	377	* [4] - Display Device Line Refresh Order
	378	* [3] - RGB/BGR Order
	379	* [2] - Display Data Latch Data Order
	380	* [1] - Flip Horizontal
	381	* [0] - Flip Vertical
	382	*/
	383	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	384	/* cf. set_data_lines() */
	385	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	386	pixfmt << 4);
	387	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	388
97cab455 KM	389	/* Enable timeout counters */
	390	iowrite32(0x00000f00, base + DSICTRL);
	391
9fd04fe3 GL	392	return 0;
	393	}
	394
c2658b70 KM	395	static void mipi_display_on(void arg, struct fb_info info)
	396	{
	397	struct sh_mipi *mipi = arg;
	398	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	399	int ret;
	400
	401	pm_runtime_get_sync(&mipi->pdev->dev);
	402
	403	ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
	404	if (ret < 0)
	405	goto mipi_display_on_fail1;
	406
	407	ret = sh_mipi_setup(mipi, pdata);
	408	if (ret < 0)
	409	goto mipi_display_on_fail2;
	410
	411	sh_mipi_dsi_enable(mipi, true);
	412
	413	if (mipi->next_display_on)
	414	mipi->next_display_on(mipi->next_board_data, info);
	415
	416	return;
	417
	418	mipi_display_on_fail1:
	419	pm_runtime_put_sync(&mipi->pdev->dev);
	420	mipi_display_on_fail2:
	421	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
	422	}
	423
	424	static void mipi_display_off(void *arg)
	425	{
	426	struct sh_mipi *mipi = arg;
	427	struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
	428
	429	if (mipi->next_display_off)
	430	mipi->next_display_off(mipi->next_board_data);
	431
	432	sh_mipi_dsi_enable(mipi, false);
	433
	434	pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
	435
	436	pm_runtime_put_sync(&mipi->pdev->dev);
	437	}
	438
9fd04fe3 GL	439	static int __init sh_mipi_probe(struct platform_device *pdev)
	440	{
	441	struct sh_mipi *mipi;
	442	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	443	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	444	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	445	unsigned long rate, f_current;
9fd04fe3 GL	446	int idx = pdev->id, ret;
9fd04fe3	447
deaba190	448	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	449	return -ENODEV;
9fd04fe3 GL	450
5e47431a KM	451	if (!pdata->set_dot_clock)
	452	return -EINVAL;
	453
9fd04fe3 GL	454	mutex_lock(&array_lock);
	455	if (idx < 0)
	456	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	457	;
	458
	459	if (idx == ARRAY_SIZE(mipi_dsi)) {
	460	ret = -EBUSY;
	461	goto efindslot;
	462	}
	463
	464	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	465	if (!mipi) {
	466	ret = -ENOMEM;
	467	goto ealloc;
	468	}
	469
	470	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	471	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	472	ret = -EBUSY;
	473	goto ereqreg;
	474	}
	475
	476	mipi->base = ioremap(res->start, resource_size(res));
	477	if (!mipi->base) {
	478	ret = -ENOMEM;
	479	goto emap;
	480	}
	481
deaba190 MD	482	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	483	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	484	ret = -EBUSY;
	485	goto ereqreg2;
	486	}
	487
	488	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	489	if (!mipi->linkbase) {
	490	ret = -ENOMEM;
	491	goto emap2;
	492	}
	493
7d9f88b4	494	mipi->pdev = pdev;
236782a5	495
9fd04fe3 GL	496	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	497	if (IS_ERR(mipi->dsit_clk)) {
	498	ret = PTR_ERR(mipi->dsit_clk);
	499	goto eclktget;
	500	}
	501
	502	f_current = clk_get_rate(mipi->dsit_clk);
	503	/* 80MHz required by the datasheet */
	504	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	505	if (rate > 0 && rate != f_current)
	506	ret = clk_set_rate(mipi->dsit_clk, rate);
	507	else
	508	ret = rate;
	509	if (ret < 0)
	510	goto esettrate;
	511
	512	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	513
9fd04fe3 GL	514	ret = clk_enable(mipi->dsit_clk);
	515	if (ret < 0)
	516	goto eclkton;
	517
9fd04fe3 GL	518	mipi_dsi[idx] = mipi;
9fd04fe3 GL	519
236782a5 GL	520	pm_runtime_enable(&pdev->dev);
	521	pm_runtime_resume(&pdev->dev);
	522
9fd04fe3 GL	523	mutex_unlock(&array_lock);
	524	platform_set_drvdata(pdev, mipi);
	525
6722a401 MD	526	/* Save original LCDC callbacks */
	527	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	528	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	529	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
	530
9fd04fe3 GL	531	/* Set up LCDC callbacks */
	532	pdata->lcd_chan->board_cfg.board_data = mipi;
	533	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	534	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
236782a5	535	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;
9fd04fe3 GL	536
	537	return 0;
	538
9fd04fe3	539	eclkton:
9fd04fe3 GL	540	esettrate:
	541	clk_put(mipi->dsit_clk);
	542	eclktget:
deaba190 MD	543	iounmap(mipi->linkbase);
	544	emap2:
	545	release_mem_region(res2->start, resource_size(res2));
	546	ereqreg2:
9fd04fe3 GL	547	iounmap(mipi->base);
	548	emap:
	549	release_mem_region(res->start, resource_size(res));
	550	ereqreg:
	551	kfree(mipi);
	552	ealloc:
	553	efindslot:
	554	mutex_unlock(&array_lock);
	555
	556	return ret;
	557	}
	558
	559	static int __exit sh_mipi_remove(struct platform_device *pdev)
	560	{
	561	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	562	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	563	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	564	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	565	int i, ret;
	566
	567	mutex_lock(&array_lock);
	568
	569	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	570	;
	571
	572	if (i == ARRAY_SIZE(mipi_dsi)) {
	573	ret = -EINVAL;
	574	} else {
	575	ret = 0;
	576	mipi_dsi[i] = NULL;
	577	}
	578
	579	mutex_unlock(&array_lock);
	580
	581	if (ret < 0)
	582	return ret;
	583
236782a5	584	pdata->lcd_chan->board_cfg.owner = NULL;
9fd04fe3 GL	585	pdata->lcd_chan->board_cfg.display_on = NULL;
	586	pdata->lcd_chan->board_cfg.display_off = NULL;
	587	pdata->lcd_chan->board_cfg.board_data = NULL;
	588
236782a5	589	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	590	clk_disable(mipi->dsit_clk);
9fd04fe3 GL	591	clk_put(mipi->dsit_clk);
5e47431a	592
deaba190 MD	593	iounmap(mipi->linkbase);
	594	if (res2)
	595	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	596	iounmap(mipi->base);
	597	if (res)
	598	release_mem_region(res->start, resource_size(res));
	599	platform_set_drvdata(pdev, NULL);
	600	kfree(mipi);
	601
	602	return 0;
	603	}
	604
	605	static struct platform_driver sh_mipi_driver = {
	606	.remove = __exit_p(sh_mipi_remove),
	607	.shutdown = sh_mipi_shutdown,
	608	.driver = {
	609	.name = "sh-mipi-dsi",
	610	},
	611	};
	612
	613	static int __init sh_mipi_init(void)
	614	{
	615	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	616	}
	617	module_init(sh_mipi_init);
	618
	619	static void __exit sh_mipi_exit(void)
	620	{
	621	platform_driver_unregister(&sh_mipi_driver);
	622	}
	623	module_exit(sh_mipi_exit);
	624
	625	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	626	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	627	MODULE_LICENSE("GPL v2");