[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct clk	*dsip_clk;
	void *next_board_data;
	void (*next_display_on)(void *board_data, struct fb_info *info);
	void (*next_display_off)(void *board_data);
};

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = platform_get_drvdata(pdev);

	sh_mipi_dsi_enable(mipi, false);
}

static void mipi_display_on(void *arg, struct fb_info *info)
{
	struct sh_mipi *mipi = arg;

	sh_mipi_dsi_enable(mipi, true);

	if (mipi->next_display_on)
		mipi->next_display_on(mipi->next_board_data, info);
}

static void mipi_display_off(void *arg)
{
	struct sh_mipi *mipi = arg;

	if (mipi->next_display_off)
		mipi->next_display_off(mipi->next_board_data);

	sh_mipi_dsi_enable(mipi, false);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt;
	u32 linelength;
	bool yuv;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_cfg[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 * additionally enable first two lanes
	 */
	iowrite32(0x00003703, base + SYSCONF);
	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on, set multiplier */
	iowrite32(0x03070b01, base + PHYCTRL);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32(0x00040000 | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);
	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	iowrite32(0x00e00000, mipi->linkbase + VMCTR2);
	/*
	 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
	 * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
	 * (unused, since VMCTR2[HSABM] = 0)
	 */
	iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	return 0;
}

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;
	char dsip_clk[] = "dsi.p_clk";

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
	mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
	if (IS_ERR(mipi->dsip_clk)) {
		ret = PTR_ERR(mipi->dsip_clk);
		goto eclkpget;
	}

	f_current = clk_get_rate(mipi->dsip_clk);
	/* Between 10 and 50MHz */
	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsip_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esetprate;

	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);

	msleep(10);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	ret = clk_enable(mipi->dsip_clk);
	if (ret < 0)
		goto eclkpon;

	mipi_dsi[idx] = mipi;

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto emipisetup;

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, mipi);

	/* Save original LCDC callbacks */
	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;

	/* Set up LCDC callbacks */
	pdata->lcd_chan->board_cfg.board_data = mipi;
	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;

	return 0;

emipisetup:
	mipi_dsi[idx] = NULL;
	clk_disable(mipi->dsip_clk);
eclkpon:
	clk_disable(mipi->dsit_clk);
eclkton:
esetprate:
	clk_put(mipi->dsip_clk);
eclkpget:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pdata->lcd_chan->board_cfg.display_on = NULL;
	pdata->lcd_chan->board_cfg.display_off = NULL;
	pdata->lcd_chan->board_cfg.board_data = NULL;

	clk_disable(mipi->dsip_clk);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);
	clk_put(mipi->dsip_clk);
	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/slab.h>
	17	#include <linux/string.h>
	18	#include <linux/types.h>
	19
	20	#include <video/mipi_display.h>
	21	#include <video/sh_mipi_dsi.h>
	22	#include <video/sh_mobile_lcdc.h>
	23
71b146c8 MD	24	#define SYSCTRL 0x0000
	25	#define SYSCONF 0x0004
	26	#define TIMSET 0x0008
	27	#define RESREQSET0 0x0018
	28	#define RESREQSET1 0x001c
	29	#define HSTTOVSET 0x0020
	30	#define LPRTOVSET 0x0024
	31	#define TATOVSET 0x0028
	32	#define PRTOVSET 0x002c
	33	#define DSICTRL 0x0030
	34	#define DSIINTE 0x0060
	35	#define PHYCTRL 0x0070
	36
deaba190 MD	37	/* relative to linkbase */
	38	#define DTCTR 0x0000
	39	#define VMCTR1 0x0020
	40	#define VMCTR2 0x0024
	41	#define VMLEN1 0x0028
	42	#define CMTSRTREQ 0x0070
	43	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	44
	45	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	46	#define MAX_SH_MIPI_DSI 2
	47
	48	struct sh_mipi {
	49	void __iomem *base;
deaba190	50	void __iomem *linkbase;
9fd04fe3 GL	51	struct clk *dsit_clk;
9fd04fe3 GL	52	struct clk *dsip_clk;
6722a401 MD	53	void *next_board_data;
	54	void (next_display_on)(void board_data, struct fb_info *info);
	55	void (next_display_off)(void board_data);
9fd04fe3 GL	56	};
	57
	58	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	59
	60	/* Protect the above array */
	61	static DEFINE_MUTEX(array_lock);
	62
	63	static struct sh_mipi *sh_mipi_by_handle(int handle)
	64	{
	65	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	66	return NULL;
	67
	68	return mipi_dsi[handle];
	69	}
	70
	71	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	72	u8 cmd, u8 param)
	73	{
	74	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	75	int cnt = 100;
	76
	77	/* transmit a short packet to LCD panel */
deaba190 MD	78	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	79	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	80
deaba190	81	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	82	udelay(1);
	83
	84	return cnt ? 0 : -ETIMEDOUT;
	85	}
	86
	87	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	88	-EINVAL : (c) - 1)
	89
	90	static int sh_mipi_dcs(int handle, u8 cmd)
	91	{
	92	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	93	if (!mipi)
	94	return -ENODEV;
	95	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	96	}
	97
	98	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	99	{
	100	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	101	if (!mipi)
	102	return -ENODEV;
	103	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	104	param);
	105	}
	106
	107	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	108	{
	109	/*
	110	* enable LCDC data tx, transition to LPS after completion of each HS
	111	* packet
	112	*/
deaba190	113	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	114	}
	115
	116	static void sh_mipi_shutdown(struct platform_device *pdev)
	117	{
	118	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	119
	120	sh_mipi_dsi_enable(mipi, false);
	121	}
	122
c2439398	123	static void mipi_display_on(void arg, struct fb_info info)
9fd04fe3 GL	124	{
	125	struct sh_mipi *mipi = arg;
	126
	127	sh_mipi_dsi_enable(mipi, true);
6722a401 MD	128
	129	if (mipi->next_display_on)
	130	mipi->next_display_on(mipi->next_board_data, info);
9fd04fe3 GL	131	}
	132
	133	static void mipi_display_off(void *arg)
	134	{
	135	struct sh_mipi *mipi = arg;
	136
6722a401 MD	137	if (mipi->next_display_off)
	138	mipi->next_display_off(mipi->next_board_data);
	139
9fd04fe3 GL	140	sh_mipi_dsi_enable(mipi, false);
	141	}
	142
	143	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	144	struct sh_mipi_dsi_info *pdata)
	145	{
	146	void __iomem *base = mipi->base;
	147	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	148	u32 pctype, datatype, pixfmt;
	149	u32 linelength;
	150	bool yuv;
	151
44432407 GL	152	/*
	153	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	154	* the default videomode. If this ever becomes a problem, We'll have to
	155	* move this to mipi_display_on() above and use info->var.xres
	156	*/
9fd04fe3 GL	157	switch (pdata->data_format) {
	158	case MIPI_RGB888:
	159	pctype = 0;
	160	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	161	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	162	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	163	yuv = false;
	164	break;
	165	case MIPI_RGB565:
	166	pctype = 1;
	167	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	168	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	169	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	170	yuv = false;
	171	break;
	172	case MIPI_RGB666_LP:
	173	pctype = 2;
	174	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	175	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	176	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	177	yuv = false;
	178	break;
	179	case MIPI_RGB666:
	180	pctype = 3;
	181	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	182	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	183	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	184	yuv = false;
	185	break;
	186	case MIPI_BGR888:
	187	pctype = 8;
	188	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	189	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	190	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	191	yuv = false;
	192	break;
	193	case MIPI_BGR565:
	194	pctype = 9;
	195	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	196	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	197	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	198	yuv = false;
	199	break;
	200	case MIPI_BGR666_LP:
	201	pctype = 0xa;
	202	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	203	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	204	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	205	yuv = false;
	206	break;
	207	case MIPI_BGR666:
	208	pctype = 0xb;
	209	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	210	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	211	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	212	yuv = false;
	213	break;
	214	case MIPI_YUYV:
	215	pctype = 4;
	216	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	217	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	218	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	219	yuv = true;
	220	break;
	221	case MIPI_UYVY:
	222	pctype = 5;
	223	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	224	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	225	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	226	yuv = true;
	227	break;
	228	case MIPI_YUV420_L:
	229	pctype = 6;
	230	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	231	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
44432407	232	linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
9fd04fe3 GL	233	yuv = true;
	234	break;
	235	case MIPI_YUV420:
	236	pctype = 7;
	237	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	238	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	239	/* Length of U/V line */
44432407	240	linelength = (ch->lcd_cfg[0].xres + 1) / 2;
9fd04fe3 GL	241	yuv = true;
	242	break;
	243	default:
	244	return -EINVAL;
	245	}
	246
	247	if ((yuv && ch->interface_type != YUV422) \|\|
	248	(!yuv && ch->interface_type != RGB24))
	249	return -EINVAL;
	250
	251	/* reset DSI link */
71b146c8	252	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	253	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	254	udelay(50);
71b146c8	255	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	256
	257	/* setup DSI link */
	258
	259	/*
	260	* Default = ULPS enable \|
	261	* Contention detection enabled \|
	262	* EoT packet transmission enable \|
	263	* CRC check enable \|
	264	* ECC check enable
	265	* additionally enable first two lanes
	266	*/
71b146c8	267	iowrite32(0x00003703, base + SYSCONF);
9fd04fe3 GL	268	/*
	269	* T_wakeup = 0x7000
	270	* T_hs-trail = 3
	271	* T_hs-prepare = 3
	272	* T_clk-trail = 3
	273	* T_clk-prepare = 2
	274	*/
71b146c8	275	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	276	/* no responses requested */
71b146c8	277	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	278	/* request response to packets of type 0x28 */
71b146c8	279	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	280	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	281	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	282	/* LP reception timeout, default 0xffffffff */
71b146c8	283	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	284	/* Turn-around timeout, default 0xffffffff */
71b146c8	285	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	286	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	287	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3	288	/* Enable timeout counters */
71b146c8	289	iowrite32(0x00000f00, base + DSICTRL);
9fd04fe3 GL	290	/* Interrupts not used, disable all */
	291	iowrite32(0, base + DSIINTE);
	292	/* DSI-Tx bias on */
71b146c8	293	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3 GL	294	udelay(200);
9fd04fe3 GL	295	/* Deassert resets, power on, set multiplier */
71b146c8	296	iowrite32(0x03070b01, base + PHYCTRL);
9fd04fe3 GL	297
	298	/* setup l-bridge */
	299
	300	/*
	301	* Enable transmission of all packets,
	302	* transmit LPS after each HS packet completion
	303	*/
deaba190	304	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	305	/* VSYNC width = 2 (<< 17) */
deaba190 MD	306	iowrite32(0x00040000 \| (pctype << 12) \| datatype,
deaba190 MD	307	mipi->linkbase + VMCTR1);
9fd04fe3 GL	308	/*
	309	* Non-burst mode with sync pulses: VSE and HSE are output,
	310	* HSA period allowed, no commands in LP
	311	*/
deaba190	312	iowrite32(0x00e00000, mipi->linkbase + VMCTR2);
9fd04fe3 GL	313	/*
9fd04fe3 GL	314	* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
44432407	315	* sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
9fd04fe3 GL	316	* (unused, since VMCTR2[HSABM] = 0)
9fd04fe3 GL	317	*/
deaba190	318	iowrite32(1 \| (linelength << 16), mipi->linkbase + VMLEN1);
9fd04fe3 GL	319
	320	msleep(5);
	321
	322	/* setup LCD panel */
	323
	324	/* cf. drivers/video/omap/lcd_mipid.c */
	325	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	326	msleep(120);
	327	/*
	328	* [7] - Page Address Mode
	329	* [6] - Column Address Mode
	330	* [5] - Page / Column Address Mode
	331	* [4] - Display Device Line Refresh Order
	332	* [3] - RGB/BGR Order
	333	* [2] - Display Data Latch Data Order
	334	* [1] - Flip Horizontal
	335	* [0] - Flip Vertical
	336	*/
	337	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	338	/* cf. set_data_lines() */
	339	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	340	pixfmt << 4);
	341	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	342
	343	return 0;
	344	}
	345
	346	static int __init sh_mipi_probe(struct platform_device *pdev)
	347	{
	348	struct sh_mipi *mipi;
	349	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	350	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	351	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	352	unsigned long rate, f_current;
	353	int idx = pdev->id, ret;
	354	char dsip_clk[] = "dsi.p_clk";
	355
deaba190	356	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	357	return -ENODEV;
	358
	359	mutex_lock(&array_lock);
	360	if (idx < 0)
	361	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	362	;
	363
	364	if (idx == ARRAY_SIZE(mipi_dsi)) {
	365	ret = -EBUSY;
	366	goto efindslot;
	367	}
	368
	369	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	370	if (!mipi) {
	371	ret = -ENOMEM;
	372	goto ealloc;
	373	}
	374
	375	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	376	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	377	ret = -EBUSY;
	378	goto ereqreg;
	379	}
	380
	381	mipi->base = ioremap(res->start, resource_size(res));
	382	if (!mipi->base) {
	383	ret = -ENOMEM;
	384	goto emap;
	385	}
	386
deaba190 MD	387	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	388	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	389	ret = -EBUSY;
	390	goto ereqreg2;
	391	}
	392
	393	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	394	if (!mipi->linkbase) {
	395	ret = -ENOMEM;
	396	goto emap2;
	397	}
	398
9fd04fe3 GL	399	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	400	if (IS_ERR(mipi->dsit_clk)) {
	401	ret = PTR_ERR(mipi->dsit_clk);
	402	goto eclktget;
	403	}
	404
	405	f_current = clk_get_rate(mipi->dsit_clk);
	406	/* 80MHz required by the datasheet */
	407	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	408	if (rate > 0 && rate != f_current)
	409	ret = clk_set_rate(mipi->dsit_clk, rate);
	410	else
	411	ret = rate;
	412	if (ret < 0)
	413	goto esettrate;
	414
	415	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	416
	417	sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
	418	mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
	419	if (IS_ERR(mipi->dsip_clk)) {
	420	ret = PTR_ERR(mipi->dsip_clk);
	421	goto eclkpget;
	422	}
	423
	424	f_current = clk_get_rate(mipi->dsip_clk);
	425	/* Between 10 and 50MHz */
	426	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	427	if (rate > 0 && rate != f_current)
	428	ret = clk_set_rate(mipi->dsip_clk, rate);
	429	else
	430	ret = rate;
	431	if (ret < 0)
	432	goto esetprate;
	433
	434	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
	435
	436	msleep(10);
	437
	438	ret = clk_enable(mipi->dsit_clk);
	439	if (ret < 0)
	440	goto eclkton;
	441
	442	ret = clk_enable(mipi->dsip_clk);
	443	if (ret < 0)
	444	goto eclkpon;
	445
	446	mipi_dsi[idx] = mipi;
	447
	448	ret = sh_mipi_setup(mipi, pdata);
	449	if (ret < 0)
	450	goto emipisetup;
	451
	452	mutex_unlock(&array_lock);
	453	platform_set_drvdata(pdev, mipi);
	454
6722a401 MD	455	/* Save original LCDC callbacks */
	456	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	457	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	458	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
	459
9fd04fe3 GL	460	/* Set up LCDC callbacks */
	461	pdata->lcd_chan->board_cfg.board_data = mipi;
	462	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	463	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
	464
	465	return 0;
	466
	467	emipisetup:
	468	mipi_dsi[idx] = NULL;
	469	clk_disable(mipi->dsip_clk);
	470	eclkpon:
	471	clk_disable(mipi->dsit_clk);
	472	eclkton:
	473	esetprate:
	474	clk_put(mipi->dsip_clk);
	475	eclkpget:
	476	esettrate:
	477	clk_put(mipi->dsit_clk);
	478	eclktget:
deaba190 MD	479	iounmap(mipi->linkbase);
	480	emap2:
	481	release_mem_region(res2->start, resource_size(res2));
	482	ereqreg2:
9fd04fe3 GL	483	iounmap(mipi->base);
	484	emap:
	485	release_mem_region(res->start, resource_size(res));
	486	ereqreg:
	487	kfree(mipi);
	488	ealloc:
	489	efindslot:
	490	mutex_unlock(&array_lock);
	491
	492	return ret;
	493	}
	494
	495	static int __exit sh_mipi_remove(struct platform_device *pdev)
	496	{
	497	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	498	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	499	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	500	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	501	int i, ret;
	502
	503	mutex_lock(&array_lock);
	504
	505	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	506	;
	507
	508	if (i == ARRAY_SIZE(mipi_dsi)) {
	509	ret = -EINVAL;
	510	} else {
	511	ret = 0;
	512	mipi_dsi[i] = NULL;
	513	}
	514
	515	mutex_unlock(&array_lock);
	516
	517	if (ret < 0)
	518	return ret;
	519
	520	pdata->lcd_chan->board_cfg.display_on = NULL;
	521	pdata->lcd_chan->board_cfg.display_off = NULL;
	522	pdata->lcd_chan->board_cfg.board_data = NULL;
	523
	524	clk_disable(mipi->dsip_clk);
	525	clk_disable(mipi->dsit_clk);
	526	clk_put(mipi->dsit_clk);
	527	clk_put(mipi->dsip_clk);
deaba190 MD	528	iounmap(mipi->linkbase);
	529	if (res2)
	530	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	531	iounmap(mipi->base);
	532	if (res)
	533	release_mem_region(res->start, resource_size(res));
	534	platform_set_drvdata(pdev, NULL);
	535	kfree(mipi);
	536
	537	return 0;
	538	}
	539
	540	static struct platform_driver sh_mipi_driver = {
	541	.remove = __exit_p(sh_mipi_remove),
	542	.shutdown = sh_mipi_shutdown,
	543	.driver = {
	544	.name = "sh-mipi-dsi",
	545	},
	546	};
	547
	548	static int __init sh_mipi_init(void)
	549	{
	550	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	551	}
	552	module_init(sh_mipi_init);
	553
	554	static void __exit sh_mipi_exit(void)
	555	{
	556	platform_driver_unregister(&sh_mipi_driver);
	557	}
	558	module_exit(sh_mipi_exit);
	559
	560	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	561	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	562	MODULE_LICENSE("GPL v2");