[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/module.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct clk	*dsip_clk;
	struct device	*dev;

	void	*next_board_data;
	void	(*next_display_on)(void *board_data, struct fb_info *info);
	void	(*next_display_off)(void *board_data);
};

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = platform_get_drvdata(pdev);

	sh_mipi_dsi_enable(mipi, false);
}

static void mipi_display_on(void *arg, struct fb_info *info)
{
	struct sh_mipi *mipi = arg;

	pm_runtime_get_sync(mipi->dev);
	sh_mipi_dsi_enable(mipi, true);

	if (mipi->next_display_on)
		mipi->next_display_on(mipi->next_board_data, info);
}

static void mipi_display_off(void *arg)
{
	struct sh_mipi *mipi = arg;

	if (mipi->next_display_off)
		mipi->next_display_off(mipi->next_board_data);

	sh_mipi_dsi_enable(mipi, false);
	pm_runtime_put(mipi->dev);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
	bool yuv;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_cfg[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 * additionally enable first two lanes
	 */
	iowrite32(0x00003703, base + SYSCONF);
	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on, set multiplier */
	iowrite32(0x03070b01, base + PHYCTRL);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) |
		  (pdata->clksrc << 16) | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);

	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	if (pdata->flags & SH_MIPI_DSI_HSABM)
		vmctr2 |= 1 << 5;
	if (pdata->flags & SH_MIPI_DSI_HBPBM)
		vmctr2 |= 1 << 4;
	iowrite32(vmctr2, mipi->linkbase + VMCTR2);

	/*
	 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
	 * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
	 * (unused if VMCTR2[HSABM] = 0)
	 */
	iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	return 0;
}

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->dev = &pdev->dev;

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	mipi->dsip_clk = clk_get(&pdev->dev, "dsip_clk");
	if (IS_ERR(mipi->dsip_clk)) {
		ret = PTR_ERR(mipi->dsip_clk);
		goto eclkpget;
	}

	f_current = clk_get_rate(mipi->dsip_clk);
	/* Between 10 and 50MHz */
	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsip_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esetprate;

	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);

	msleep(10);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	ret = clk_enable(mipi->dsip_clk);
	if (ret < 0)
		goto eclkpon;

	mipi_dsi[idx] = mipi;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto emipisetup;

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, mipi);

	/* Save original LCDC callbacks */
	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;

	/* Set up LCDC callbacks */
	pdata->lcd_chan->board_cfg.board_data = mipi;
	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;

	return 0;

emipisetup:
	mipi_dsi[idx] = NULL;
	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsip_clk);
eclkpon:
	clk_disable(mipi->dsit_clk);
eclkton:
esetprate:
	clk_put(mipi->dsip_clk);
eclkpget:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pdata->lcd_chan->board_cfg.owner = NULL;
	pdata->lcd_chan->board_cfg.display_on = NULL;
	pdata->lcd_chan->board_cfg.display_off = NULL;
	pdata->lcd_chan->board_cfg.board_data = NULL;

	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsip_clk);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);
	clk_put(mipi->dsip_clk);
	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
	15	#include <linux/platform_device.h>
236782a5	16	#include <linux/pm_runtime.h>
9fd04fe3 GL	17	#include <linux/slab.h>
	18	#include <linux/string.h>
	19	#include <linux/types.h>
355b200b	20	#include <linux/module.h>
9fd04fe3 GL	21
	22	#include <video/mipi_display.h>
	23	#include <video/sh_mipi_dsi.h>
	24	#include <video/sh_mobile_lcdc.h>
	25
71b146c8 MD	26	#define SYSCTRL 0x0000
	27	#define SYSCONF 0x0004
	28	#define TIMSET 0x0008
	29	#define RESREQSET0 0x0018
	30	#define RESREQSET1 0x001c
	31	#define HSTTOVSET 0x0020
	32	#define LPRTOVSET 0x0024
	33	#define TATOVSET 0x0028
	34	#define PRTOVSET 0x002c
	35	#define DSICTRL 0x0030
	36	#define DSIINTE 0x0060
	37	#define PHYCTRL 0x0070
	38
deaba190 MD	39	/* relative to linkbase */
	40	#define DTCTR 0x0000
	41	#define VMCTR1 0x0020
	42	#define VMCTR2 0x0024
	43	#define VMLEN1 0x0028
	44	#define CMTSRTREQ 0x0070
	45	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	46
	47	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	48	#define MAX_SH_MIPI_DSI 2
	49
	50	struct sh_mipi {
	51	void __iomem *base;
deaba190	52	void __iomem *linkbase;
9fd04fe3 GL	53	struct clk *dsit_clk;
9fd04fe3 GL	54	struct clk *dsip_clk;
236782a5 GL	55	struct device *dev;
	56
	57	void *next_board_data;
	58	void (next_display_on)(void board_data, struct fb_info *info);
	59	void (next_display_off)(void board_data);
9fd04fe3 GL	60	};
	61
	62	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	63
	64	/* Protect the above array */
	65	static DEFINE_MUTEX(array_lock);
	66
	67	static struct sh_mipi *sh_mipi_by_handle(int handle)
	68	{
	69	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	70	return NULL;
	71
	72	return mipi_dsi[handle];
	73	}
	74
	75	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	76	u8 cmd, u8 param)
	77	{
	78	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	79	int cnt = 100;
	80
	81	/* transmit a short packet to LCD panel */
deaba190 MD	82	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	83	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	84
deaba190	85	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	86	udelay(1);
	87
	88	return cnt ? 0 : -ETIMEDOUT;
	89	}
	90
	91	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	92	-EINVAL : (c) - 1)
	93
	94	static int sh_mipi_dcs(int handle, u8 cmd)
	95	{
	96	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	97	if (!mipi)
	98	return -ENODEV;
	99	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	100	}
	101
	102	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	103	{
	104	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	105	if (!mipi)
	106	return -ENODEV;
	107	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	108	param);
	109	}
	110
	111	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	112	{
	113	/*
	114	* enable LCDC data tx, transition to LPS after completion of each HS
	115	* packet
	116	*/
deaba190	117	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	118	}
	119
	120	static void sh_mipi_shutdown(struct platform_device *pdev)
	121	{
	122	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	123
	124	sh_mipi_dsi_enable(mipi, false);
	125	}
	126
c2439398	127	static void mipi_display_on(void arg, struct fb_info info)
9fd04fe3 GL	128	{
	129	struct sh_mipi *mipi = arg;
	130
236782a5	131	pm_runtime_get_sync(mipi->dev);
9fd04fe3	132	sh_mipi_dsi_enable(mipi, true);
6722a401 MD	133
	134	if (mipi->next_display_on)
	135	mipi->next_display_on(mipi->next_board_data, info);
9fd04fe3 GL	136	}
	137
	138	static void mipi_display_off(void *arg)
	139	{
	140	struct sh_mipi *mipi = arg;
	141
6722a401 MD	142	if (mipi->next_display_off)
	143	mipi->next_display_off(mipi->next_board_data);
	144
9fd04fe3	145	sh_mipi_dsi_enable(mipi, false);
236782a5	146	pm_runtime_put(mipi->dev);
9fd04fe3 GL	147	}
	148
	149	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	150	struct sh_mipi_dsi_info *pdata)
	151	{
	152	void __iomem *base = mipi->base;
	153	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
14bbb7c6	154	u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
9fd04fe3 GL	155	bool yuv;
9fd04fe3 GL	156
44432407 GL	157	/*
	158	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	159	* the default videomode. If this ever becomes a problem, We'll have to
	160	* move this to mipi_display_on() above and use info->var.xres
	161	*/
9fd04fe3 GL	162	switch (pdata->data_format) {
	163	case MIPI_RGB888:
	164	pctype = 0;
	165	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	166	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	167	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	168	yuv = false;
	169	break;
	170	case MIPI_RGB565:
	171	pctype = 1;
	172	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	173	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	174	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	175	yuv = false;
	176	break;
	177	case MIPI_RGB666_LP:
	178	pctype = 2;
	179	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	180	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	181	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	182	yuv = false;
	183	break;
	184	case MIPI_RGB666:
	185	pctype = 3;
	186	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	187	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	188	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	189	yuv = false;
	190	break;
	191	case MIPI_BGR888:
	192	pctype = 8;
	193	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	194	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	195	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	196	yuv = false;
	197	break;
	198	case MIPI_BGR565:
	199	pctype = 9;
	200	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	201	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	202	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	203	yuv = false;
	204	break;
	205	case MIPI_BGR666_LP:
	206	pctype = 0xa;
	207	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	208	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	209	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	210	yuv = false;
	211	break;
	212	case MIPI_BGR666:
	213	pctype = 0xb;
	214	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	215	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	216	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	217	yuv = false;
	218	break;
	219	case MIPI_YUYV:
	220	pctype = 4;
	221	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	222	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	223	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	224	yuv = true;
	225	break;
	226	case MIPI_UYVY:
	227	pctype = 5;
	228	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	229	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	230	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	231	yuv = true;
	232	break;
	233	case MIPI_YUV420_L:
	234	pctype = 6;
	235	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	236	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
44432407	237	linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
9fd04fe3 GL	238	yuv = true;
	239	break;
	240	case MIPI_YUV420:
	241	pctype = 7;
	242	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	243	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	244	/* Length of U/V line */
44432407	245	linelength = (ch->lcd_cfg[0].xres + 1) / 2;
9fd04fe3 GL	246	yuv = true;
	247	break;
	248	default:
	249	return -EINVAL;
	250	}
	251
	252	if ((yuv && ch->interface_type != YUV422) \|\|
	253	(!yuv && ch->interface_type != RGB24))
	254	return -EINVAL;
	255
	256	/* reset DSI link */
71b146c8	257	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	258	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	259	udelay(50);
71b146c8	260	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	261
	262	/* setup DSI link */
	263
	264	/*
	265	* Default = ULPS enable \|
	266	* Contention detection enabled \|
	267	* EoT packet transmission enable \|
	268	* CRC check enable \|
	269	* ECC check enable
	270	* additionally enable first two lanes
	271	*/
71b146c8	272	iowrite32(0x00003703, base + SYSCONF);
9fd04fe3 GL	273	/*
	274	* T_wakeup = 0x7000
	275	* T_hs-trail = 3
	276	* T_hs-prepare = 3
	277	* T_clk-trail = 3
	278	* T_clk-prepare = 2
	279	*/
71b146c8	280	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	281	/* no responses requested */
71b146c8	282	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	283	/* request response to packets of type 0x28 */
71b146c8	284	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	285	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	286	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	287	/* LP reception timeout, default 0xffffffff */
71b146c8	288	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	289	/* Turn-around timeout, default 0xffffffff */
71b146c8	290	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	291	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	292	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3	293	/* Enable timeout counters */
71b146c8	294	iowrite32(0x00000f00, base + DSICTRL);
9fd04fe3 GL	295	/* Interrupts not used, disable all */
	296	iowrite32(0, base + DSIINTE);
	297	/* DSI-Tx bias on */
71b146c8	298	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3 GL	299	udelay(200);
9fd04fe3 GL	300	/* Deassert resets, power on, set multiplier */
71b146c8	301	iowrite32(0x03070b01, base + PHYCTRL);
9fd04fe3 GL	302
	303	/* setup l-bridge */
	304
	305	/*
	306	* Enable transmission of all packets,
	307	* transmit LPS after each HS packet completion
	308	*/
deaba190	309	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	310	/* VSYNC width = 2 (<< 17) */
14bbb7c6 GL	311	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) \|
14bbb7c6 GL	312	(pdata->clksrc << 16) \| (pctype << 12) \| datatype,
deaba190	313	mipi->linkbase + VMCTR1);
14bbb7c6	314
9fd04fe3 GL	315	/*
	316	* Non-burst mode with sync pulses: VSE and HSE are output,
	317	* HSA period allowed, no commands in LP
	318	*/
14bbb7c6	319	if (pdata->flags & SH_MIPI_DSI_HSABM)
3c2a6599	320	vmctr2 \|= 1 << 5;
32ba95c6	321	if (pdata->flags & SH_MIPI_DSI_HBPBM)
3c2a6599	322	vmctr2 \|= 1 << 4;
14bbb7c6 GL	323	iowrite32(vmctr2, mipi->linkbase + VMCTR2);
14bbb7c6 GL	324
9fd04fe3 GL	325	/*
9fd04fe3 GL	326	* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
44432407	327	* sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
14bbb7c6	328	* (unused if VMCTR2[HSABM] = 0)
9fd04fe3	329	*/
deaba190	330	iowrite32(1 \| (linelength << 16), mipi->linkbase + VMLEN1);
9fd04fe3 GL	331
	332	msleep(5);
	333
	334	/* setup LCD panel */
	335
	336	/* cf. drivers/video/omap/lcd_mipid.c */
	337	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	338	msleep(120);
	339	/*
	340	* [7] - Page Address Mode
	341	* [6] - Column Address Mode
	342	* [5] - Page / Column Address Mode
	343	* [4] - Display Device Line Refresh Order
	344	* [3] - RGB/BGR Order
	345	* [2] - Display Data Latch Data Order
	346	* [1] - Flip Horizontal
	347	* [0] - Flip Vertical
	348	*/
	349	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	350	/* cf. set_data_lines() */
	351	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	352	pixfmt << 4);
	353	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	354
	355	return 0;
	356	}
	357
	358	static int __init sh_mipi_probe(struct platform_device *pdev)
	359	{
	360	struct sh_mipi *mipi;
	361	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	362	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	363	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	364	unsigned long rate, f_current;
9fd04fe3 GL	365	int idx = pdev->id, ret;
9fd04fe3	366
deaba190	367	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	368	return -ENODEV;
	369
	370	mutex_lock(&array_lock);
	371	if (idx < 0)
	372	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	373	;
	374
	375	if (idx == ARRAY_SIZE(mipi_dsi)) {
	376	ret = -EBUSY;
	377	goto efindslot;
	378	}
	379
	380	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	381	if (!mipi) {
	382	ret = -ENOMEM;
	383	goto ealloc;
	384	}
	385
	386	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	387	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	388	ret = -EBUSY;
	389	goto ereqreg;
	390	}
	391
	392	mipi->base = ioremap(res->start, resource_size(res));
	393	if (!mipi->base) {
	394	ret = -ENOMEM;
	395	goto emap;
	396	}
	397
deaba190 MD	398	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	399	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	400	ret = -EBUSY;
	401	goto ereqreg2;
	402	}
	403
	404	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	405	if (!mipi->linkbase) {
	406	ret = -ENOMEM;
	407	goto emap2;
	408	}
	409
236782a5 GL	410	mipi->dev = &pdev->dev;
236782a5 GL	411
9fd04fe3 GL	412	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	413	if (IS_ERR(mipi->dsit_clk)) {
	414	ret = PTR_ERR(mipi->dsit_clk);
	415	goto eclktget;
	416	}
	417
	418	f_current = clk_get_rate(mipi->dsit_clk);
	419	/* 80MHz required by the datasheet */
	420	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	421	if (rate > 0 && rate != f_current)
	422	ret = clk_set_rate(mipi->dsit_clk, rate);
	423	else
	424	ret = rate;
	425	if (ret < 0)
	426	goto esettrate;
	427
	428	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	429
9250741e	430	mipi->dsip_clk = clk_get(&pdev->dev, "dsip_clk");
9fd04fe3 GL	431	if (IS_ERR(mipi->dsip_clk)) {
	432	ret = PTR_ERR(mipi->dsip_clk);
	433	goto eclkpget;
	434	}
	435
	436	f_current = clk_get_rate(mipi->dsip_clk);
	437	/* Between 10 and 50MHz */
	438	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	439	if (rate > 0 && rate != f_current)
	440	ret = clk_set_rate(mipi->dsip_clk, rate);
	441	else
	442	ret = rate;
	443	if (ret < 0)
	444	goto esetprate;
	445
	446	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
	447
	448	msleep(10);
	449
	450	ret = clk_enable(mipi->dsit_clk);
	451	if (ret < 0)
	452	goto eclkton;
	453
	454	ret = clk_enable(mipi->dsip_clk);
	455	if (ret < 0)
	456	goto eclkpon;
	457
	458	mipi_dsi[idx] = mipi;
	459
236782a5 GL	460	pm_runtime_enable(&pdev->dev);
	461	pm_runtime_resume(&pdev->dev);
	462
9fd04fe3 GL	463	ret = sh_mipi_setup(mipi, pdata);
	464	if (ret < 0)
	465	goto emipisetup;
	466
	467	mutex_unlock(&array_lock);
	468	platform_set_drvdata(pdev, mipi);
	469
6722a401 MD	470	/* Save original LCDC callbacks */
	471	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	472	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	473	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
	474
9fd04fe3 GL	475	/* Set up LCDC callbacks */
	476	pdata->lcd_chan->board_cfg.board_data = mipi;
	477	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	478	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
236782a5	479	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;
9fd04fe3 GL	480
	481	return 0;
	482
	483	emipisetup:
	484	mipi_dsi[idx] = NULL;
236782a5	485	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	486	clk_disable(mipi->dsip_clk);
	487	eclkpon:
	488	clk_disable(mipi->dsit_clk);
	489	eclkton:
	490	esetprate:
	491	clk_put(mipi->dsip_clk);
	492	eclkpget:
	493	esettrate:
	494	clk_put(mipi->dsit_clk);
	495	eclktget:
deaba190 MD	496	iounmap(mipi->linkbase);
	497	emap2:
	498	release_mem_region(res2->start, resource_size(res2));
	499	ereqreg2:
9fd04fe3 GL	500	iounmap(mipi->base);
	501	emap:
	502	release_mem_region(res->start, resource_size(res));
	503	ereqreg:
	504	kfree(mipi);
	505	ealloc:
	506	efindslot:
	507	mutex_unlock(&array_lock);
	508
	509	return ret;
	510	}
	511
	512	static int __exit sh_mipi_remove(struct platform_device *pdev)
	513	{
	514	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	515	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	516	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	517	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	518	int i, ret;
	519
	520	mutex_lock(&array_lock);
	521
	522	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	523	;
	524
	525	if (i == ARRAY_SIZE(mipi_dsi)) {
	526	ret = -EINVAL;
	527	} else {
	528	ret = 0;
	529	mipi_dsi[i] = NULL;
	530	}
	531
	532	mutex_unlock(&array_lock);
	533
	534	if (ret < 0)
	535	return ret;
	536
236782a5	537	pdata->lcd_chan->board_cfg.owner = NULL;
9fd04fe3 GL	538	pdata->lcd_chan->board_cfg.display_on = NULL;
	539	pdata->lcd_chan->board_cfg.display_off = NULL;
	540	pdata->lcd_chan->board_cfg.board_data = NULL;
	541
236782a5	542	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	543	clk_disable(mipi->dsip_clk);
	544	clk_disable(mipi->dsit_clk);
	545	clk_put(mipi->dsit_clk);
	546	clk_put(mipi->dsip_clk);
deaba190 MD	547	iounmap(mipi->linkbase);
	548	if (res2)
	549	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	550	iounmap(mipi->base);
	551	if (res)
	552	release_mem_region(res->start, resource_size(res));
	553	platform_set_drvdata(pdev, NULL);
	554	kfree(mipi);
	555
	556	return 0;
	557	}
	558
	559	static struct platform_driver sh_mipi_driver = {
	560	.remove = __exit_p(sh_mipi_remove),
	561	.shutdown = sh_mipi_shutdown,
	562	.driver = {
	563	.name = "sh-mipi-dsi",
	564	},
	565	};
	566
	567	static int __init sh_mipi_init(void)
	568	{
	569	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	570	}
	571	module_init(sh_mipi_init);
	572
	573	static void __exit sh_mipi_exit(void)
	574	{
	575	platform_driver_unregister(&sh_mipi_driver);
	576	}
	577	module_exit(sh_mipi_exit);
	578
	579	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	580	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	581	MODULE_LICENSE("GPL v2");