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s3fb: add DDC support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / s3fb.c
CommitLineData
a268422d
OZ		 1/*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
a268422d
OZ		 14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
a268422d
OZ		 20#include <linux/delay.h>
21#include <linux/fb.h>
22#include <linux/svga.h>
23#include <linux/init.h>
24#include <linux/pci.h>
ac751efa 25#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
a268422d
OZ		 26#include <video/vga.h>
27
86c0f043
OZ		 28#include <linux/i2c.h>
29#include <linux/i2c-algo-bit.h>
30
a268422d
OZ		 31#ifdef CONFIG_MTRR
32#include <asm/mtrr.h>
33#endif
34
35struct s3fb_info {
36 int chip, rev, mclk_freq;
37 int mtrr_reg;
38 struct vgastate state;
39 struct mutex open_lock;
40 unsigned int ref_count;
41 u32 pseudo_palette[16];
86c0f043
OZ		 42#ifdef CONFIG_FB_S3_DDC
43 u8 __iomem *mmio;
44 bool ddc_registered;
45 struct i2c_adapter ddc_adapter;
46 struct i2c_algo_bit_data ddc_algo;
47#endif
a268422d
OZ		 48};
49
50
51/* ------------------------------------------------------------------------- */
52
53static const struct svga_fb_format s3fb_formats[] = {
54 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
55 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 56 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
a268422d 57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 58 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
a268422d 59 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
c26d7b29 60 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
a268422d
OZ		 61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
62 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
63 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
64 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
65 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
66 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
67 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
68 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
69 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
70 SVGA_FORMAT_END
71};
72
73
74static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
249bdbbf 75 35000, 240000, 14318};
5694f9ce
OZ		 76static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
77 230000, 460000, 14318};
a268422d
OZ		 78
79static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
80
81static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
82 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
94e948e6 83 "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
a268422d 84 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
94e948e6 85 "S3 Virge/GX2", "S3 Virge/GX2+", "",
5694f9ce
OZ		 86 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
87 "S3 Trio3D"};
a268422d
OZ		 88
89#define CHIP_UNKNOWN 0x00
90#define CHIP_732_TRIO32 0x01
91#define CHIP_764_TRIO64 0x02
92#define CHIP_765_TRIO64VP 0x03
93#define CHIP_767_TRIO64UVP 0x04
94#define CHIP_775_TRIO64V2_DX 0x05
95#define CHIP_785_TRIO64V2_GX 0x06
96#define CHIP_551_PLATO_PX 0x07
97#define CHIP_M65_AURORA64VP 0x08
98#define CHIP_325_VIRGE 0x09
99#define CHIP_988_VIRGE_VX 0x0A
100#define CHIP_375_VIRGE_DX 0x0B
101#define CHIP_385_VIRGE_GX 0x0C
94e948e6
OZ		 102#define CHIP_357_VIRGE_GX2 0x0D
103#define CHIP_359_VIRGE_GX2P 0x0E
9966c4fe
OZ		 104#define CHIP_360_TRIO3D_1X 0x10
105#define CHIP_362_TRIO3D_2X 0x11
106#define CHIP_368_TRIO3D_2X 0x12
5694f9ce 107#define CHIP_365_TRIO3D 0x13
a268422d
OZ		 108
109#define CHIP_XXX_TRIO 0x80
110#define CHIP_XXX_TRIO64V2_DXGX 0x81
111#define CHIP_XXX_VIRGE_DXGX 0x82
9966c4fe 112#define CHIP_36X_TRIO3D_1X_2X 0x83
a268422d
OZ		 113
114#define CHIP_UNDECIDED_FLAG 0x80
115#define CHIP_MASK 0xFF
116
86c0f043
OZ		 117#define MMIO_OFFSET 0x1000000
118#define MMIO_SIZE 0x10000
119
a268422d
OZ		 120/* CRT timing register sets */
121
122static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
123static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
124static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
125static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
126static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
127static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
128
129static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
130static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
131static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
132static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
133static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
134static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
135
136static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
7fe029df 137static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
a268422d
OZ		 138static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
139
cb11c048
OZ		 140static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
141
a268422d
OZ		 142static const struct svga_timing_regs s3_timing_regs = {
143 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
144 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
145 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
146 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
147};
148
149
150/* ------------------------------------------------------------------------- */
151
152/* Module parameters */
153
154
86c0f043 155static char *mode_option __devinitdata;
a268422d
OZ		 156
157#ifdef CONFIG_MTRR
a8140543 158static int mtrr __devinitdata = 1;
a268422d
OZ		 159#endif
160
161static int fasttext = 1;
162
163
164MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
165MODULE_LICENSE("GPL");
166MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
167
a8140543
KH		 168module_param(mode_option, charp, 0444);
169MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
170module_param_named(mode, mode_option, charp, 0444);
171MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
a268422d
OZ		 172
173#ifdef CONFIG_MTRR
174module_param(mtrr, int, 0444);
175MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
176#endif
177
178module_param(fasttext, int, 0644);
179MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
180
181
86c0f043
OZ		 182/* ------------------------------------------------------------------------- */
183
184#ifdef CONFIG_FB_S3_DDC
185
186#define DDC_REG 0xaa /* Trio 3D/1X/2X */
187#define DDC_MMIO_REG 0xff20 /* all other chips */
188#define DDC_SCL_OUT (1 << 0)
189#define DDC_SDA_OUT (1 << 1)
190#define DDC_SCL_IN (1 << 2)
191#define DDC_SDA_IN (1 << 3)
192#define DDC_DRIVE_EN (1 << 4)
193
194static bool s3fb_ddc_needs_mmio(int chip)
195{
196 return !(chip == CHIP_360_TRIO3D_1X ||
197 chip == CHIP_362_TRIO3D_2X ||
198 chip == CHIP_368_TRIO3D_2X);
199}
200
201static u8 s3fb_ddc_read(struct s3fb_info *par)
202{
203 if (s3fb_ddc_needs_mmio(par->chip))
204 return readb(par->mmio + DDC_MMIO_REG);
205 else
206 return vga_rcrt(par->state.vgabase, DDC_REG);
207}
208
209static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
210{
211 if (s3fb_ddc_needs_mmio(par->chip))
212 writeb(val, par->mmio + DDC_MMIO_REG);
213 else
214 vga_wcrt(par->state.vgabase, DDC_REG, val);
215}
216
217static void s3fb_ddc_setscl(void *data, int val)
218{
219 struct s3fb_info *par = data;
220 unsigned char reg;
221
222 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
223 if (val)
224 reg |= DDC_SCL_OUT;
225 else
226 reg &= ~DDC_SCL_OUT;
227 s3fb_ddc_write(par, reg);
228}
229
230static void s3fb_ddc_setsda(void *data, int val)
231{
232 struct s3fb_info *par = data;
233 unsigned char reg;
234
235 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
236 if (val)
237 reg |= DDC_SDA_OUT;
238 else
239 reg &= ~DDC_SDA_OUT;
240 s3fb_ddc_write(par, reg);
241}
242
243static int s3fb_ddc_getscl(void *data)
244{
245 struct s3fb_info *par = data;
246
247 return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
248}
249
250static int s3fb_ddc_getsda(void *data)
251{
252 struct s3fb_info *par = data;
253
254 return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
255}
256
257static int __devinit s3fb_setup_ddc_bus(struct fb_info *info)
258{
259 struct s3fb_info *par = info->par;
260
261 strlcpy(par->ddc_adapter.name, info->fix.id,
262 sizeof(par->ddc_adapter.name));
263 par->ddc_adapter.owner = THIS_MODULE;
264 par->ddc_adapter.class = I2C_CLASS_DDC;
265 par->ddc_adapter.algo_data = &par->ddc_algo;
266 par->ddc_adapter.dev.parent = info->device;
267 par->ddc_algo.setsda = s3fb_ddc_setsda;
268 par->ddc_algo.setscl = s3fb_ddc_setscl;
269 par->ddc_algo.getsda = s3fb_ddc_getsda;
270 par->ddc_algo.getscl = s3fb_ddc_getscl;
271 par->ddc_algo.udelay = 10;
272 par->ddc_algo.timeout = 20;
273 par->ddc_algo.data = par;
274
275 i2c_set_adapdata(&par->ddc_adapter, par);
276
277 /*
278 * some Virge cards have external MUX to switch chip I2C bus between
279 * DDC and extension pins - switch it do DDC
280 */
281/* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
282 if (par->chip == CHIP_357_VIRGE_GX2 ||
283 par->chip == CHIP_359_VIRGE_GX2P)
284 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
285 else
286 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
287 /* some Virge need this or the DDC is ignored */
288 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
289
290 return i2c_bit_add_bus(&par->ddc_adapter);
291}
292#endif /* CONFIG_FB_S3_DDC */
293
294
a268422d
OZ		 295/* ------------------------------------------------------------------------- */
296
297/* Set font in S3 fast text mode */
298
299static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
300{
301 const u8 *font = map->data;
75814d87 302 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
a268422d
OZ		 303 int i, c;
304
305 if ((map->width != 8) || (map->height != 16) ||
306 (map->depth != 1) || (map->length != 256)) {
307 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
308 info->node, map->width, map->height, map->depth, map->length);
309 return;
310 }
311
312 fb += 2;
313 for (i = 0; i < map->height; i++) {
314 for (c = 0; c < map->length; c++) {
75814d87 315 fb_writeb(font[c * map->height + i], fb + c * 4);
a268422d
OZ		 316 }
317 fb += 1024;
318 }
319}
320
55db0923
DM		 321static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
322{
323 struct s3fb_info *par = info->par;
324
325 svga_tilecursor(par->state.vgabase, info, cursor);
326}
327
a268422d
OZ		 328static struct fb_tile_ops s3fb_tile_ops = {
329 .fb_settile = svga_settile,
330 .fb_tilecopy = svga_tilecopy,
331 .fb_tilefill = svga_tilefill,
332 .fb_tileblit = svga_tileblit,
55db0923 333 .fb_tilecursor = s3fb_tilecursor,
34ed25f5 334 .fb_get_tilemax = svga_get_tilemax,
a268422d
OZ		 335};
336
337static struct fb_tile_ops s3fb_fast_tile_ops = {
338 .fb_settile = s3fb_settile_fast,
339 .fb_tilecopy = svga_tilecopy,
340 .fb_tilefill = svga_tilefill,
341 .fb_tileblit = svga_tileblit,
55db0923 342 .fb_tilecursor = s3fb_tilecursor,
34ed25f5 343 .fb_get_tilemax = svga_get_tilemax,
a268422d
OZ		 344};
345
346
347/* ------------------------------------------------------------------------- */
348
349/* image data is MSB-first, fb structure is MSB-first too */
350static inline u32 expand_color(u32 c)
351{
352 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
353}
354
355/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
356static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
357{
358 u32 fg = expand_color(image->fg_color);
359 u32 bg = expand_color(image->bg_color);
360 const u8 *src1, *src;
361 u8 __iomem *dst1;
362 u32 __iomem *dst;
363 u32 val;
364 int x, y;
365
366 src1 = image->data;
367 dst1 = info->screen_base + (image->dy * info->fix.line_length)
368 + ((image->dx / 8) * 4);
369
370 for (y = 0; y < image->height; y++) {
371 src = src1;
372 dst = (u32 __iomem *) dst1;
373 for (x = 0; x < image->width; x += 8) {
374 val = *(src++) * 0x01010101;
375 val = (val & fg) | (~val & bg);
376 fb_writel(val, dst++);
377 }
378 src1 += image->width / 8;
379 dst1 += info->fix.line_length;
380 }
381
382}
383
384/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
385static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
386{
387 u32 fg = expand_color(rect->color);
388 u8 __iomem *dst1;
389 u32 __iomem *dst;
390 int x, y;
391
392 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
393 + ((rect->dx / 8) * 4);
394
395 for (y = 0; y < rect->height; y++) {
396 dst = (u32 __iomem *) dst1;
397 for (x = 0; x < rect->width; x += 8) {
398 fb_writel(fg, dst++);
399 }
400 dst1 += info->fix.line_length;
401 }
402}
403
404
405/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
406static inline u32 expand_pixel(u32 c)
407{
408 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
409 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
410}
411
412/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
413static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
414{
415 u32 fg = image->fg_color * 0x11111111;
416 u32 bg = image->bg_color * 0x11111111;
417 const u8 *src1, *src;
418 u8 __iomem *dst1;
419 u32 __iomem *dst;
420 u32 val;
421 int x, y;
422
423 src1 = image->data;
424 dst1 = info->screen_base + (image->dy * info->fix.line_length)
425 + ((image->dx / 8) * 4);
426
427 for (y = 0; y < image->height; y++) {
428 src = src1;
429 dst = (u32 __iomem *) dst1;
430 for (x = 0; x < image->width; x += 8) {
431 val = expand_pixel(*(src++));
432 val = (val & fg) | (~val & bg);
433 fb_writel(val, dst++);
434 }
435 src1 += image->width / 8;
436 dst1 += info->fix.line_length;
437 }
438}
439
440static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
441{
442 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
443 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
444 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
445 s3fb_iplan_imageblit(info, image);
446 else
447 s3fb_cfb4_imageblit(info, image);
448 } else
449 cfb_imageblit(info, image);
450}
451
452static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
453{
454 if ((info->var.bits_per_pixel == 4)
455 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
456 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
457 s3fb_iplan_fillrect(info, rect);
458 else
459 cfb_fillrect(info, rect);
460}
461
462
463
464/* ------------------------------------------------------------------------- */
465
466
467static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
468{
9966c4fe 469 struct s3fb_info *par = info->par;
a268422d
OZ		 470 u16 m, n, r;
471 u8 regval;
249bdbbf 472 int rv;
a268422d 473
5694f9ce
OZ		 474 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
475 1000000000 / pixclock, &m, &n, &r, info->node);
249bdbbf
OZ		 476 if (rv < 0) {
477 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
478 return;
479 }
a268422d
OZ		 480
481 /* Set VGA misc register */
f8645933
DM		 482 regval = vga_r(par->state.vgabase, VGA_MIS_R);
483 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
a268422d
OZ		 484
485 /* Set S3 clock registers */
94e948e6
OZ		 486 if (par->chip == CHIP_357_VIRGE_GX2 ||
487 par->chip == CHIP_359_VIRGE_GX2P ||
488 par->chip == CHIP_360_TRIO3D_1X ||
9966c4fe
OZ		 489 par->chip == CHIP_362_TRIO3D_2X ||
490 par->chip == CHIP_368_TRIO3D_2X) {
f8645933
DM		 491 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
492 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
9966c4fe 493 } else
f8645933
DM		 494 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
495 vga_wseq(par->state.vgabase, 0x13, m - 2);
a268422d
OZ		 496
497 udelay(1000);
498
499 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
f8645933
DM		 500 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
501 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
502 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
503 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
a268422d
OZ		 504}
505
506
507/* Open framebuffer */
508
509static int s3fb_open(struct fb_info *info, int user)
510{
511 struct s3fb_info *par = info->par;
512
513 mutex_lock(&(par->open_lock));
514 if (par->ref_count == 0) {
3ff259f2
DM		 515 void __iomem *vgabase = par->state.vgabase;
516
a268422d 517 memset(&(par->state), 0, sizeof(struct vgastate));
3ff259f2 518 par->state.vgabase = vgabase;
a268422d
OZ		 519 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
520 par->state.num_crtc = 0x70;
521 par->state.num_seq = 0x20;
522 save_vga(&(par->state));
523 }
524
525 par->ref_count++;
526 mutex_unlock(&(par->open_lock));
527
528 return 0;
529}
530
531/* Close framebuffer */
532
533static int s3fb_release(struct fb_info *info, int user)
534{
535 struct s3fb_info *par = info->par;
536
537 mutex_lock(&(par->open_lock));
538 if (par->ref_count == 0) {
539 mutex_unlock(&(par->open_lock));
540 return -EINVAL;
541 }
542
543 if (par->ref_count == 1)
544 restore_vga(&(par->state));
545
546 par->ref_count--;
547 mutex_unlock(&(par->open_lock));
548
549 return 0;
550}
551
552/* Validate passed in var */
553
554static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
555{
556 struct s3fb_info *par = info->par;
557 int rv, mem, step;
c3ca34f9 558 u16 m, n, r;
a268422d
OZ		 559
560 /* Find appropriate format */
561 rv = svga_match_format (s3fb_formats, var, NULL);
d4b766a0
OZ		 562
563 /* 32bpp mode is not supported on VIRGE VX,
564 24bpp is not supported on others */
565 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
566 rv = -EINVAL;
567
568 if (rv < 0) {
a268422d
OZ		 569 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
570 return rv;
571 }
572
573 /* Do not allow to have real resoulution larger than virtual */
574 if (var->xres > var->xres_virtual)
575 var->xres_virtual = var->xres;
576
577 if (var->yres > var->yres_virtual)
578 var->yres_virtual = var->yres;
579
580 /* Round up xres_virtual to have proper alignment of lines */
581 step = s3fb_formats[rv].xresstep - 1;
582 var->xres_virtual = (var->xres_virtual+step) & ~step;
583
584 /* Check whether have enough memory */
585 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
c3ca34f9 586 if (mem > info->screen_size) {
a268422d
OZ		 587 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
588 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
589 return -EINVAL;
590 }
591
592 rv = svga_check_timings (&s3_timing_regs, var, info->node);
c3ca34f9 593 if (rv < 0) {
a268422d
OZ		 594 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
595 return rv;
596 }
597
c3ca34f9
KH		 598 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
599 info->node);
600 if (rv < 0) {
601 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
602 info->node);
603 return rv;
604 }
605
a268422d
OZ		 606 return 0;
607}
608
609/* Set video mode from par */
610
611static int s3fb_set_par(struct fb_info *info)
612{
613 struct s3fb_info *par = info->par;
9966c4fe 614 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
a268422d 615 u32 bpp = info->var.bits_per_pixel;
cb11c048 616 u32 htotal, hsstart;
a268422d
OZ		 617
618 if (bpp != 0) {
619 info->fix.ypanstep = 1;
620 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
621
622 info->flags &= ~FBINFO_MISC_TILEBLITTING;
623 info->tileops = NULL;
624
34ed25f5
OZ		 625 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
626 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
8db51668 627 info->pixmap.blit_y = ~(u32)0;
34ed25f5 628
a268422d
OZ		 629 offset_value = (info->var.xres_virtual * bpp) / 64;
630 screen_size = info->var.yres_virtual * info->fix.line_length;
631 } else {
632 info->fix.ypanstep = 16;
633 info->fix.line_length = 0;
634
635 info->flags |= FBINFO_MISC_TILEBLITTING;
636 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
34ed25f5 637
8db51668
AD		 638 /* supports 8x16 tiles only */
639 info->pixmap.blit_x = 1 << (8 - 1);
640 info->pixmap.blit_y = 1 << (16 - 1);
a268422d
OZ		 641
642 offset_value = info->var.xres_virtual / 16;
643 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
644 }
645
646 info->var.xoffset = 0;
647 info->var.yoffset = 0;
648 info->var.activate = FB_ACTIVATE_NOW;
649
650 /* Unlock registers */
f8645933
DM		 651 vga_wcrt(par->state.vgabase, 0x38, 0x48);
652 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
653 vga_wseq(par->state.vgabase, 0x08, 0x06);
ea770789 654 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
a268422d
OZ		 655
656 /* Blank screen and turn off sync */
d907ec04 657 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
ea770789 658 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
a268422d
OZ		 659
660 /* Set default values */
e2fade2c 661 svga_set_default_gfx_regs(par->state.vgabase);
f51a14dd 662 svga_set_default_atc_regs(par->state.vgabase);
a4ade839 663 svga_set_default_seq_regs(par->state.vgabase);
1d28fcad 664 svga_set_default_crt_regs(par->state.vgabase);
21da386d
DM		 665 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
666 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
a268422d
OZ		 667
668 /* S3 specific initialization */
ea770789
DM		 669 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
670 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
a268422d 671
ea770789
DM		 672/* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
673/* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
674 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
675 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
a268422d 676
ea770789 677 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
a268422d 678
ea770789 679/* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
a268422d 680
ea770789
DM		 681/* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
682/* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
a268422d
OZ		 683
684
685 /* Set the offset register */
686 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
21da386d 687 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
a268422d 688
94e948e6
OZ		 689 if (par->chip != CHIP_357_VIRGE_GX2 &&
690 par->chip != CHIP_359_VIRGE_GX2P &&
691 par->chip != CHIP_360_TRIO3D_1X &&
9966c4fe
OZ		 692 par->chip != CHIP_362_TRIO3D_2X &&
693 par->chip != CHIP_368_TRIO3D_2X) {
f8645933
DM		 694 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
695 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
696 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
697 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
9966c4fe 698 }
a268422d 699
f8645933 700 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
f6b0cc47 701 svga_wattr(par->state.vgabase, 0x33, 0x00);
a268422d
OZ		 702
703 if (info->var.vmode & FB_VMODE_DOUBLE)
ea770789 704 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
a268422d 705 else
ea770789 706 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
a268422d
OZ		 707
708 if (info->var.vmode & FB_VMODE_INTERLACED)
ea770789 709 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
a268422d 710 else
ea770789 711 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
a268422d
OZ		 712
713 /* Disable hardware graphics cursor */
ea770789 714 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
a268422d 715 /* Disable Streams engine */
ea770789 716 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
a268422d
OZ		 717
718 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
719
720 /* S3 virge DX hack */
721 if (par->chip == CHIP_375_VIRGE_DX) {
f8645933
DM		 722 vga_wcrt(par->state.vgabase, 0x86, 0x80);
723 vga_wcrt(par->state.vgabase, 0x90, 0x00);
a268422d
OZ		 724 }
725
726 /* S3 virge VX hack */
727 if (par->chip == CHIP_988_VIRGE_VX) {
f8645933
DM		 728 vga_wcrt(par->state.vgabase, 0x50, 0x00);
729 vga_wcrt(par->state.vgabase, 0x67, 0x50);
a268422d 730
f8645933
DM		 731 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
732 vga_wcrt(par->state.vgabase, 0x66, 0x90);
a268422d
OZ		 733 }
734
94e948e6
OZ		 735 if (par->chip == CHIP_357_VIRGE_GX2 ||
736 par->chip == CHIP_359_VIRGE_GX2P ||
737 par->chip == CHIP_360_TRIO3D_1X ||
9966c4fe 738 par->chip == CHIP_362_TRIO3D_2X ||
5694f9ce 739 par->chip == CHIP_368_TRIO3D_2X ||
cb11c048
OZ		 740 par->chip == CHIP_365_TRIO3D ||
741 par->chip == CHIP_375_VIRGE_DX ||
742 par->chip == CHIP_385_VIRGE_GX) {
9966c4fe 743 dbytes = info->var.xres * ((bpp+7)/8);
f8645933
DM		 744 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
745 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
9966c4fe 746
f8645933 747 vga_wcrt(par->state.vgabase, 0x66, 0x81);
9966c4fe
OZ		 748 }
749
94e948e6 750 if (par->chip == CHIP_357_VIRGE_GX2 ||
cb11c048
OZ		 751 par->chip == CHIP_359_VIRGE_GX2P ||
752 par->chip == CHIP_360_TRIO3D_1X ||
753 par->chip == CHIP_362_TRIO3D_2X ||
754 par->chip == CHIP_368_TRIO3D_2X)
755 vga_wcrt(par->state.vgabase, 0x34, 0x00);
756 else /* enable Data Transfer Position Control (DTPC) */
757 vga_wcrt(par->state.vgabase, 0x34, 0x10);
758
ea770789 759 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
a268422d
OZ		 760 multiplex = 0;
761 hmul = 1;
762
763 /* Set mode-specific register values */
764 switch (mode) {
765 case 0:
766 pr_debug("fb%d: text mode\n", info->node);
9c96394b 767 svga_set_textmode_vga_regs(par->state.vgabase);
a268422d
OZ		 768
769 /* Set additional registers like in 8-bit mode */
ea770789
DM		 770 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
771 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 772
773 /* Disable enhanced mode */
ea770789 774 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 775
776 if (fasttext) {
777 pr_debug("fb%d: high speed text mode set\n", info->node);
ea770789 778 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
a268422d
OZ		 779 }
780 break;
781 case 1:
782 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
f8645933 783 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
a268422d
OZ		 784
785 /* Set additional registers like in 8-bit mode */
ea770789
DM		 786 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
787 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 788
789 /* disable enhanced mode */
ea770789 790 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 791 break;
792 case 2:
793 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
794
795 /* Set additional registers like in 8-bit mode */
ea770789
DM		 796 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
797 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
a268422d
OZ		 798
799 /* disable enhanced mode */
ea770789 800 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
a268422d
OZ		 801 break;
802 case 3:
803 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
ea770789 804 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
9966c4fe 805 if (info->var.pixclock > 20000 ||
94e948e6
OZ		 806 par->chip == CHIP_357_VIRGE_GX2 ||
807 par->chip == CHIP_359_VIRGE_GX2P ||
9966c4fe
OZ		 808 par->chip == CHIP_360_TRIO3D_1X ||
809 par->chip == CHIP_362_TRIO3D_2X ||
810 par->chip == CHIP_368_TRIO3D_2X)
ea770789 811 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
9966c4fe 812 else {
ea770789 813 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
a268422d
OZ		 814 multiplex = 1;
815 }
816 break;
817 case 4:
818 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
819 if (par->chip == CHIP_988_VIRGE_VX) {
820 if (info->var.pixclock > 20000)
ea770789 821 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
a268422d 822 else
ea770789 823 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
3827d10e
OZ		 824 } else if (par->chip == CHIP_365_TRIO3D) {
825 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
826 if (info->var.pixclock > 8695) {
827 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
828 hmul = 2;
829 } else {
830 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
831 multiplex = 1;
832 }
a268422d 833 } else {
ea770789
DM		 834 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
835 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
94e948e6
OZ		 836 if (par->chip != CHIP_357_VIRGE_GX2 &&
837 par->chip != CHIP_359_VIRGE_GX2P &&
838 par->chip != CHIP_360_TRIO3D_1X &&
9966c4fe
OZ		 839 par->chip != CHIP_362_TRIO3D_2X &&
840 par->chip != CHIP_368_TRIO3D_2X)
841 hmul = 2;
a268422d
OZ		 842 }
843 break;
844 case 5:
845 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
846 if (par->chip == CHIP_988_VIRGE_VX) {
847 if (info->var.pixclock > 20000)
ea770789 848 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
a268422d 849 else
ea770789 850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
3827d10e
OZ		 851 } else if (par->chip == CHIP_365_TRIO3D) {
852 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
853 if (info->var.pixclock > 8695) {
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
855 hmul = 2;
856 } else {
857 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
858 multiplex = 1;
859 }
a268422d 860 } else {
ea770789
DM		 861 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
862 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
94e948e6
OZ		 863 if (par->chip != CHIP_357_VIRGE_GX2 &&
864 par->chip != CHIP_359_VIRGE_GX2P &&
865 par->chip != CHIP_360_TRIO3D_1X &&
9966c4fe
OZ		 866 par->chip != CHIP_362_TRIO3D_2X &&
867 par->chip != CHIP_368_TRIO3D_2X)
868 hmul = 2;
a268422d
OZ		 869 }
870 break;
871 case 6:
872 /* VIRGE VX case */
873 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
ea770789 874 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
a268422d
OZ		 875 break;
876 case 7:
877 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
ea770789
DM		 878 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
879 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
a268422d
OZ		 880 break;
881 default:
882 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
883 return -EINVAL;
884 }
885
886 if (par->chip != CHIP_988_VIRGE_VX) {
d907ec04
DM		 887 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
888 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
a268422d
OZ		 889 }
890
891 s3_set_pixclock(info, info->var.pixclock);
38d2620e 892 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
a268422d
OZ		 893 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
894 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
895 hmul, info->node);
896
897 /* Set interlaced mode start/end register */
cb11c048
OZ		 898 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
899 htotal = ((htotal * hmul) / 8) - 5;
900 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
901
902 /* Set Data Transfer Position */
903 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
904 value = clamp((htotal + hsstart + 1) / 2, hsstart + 4, htotal + 1);
905 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
a268422d 906
75814d87 907 memset_io(info->screen_base, 0x00, screen_size);
a268422d 908 /* Device and screen back on */
ea770789 909 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
d907ec04 910 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
a268422d
OZ		 911
912 return 0;
913}
914
915/* Set a colour register */
916
917static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
918 u_int transp, struct fb_info *fb)
919{
920 switch (fb->var.bits_per_pixel) {
921 case 0:
922 case 4:
923 if (regno >= 16)
924 return -EINVAL;
925
926 if ((fb->var.bits_per_pixel == 4) &&
927 (fb->var.nonstd == 0)) {
928 outb(0xF0, VGA_PEL_MSK);
929 outb(regno*16, VGA_PEL_IW);
930 } else {
931 outb(0x0F, VGA_PEL_MSK);
932 outb(regno, VGA_PEL_IW);
933 }
934 outb(red >> 10, VGA_PEL_D);
935 outb(green >> 10, VGA_PEL_D);
936 outb(blue >> 10, VGA_PEL_D);
937 break;
938 case 8:
939 if (regno >= 256)
940 return -EINVAL;
941
942 outb(0xFF, VGA_PEL_MSK);
943 outb(regno, VGA_PEL_IW);
944 outb(red >> 10, VGA_PEL_D);
945 outb(green >> 10, VGA_PEL_D);
946 outb(blue >> 10, VGA_PEL_D);
947 break;
948 case 16:
949 if (regno >= 16)
249bdbbf 950 return 0;
a268422d
OZ		 951
952 if (fb->var.green.length == 5)
953 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
954 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
955 else if (fb->var.green.length == 6)
956 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
957 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
958 else return -EINVAL;
959 break;
960 case 24:
961 case 32:
962 if (regno >= 16)
249bdbbf 963 return 0;
a268422d 964
249bdbbf 965 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
a268422d
OZ		 966 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
967 break;
968 default:
969 return -EINVAL;
970 }
971
972 return 0;
973}
974
975
976/* Set the display blanking state */
977
978static int s3fb_blank(int blank_mode, struct fb_info *info)
979{
d907ec04
DM		 980 struct s3fb_info *par = info->par;
981
a268422d
OZ		 982 switch (blank_mode) {
983 case FB_BLANK_UNBLANK:
984 pr_debug("fb%d: unblank\n", info->node);
ea770789 985 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
d907ec04 986 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
a268422d
OZ		 987 break;
988 case FB_BLANK_NORMAL:
989 pr_debug("fb%d: blank\n", info->node);
ea770789 990 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
d907ec04 991 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 992 break;
993 case FB_BLANK_HSYNC_SUSPEND:
994 pr_debug("fb%d: hsync\n", info->node);
ea770789 995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
d907ec04 996 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 997 break;
998 case FB_BLANK_VSYNC_SUSPEND:
999 pr_debug("fb%d: vsync\n", info->node);
ea770789 1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
d907ec04 1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 1002 break;
1003 case FB_BLANK_POWERDOWN:
1004 pr_debug("fb%d: sync down\n", info->node);
ea770789 1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
d907ec04 1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
a268422d
OZ		 1007 break;
1008 }
1009
1010 return 0;
1011}
1012
1013
1014/* Pan the display */
1015
21da386d
DM		 1016static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1017{
1018 struct s3fb_info *par = info->par;
a268422d
OZ		 1019 unsigned int offset;
1020
a268422d
OZ		 1021 /* Calculate the offset */
1022 if (var->bits_per_pixel == 0) {
1023 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
1024 offset = offset >> 2;
1025 } else {
1026 offset = (var->yoffset * info->fix.line_length) +
1027 (var->xoffset * var->bits_per_pixel / 8);
1028 offset = offset >> 2;
1029 }
1030
1031 /* Set the offset */
21da386d 1032 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
a268422d
OZ		 1033
1034 return 0;
1035}
1036
1037/* ------------------------------------------------------------------------- */
1038
1039/* Frame buffer operations */
1040
1041static struct fb_ops s3fb_ops = {
1042 .owner = THIS_MODULE,
1043 .fb_open = s3fb_open,
1044 .fb_release = s3fb_release,
1045 .fb_check_var = s3fb_check_var,
1046 .fb_set_par = s3fb_set_par,
1047 .fb_setcolreg = s3fb_setcolreg,
1048 .fb_blank = s3fb_blank,
1049 .fb_pan_display = s3fb_pan_display,
1050 .fb_fillrect = s3fb_fillrect,
1051 .fb_copyarea = cfb_copyarea,
1052 .fb_imageblit = s3fb_imageblit,
5a87ede9 1053 .fb_get_caps = svga_get_caps,
a268422d
OZ		 1054};
1055
1056/* ------------------------------------------------------------------------- */
1057
f8645933 1058static int __devinit s3_identification(struct s3fb_info *par)
a268422d 1059{
f8645933
DM		 1060 int chip = par->chip;
1061
a268422d 1062 if (chip == CHIP_XXX_TRIO) {
f8645933
DM		 1063 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1064 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1065 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
a268422d
OZ		 1066
1067 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
1068 if (cr2e == 0x10)
1069 return CHIP_732_TRIO32;
1070 if (cr2e == 0x11) {
1071 if (! (cr2f & 0x40))
1072 return CHIP_764_TRIO64;
1073 else
1074 return CHIP_765_TRIO64VP;
1075 }
1076 }
1077 }
1078
1079 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
f8645933 1080 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
a268422d
OZ		 1081
1082 if (! (cr6f & 0x01))
1083 return CHIP_775_TRIO64V2_DX;
1084 else
1085 return CHIP_785_TRIO64V2_GX;
1086 }
1087
1088 if (chip == CHIP_XXX_VIRGE_DXGX) {
f8645933 1089 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
a268422d
OZ		 1090
1091 if (! (cr6f & 0x01))
1092 return CHIP_375_VIRGE_DX;
1093 else
1094 return CHIP_385_VIRGE_GX;
1095 }
1096
9966c4fe 1097 if (chip == CHIP_36X_TRIO3D_1X_2X) {
f8645933 1098 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
9966c4fe
OZ		 1099 case 0x00:
1100 return CHIP_360_TRIO3D_1X;
1101 case 0x01:
1102 return CHIP_362_TRIO3D_2X;
1103 case 0x02:
1104 return CHIP_368_TRIO3D_2X;
1105 }
1106 }
1107
a268422d
OZ		 1108 return CHIP_UNKNOWN;
1109}
1110
1111
1112/* PCI probe */
1113
1114static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1115{
94c322c3
DM		 1116 struct pci_bus_region bus_reg;
1117 struct resource vga_res;
a268422d
OZ		 1118 struct fb_info *info;
1119 struct s3fb_info *par;
1120 int rc;
1121 u8 regval, cr38, cr39;
86c0f043 1122 bool found = false;
a268422d
OZ		 1123
1124 /* Ignore secondary VGA device because there is no VGA arbitration */
1125 if (! svga_primary_device(dev)) {
1126 dev_info(&(dev->dev), "ignoring secondary device\n");
1127 return -ENODEV;
1128 }
1129
1130 /* Allocate and fill driver data structure */
20e061fb 1131 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
a268422d
OZ		 1132 if (!info) {
1133 dev_err(&(dev->dev), "cannot allocate memory\n");
1134 return -ENOMEM;
1135 }
1136
1137 par = info->par;
1138 mutex_init(&par->open_lock);
1139
1140 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
1141 info->fbops = &s3fb_ops;
1142
1143 /* Prepare PCI device */
1144 rc = pci_enable_device(dev);
1145 if (rc < 0) {
594a8819 1146 dev_err(info->device, "cannot enable PCI device\n");
a268422d
OZ		 1147 goto err_enable_device;
1148 }
1149
1150 rc = pci_request_regions(dev, "s3fb");
1151 if (rc < 0) {
594a8819 1152 dev_err(info->device, "cannot reserve framebuffer region\n");
a268422d
OZ		 1153 goto err_request_regions;
1154 }
1155
1156
1157 info->fix.smem_start = pci_resource_start(dev, 0);
1158 info->fix.smem_len = pci_resource_len(dev, 0);
1159
1160 /* Map physical IO memory address into kernel space */
1161 info->screen_base = pci_iomap(dev, 0, 0);
1162 if (! info->screen_base) {
1163 rc = -ENOMEM;
594a8819 1164 dev_err(info->device, "iomap for framebuffer failed\n");
a268422d
OZ		 1165 goto err_iomap;
1166 }
1167
94c322c3
DM		 1168 bus_reg.start = 0;
1169 bus_reg.end = 64 * 1024;
1170
1171 vga_res.flags = IORESOURCE_IO;
1172
1173 pcibios_bus_to_resource(dev, &vga_res, &bus_reg);
1174
1175 par->state.vgabase = (void __iomem *) vga_res.start;
1176
a268422d 1177 /* Unlock regs */
f8645933
DM		 1178 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1179 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1180 vga_wseq(par->state.vgabase, 0x08, 0x06);
1181 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1182 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
a268422d 1183
9966c4fe 1184 /* Identify chip type */
a268422d 1185 par->chip = id->driver_data & CHIP_MASK;
f8645933 1186 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
a268422d 1187 if (par->chip & CHIP_UNDECIDED_FLAG)
f8645933 1188 par->chip = s3_identification(par);
a268422d 1189
9966c4fe
OZ		 1190 /* Find how many physical memory there is on card */
1191 /* 0x36 register is accessible even if other registers are locked */
f8645933 1192 regval = vga_rcrt(par->state.vgabase, 0x36);
9966c4fe
OZ		 1193 if (par->chip == CHIP_360_TRIO3D_1X ||
1194 par->chip == CHIP_362_TRIO3D_2X ||
5694f9ce
OZ		 1195 par->chip == CHIP_368_TRIO3D_2X ||
1196 par->chip == CHIP_365_TRIO3D) {
9966c4fe
OZ		 1197 switch ((regval & 0xE0) >> 5) {
1198 case 0: /* 8MB -- only 4MB usable for display */
1199 case 1: /* 4MB with 32-bit bus */
1200 case 2: /* 4MB */
1201 info->screen_size = 4 << 20;
1202 break;
5694f9ce 1203 case 4: /* 2MB on 365 Trio3D */
9966c4fe
OZ		 1204 case 6: /* 2MB */
1205 info->screen_size = 2 << 20;
1206 break;
1207 }
94e948e6
OZ		 1208 } else if (par->chip == CHIP_357_VIRGE_GX2 ||
1209 par->chip == CHIP_359_VIRGE_GX2P) {
1210 switch ((regval & 0xC0) >> 6) {
1211 case 1: /* 4MB */
1212 info->screen_size = 4 << 20;
1213 break;
1214 case 3: /* 2MB */
1215 info->screen_size = 2 << 20;
1216 break;
1217 }
9966c4fe
OZ		 1218 } else
1219 info->screen_size = s3_memsizes[regval >> 5] << 10;
1220 info->fix.smem_len = info->screen_size;
1221
a268422d 1222 /* Find MCLK frequency */
f8645933
DM		 1223 regval = vga_rseq(par->state.vgabase, 0x10);
1224 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
a268422d
OZ		 1225 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1226
1227 /* Restore locks */
f8645933
DM		 1228 vga_wcrt(par->state.vgabase, 0x38, cr38);
1229 vga_wcrt(par->state.vgabase, 0x39, cr39);
a268422d
OZ		 1230
1231 strcpy(info->fix.id, s3_names [par->chip]);
1232 info->fix.mmio_start = 0;
1233 info->fix.mmio_len = 0;
1234 info->fix.type = FB_TYPE_PACKED_PIXELS;
1235 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1236 info->fix.ypanstep = 0;
1237 info->fix.accel = FB_ACCEL_NONE;
1238 info->pseudo_palette = (void*) (par->pseudo_palette);
86c0f043
OZ		 1239 info->var.bits_per_pixel = 8;
1240
1241#ifdef CONFIG_FB_S3_DDC
1242 /* Enable MMIO if needed */
1243 if (s3fb_ddc_needs_mmio(par->chip)) {
1244 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
1245 if (par->mmio)
1246 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
1247 else
1248 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
1249 info->fix.smem_start + MMIO_OFFSET);
1250 }
1251 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
1252 if (s3fb_setup_ddc_bus(info) == 0) {
1253 u8 *edid = fb_ddc_read(&par->ddc_adapter);
1254 par->ddc_registered = true;
1255 if (edid) {
1256 fb_edid_to_monspecs(edid, &info->monspecs);
1257 kfree(edid);
1258 if (!info->monspecs.modedb)
1259 dev_err(info->device, "error getting mode database\n");
1260 else {
1261 const struct fb_videomode *m;
1262
1263 fb_videomode_to_modelist(info->monspecs.modedb,
1264 info->monspecs.modedb_len,
1265 &info->modelist);
1266 m = fb_find_best_display(&info->monspecs, &info->modelist);
1267 if (m) {
1268 fb_videomode_to_var(&info->var, m);
1269 /* fill all other info->var's fields */
1270 if (s3fb_check_var(&info->var, info) == 0)
1271 found = true;
1272 }
1273 }
1274 }
1275 }
1276#endif
1277 if (!mode_option && !found)
1278 mode_option = "640x480-8@60";
a268422d
OZ		 1279
1280 /* Prepare startup mode */
86c0f043
OZ		 1281 if (mode_option) {
1282 rc = fb_find_mode(&info->var, info, mode_option,
1283 info->monspecs.modedb, info->monspecs.modedb_len,
1284 NULL, info->var.bits_per_pixel);
1285 if (!rc || rc == 4) {
1286 rc = -EINVAL;
1287 dev_err(info->device, "mode %s not found\n", mode_option);
1288 fb_destroy_modedb(info->monspecs.modedb);
1289 info->monspecs.modedb = NULL;
1290 goto err_find_mode;
1291 }
1292 }
1293
1294 fb_destroy_modedb(info->monspecs.modedb);
1295 info->monspecs.modedb = NULL;
1296
1297 /* maximize virtual vertical size for fast scrolling */
1298 info->var.yres_virtual = info->fix.smem_len * 8 /
1299 (info->var.bits_per_pixel * info->var.xres_virtual);
1300 if (info->var.yres_virtual < info->var.yres) {
1301 dev_err(info->device, "virtual vertical size smaller than real\n");
a268422d
OZ		 1302 goto err_find_mode;
1303 }
1304
99d054d8
OZ		 1305 /* maximize virtual vertical size for fast scrolling */
1306 info->var.yres_virtual = info->fix.smem_len * 8 /
1307 (info->var.bits_per_pixel * info->var.xres_virtual);
1308 if (info->var.yres_virtual < info->var.yres) {
1309 dev_err(info->device, "virtual vertical size smaller than real\n");
1310 goto err_find_mode;
1311 }
1312
a268422d
OZ		 1313 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1314 if (rc < 0) {
594a8819 1315 dev_err(info->device, "cannot allocate colormap\n");
a268422d
OZ		 1316 goto err_alloc_cmap;
1317 }
1318
1319 rc = register_framebuffer(info);
1320 if (rc < 0) {
594a8819 1321 dev_err(info->device, "cannot register framebuffer\n");
a268422d
OZ		 1322 goto err_reg_fb;
1323 }
1324
1325 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
1326 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1327
1328 if (par->chip == CHIP_UNKNOWN)
1329 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
f8645933
DM		 1330 info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e),
1331 vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30));
a268422d
OZ		 1332
1333 /* Record a reference to the driver data */
1334 pci_set_drvdata(dev, info);
1335
1336#ifdef CONFIG_MTRR
1337 if (mtrr) {
1338 par->mtrr_reg = -1;
1339 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1340 }
1341#endif
1342
1343 return 0;
1344
1345 /* Error handling */
1346err_reg_fb:
1347 fb_dealloc_cmap(&info->cmap);
1348err_alloc_cmap:
1349err_find_mode:
86c0f043
OZ		 1350#ifdef CONFIG_FB_S3_DDC
1351 if (par->ddc_registered)
1352 i2c_del_adapter(&par->ddc_adapter);
1353 if (par->mmio)
1354 iounmap(par->mmio);
1355#endif
a268422d
OZ		 1356 pci_iounmap(dev, info->screen_base);
1357err_iomap:
1358 pci_release_regions(dev);
1359err_request_regions:
1360/* pci_disable_device(dev); */
1361err_enable_device:
1362 framebuffer_release(info);
1363 return rc;
1364}
1365
1366
1367/* PCI remove */
1368
1369static void __devexit s3_pci_remove(struct pci_dev *dev)
1370{
1371 struct fb_info *info = pci_get_drvdata(dev);
a268422d
OZ		 1372
1373 if (info) {
1374
1375#ifdef CONFIG_MTRR
47ebea83
AB		 1376 struct s3fb_info *par = info->par;
1377
a268422d
OZ		 1378 if (par->mtrr_reg >= 0) {
1379 mtrr_del(par->mtrr_reg, 0, 0);
1380 par->mtrr_reg = -1;
1381 }
1382#endif
1383
1384 unregister_framebuffer(info);
1385 fb_dealloc_cmap(&info->cmap);
1386
86c0f043
OZ		 1387#ifdef CONFIG_FB_S3_DDC
1388 if (par->ddc_registered)
1389 i2c_del_adapter(&par->ddc_adapter);
1390 if (par->mmio)
1391 iounmap(par->mmio);
1392#endif
1393
a268422d
OZ		 1394 pci_iounmap(dev, info->screen_base);
1395 pci_release_regions(dev);
1396/* pci_disable_device(dev); */
1397
1398 pci_set_drvdata(dev, NULL);
1399 framebuffer_release(info);
1400 }
1401}
1402
1403/* PCI suspend */
1404
1405static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1406{
1407 struct fb_info *info = pci_get_drvdata(dev);
1408 struct s3fb_info *par = info->par;
1409
594a8819 1410 dev_info(info->device, "suspend\n");
a268422d 1411
ac751efa 1412 console_lock();
a268422d
OZ		 1413 mutex_lock(&(par->open_lock));
1414
1415 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1416 mutex_unlock(&(par->open_lock));
ac751efa 1417 console_unlock();
a268422d
OZ		 1418 return 0;
1419 }
1420
1421 fb_set_suspend(info, 1);
1422
1423 pci_save_state(dev);
1424 pci_disable_device(dev);
1425 pci_set_power_state(dev, pci_choose_state(dev, state));
1426
1427 mutex_unlock(&(par->open_lock));
ac751efa 1428 console_unlock();
a268422d
OZ		 1429
1430 return 0;
1431}
1432
1433
1434/* PCI resume */
1435
1436static int s3_pci_resume(struct pci_dev* dev)
1437{
1438 struct fb_info *info = pci_get_drvdata(dev);
1439 struct s3fb_info *par = info->par;
6314db41 1440 int err;
a268422d 1441
594a8819 1442 dev_info(info->device, "resume\n");
a268422d 1443
ac751efa 1444 console_lock();
a268422d
OZ		 1445 mutex_lock(&(par->open_lock));
1446
1447 if (par->ref_count == 0) {
1448 mutex_unlock(&(par->open_lock));
ac751efa 1449 console_unlock();
a268422d
OZ		 1450 return 0;
1451 }
1452
1453 pci_set_power_state(dev, PCI_D0);
1454 pci_restore_state(dev);
6314db41
RD		 1455 err = pci_enable_device(dev);
1456 if (err) {
1457 mutex_unlock(&(par->open_lock));
ac751efa 1458 console_unlock();
594a8819 1459 dev_err(info->device, "error %d enabling device for resume\n", err);
6314db41
RD		 1460 return err;
1461 }
a268422d
OZ		 1462 pci_set_master(dev);
1463
1464 s3fb_set_par(info);
1465 fb_set_suspend(info, 0);
1466
1467 mutex_unlock(&(par->open_lock));
ac751efa 1468 console_unlock();
a268422d
OZ		 1469
1470 return 0;
1471}
1472
1473
1474/* List of boards that we are trying to support */
1475
1476static struct pci_device_id s3_devices[] __devinitdata = {
1477 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1478 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1479 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1480 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1481 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1482 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1483
1484 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1485 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1486 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
94e948e6
OZ		 1487 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
1488 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
a268422d 1489 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
9966c4fe 1490 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
5694f9ce 1491 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
a268422d
OZ		 1492
1493 {0, 0, 0, 0, 0, 0, 0}
1494};
1495
1496
1497MODULE_DEVICE_TABLE(pci, s3_devices);
1498
1499static struct pci_driver s3fb_pci_driver = {
1500 .name = "s3fb",
1501 .id_table = s3_devices,
1502 .probe = s3_pci_probe,
1503 .remove = __devexit_p(s3_pci_remove),
1504 .suspend = s3_pci_suspend,
1505 .resume = s3_pci_resume,
1506};
1507
1508/* Parse user speficied options */
1509
1510#ifndef MODULE
1511static int __init s3fb_setup(char *options)
1512{
1513 char *opt;
1514
1515 if (!options || !*options)
1516 return 0;
1517
1518 while ((opt = strsep(&options, ",")) != NULL) {
1519
1520 if (!*opt)
1521 continue;
1522#ifdef CONFIG_MTRR
62fa4dc7 1523 else if (!strncmp(opt, "mtrr:", 5))
a268422d
OZ		 1524 mtrr = simple_strtoul(opt + 5, NULL, 0);
1525#endif
62fa4dc7
OZ		 1526 else if (!strncmp(opt, "fasttext:", 9))
1527 fasttext = simple_strtoul(opt + 9, NULL, 0);
a268422d 1528 else
a8140543 1529 mode_option = opt;
a268422d
OZ		 1530 }
1531
1532 return 0;
1533}
1534#endif
1535
1536/* Cleanup */
1537
1538static void __exit s3fb_cleanup(void)
1539{
1540 pr_debug("s3fb: cleaning up\n");
1541 pci_unregister_driver(&s3fb_pci_driver);
1542}
1543
1544/* Driver Initialisation */
1545
1546static int __init s3fb_init(void)
1547{
1548
1549#ifndef MODULE
1550 char *option = NULL;
1551
1552 if (fb_get_options("s3fb", &option))
1553 return -ENODEV;
1554 s3fb_setup(option);
1555#endif
1556
1557 pr_debug("s3fb: initializing\n");
1558 return pci_register_driver(&s3fb_pci_driver);
1559}
1560
1561/* ------------------------------------------------------------------------- */
1562
1563/* Modularization */
1564
1565module_init(s3fb_init);
1566module_exit(s3fb_cleanup);
kernel source for telekom puls (alcatel/mediatek)