[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pxafb.h

#ifndef __PXAFB_H__
#define __PXAFB_H__

/*
 * linux/drivers/video/pxafb.h
 *    -- Intel PXA250/210 LCD Controller Frame Buffer Device
 *
 *  Copyright (C) 1999 Eric A. Thomas.
 *  Copyright (C) 2004 Jean-Frederic Clere.
 *  Copyright (C) 2004 Ian Campbell.
 *  Copyright (C) 2004 Jeff Lackey.
 *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
 *  which in turn is
 *   Based on acornfb.c Copyright (C) Russell King.
 *
 *  2001-08-03: Cliff Brake <cbrake@acclent.com>
 *	 - ported SA1100 code to PXA
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

/* PXA LCD DMA descriptor */
struct pxafb_dma_descriptor {
	unsigned int fdadr;
	unsigned int fsadr;
	unsigned int fidr;
	unsigned int ldcmd;
};

enum {
	PAL_NONE	= -1,
	PAL_BASE	= 0,
	PAL_OV1		= 1,
	PAL_OV2		= 2,
	PAL_MAX,
};

enum {
	DMA_BASE	= 0,
	DMA_UPPER	= 0,
	DMA_LOWER	= 1,
	DMA_OV1		= 1,
	DMA_OV2_Y	= 2,
	DMA_OV2_Cb	= 3,
	DMA_OV2_Cr	= 4,
	DMA_CURSOR	= 5,
	DMA_CMD		= 6,
	DMA_MAX,
};

/* maximum palette size - 256 entries, each 4 bytes long */
#define PALETTE_SIZE	(256 * 4)

struct pxafb_dma_buff {
	unsigned char palette[PAL_MAX * PALETTE_SIZE];
	struct pxafb_dma_descriptor pal_desc[PAL_MAX];
	struct pxafb_dma_descriptor dma_desc[DMA_MAX];
};

struct pxafb_info {
	struct fb_info		fb;
	struct device		*dev;
	struct clk		*clk;

	void __iomem		*mmio_base;

	struct pxafb_dma_buff	*dma_buff;
	dma_addr_t		dma_buff_phys;
	dma_addr_t		fdadr[DMA_MAX];

	/*
	 * These are the addresses we mapped
	 * the framebuffer memory region to.
	 */
	/* raw memory addresses */
	dma_addr_t		map_dma;	/* physical */
	u_char *		map_cpu;	/* virtual */
	u_int			map_size;

	/* addresses of pieces placed in raw buffer */
	u_char *		screen_cpu;	/* virtual address of frame buffer */
	dma_addr_t		screen_dma;	/* physical address of frame buffer */
	u16 *			palette_cpu;	/* virtual address of palette memory */
	u_int			palette_size;

	u_int			lccr0;
	u_int			lccr3;
	u_int			lccr4;
	u_int			cmap_inverse:1,
				cmap_static:1,
				unused:30;

	u_int			reg_lccr0;
	u_int			reg_lccr1;
	u_int			reg_lccr2;
	u_int			reg_lccr3;
	u_int			reg_lccr4;

	unsigned long	hsync_time;

	volatile u_char		state;
	volatile u_char		task_state;
	struct semaphore	ctrlr_sem;
	wait_queue_head_t	ctrlr_wait;
	struct work_struct	task;

	struct completion	disable_done;

#ifdef CONFIG_CPU_FREQ
	struct notifier_block	freq_transition;
	struct notifier_block	freq_policy;
#endif
};

#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)

/*
 * These are the actions for set_ctrlr_state
 */
#define C_DISABLE		(0)
#define C_ENABLE		(1)
#define C_DISABLE_CLKCHANGE	(2)
#define C_ENABLE_CLKCHANGE	(3)
#define C_REENABLE		(4)
#define C_DISABLE_PM		(5)
#define C_ENABLE_PM		(6)
#define C_STARTUP		(7)

#define PXA_NAME	"PXA"

/*
 * Minimum X and Y resolutions
 */
#define MIN_XRES	64
#define MIN_YRES	64

#endif /* __PXAFB_H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __PXAFB_H__
	2	#define __PXAFB_H__
	3
	4	/*
	5	* linux/drivers/video/pxafb.h
	6	* -- Intel PXA250/210 LCD Controller Frame Buffer Device
	7	*
	8	* Copyright (C) 1999 Eric A. Thomas.
	9	* Copyright (C) 2004 Jean-Frederic Clere.
	10	* Copyright (C) 2004 Ian Campbell.
	11	* Copyright (C) 2004 Jeff Lackey.
	12	* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
	13	* which in turn is
	14	* Based on acornfb.c Copyright (C) Russell King.
	15	*
	16	* 2001-08-03: Cliff Brake <cbrake@acclent.com>
	17	* - ported SA1100 code to PXA
	18	*
	19	* This file is subject to the terms and conditions of the GNU General Public
	20	* License. See the file COPYING in the main directory of this archive
	21	* for more details.
	22	*/
	23
1da177e4 LT	24	/* PXA LCD DMA descriptor */
	25	struct pxafb_dma_descriptor {
	26	unsigned int fdadr;
	27	unsigned int fsadr;
	28	unsigned int fidr;
	29	unsigned int ldcmd;
	30	};
	31
2c42dd8e	32	enum {
	33	PAL_NONE = -1,
	34	PAL_BASE = 0,
	35	PAL_OV1 = 1,
	36	PAL_OV2 = 2,
	37	PAL_MAX,
	38	};
	39
	40	enum {
	41	DMA_BASE = 0,
	42	DMA_UPPER = 0,
	43	DMA_LOWER = 1,
	44	DMA_OV1 = 1,
	45	DMA_OV2_Y = 2,
	46	DMA_OV2_Cb = 3,
	47	DMA_OV2_Cr = 4,
	48	DMA_CURSOR = 5,
	49	DMA_CMD = 6,
	50	DMA_MAX,
	51	};
	52
	53	/* maximum palette size - 256 entries, each 4 bytes long */
	54	#define PALETTE_SIZE (256 * 4)
	55
	56	struct pxafb_dma_buff {
	57	unsigned char palette[PAL_MAX * PALETTE_SIZE];
	58	struct pxafb_dma_descriptor pal_desc[PAL_MAX];
	59	struct pxafb_dma_descriptor dma_desc[DMA_MAX];
	60	};
	61
1da177e4 LT	62	struct pxafb_info {
	63	struct fb_info fb;
	64	struct device *dev;
72e3524c	65	struct clk *clk;
1da177e4	66
ce4fb7b8	67	void __iomem *mmio_base;
ce4fb7b8	68
2c42dd8e	69	struct pxafb_dma_buff *dma_buff;
	70	dma_addr_t dma_buff_phys;
	71	dma_addr_t fdadr[DMA_MAX];
	72
1da177e4 LT	73	/*
	74	* These are the addresses we mapped
	75	* the framebuffer memory region to.
	76	*/
	77	/* raw memory addresses */
	78	dma_addr_t map_dma; /* physical */
	79	u_char * map_cpu; /* virtual */
	80	u_int map_size;
	81
	82	/* addresses of pieces placed in raw buffer */
	83	u_char * screen_cpu; /* virtual address of frame buffer */
	84	dma_addr_t screen_dma; /* physical address of frame buffer */
	85	u16 * palette_cpu; /* virtual address of palette memory */
1da177e4 LT	86	u_int palette_size;
1da177e4 LT	87
1da177e4 LT	88	u_int lccr0;
1da177e4 LT	89	u_int lccr3;
9ffa7396	90	u_int lccr4;
1da177e4 LT	91	u_int cmap_inverse:1,
	92	cmap_static:1,
	93	unused:30;
	94
	95	u_int reg_lccr0;
	96	u_int reg_lccr1;
	97	u_int reg_lccr2;
	98	u_int reg_lccr3;
9ffa7396	99	u_int reg_lccr4;
1da177e4	100
ba44cd2d RP	101	unsigned long hsync_time;
ba44cd2d RP	102
1da177e4 LT	103	volatile u_char state;
	104	volatile u_char task_state;
	105	struct semaphore ctrlr_sem;
	106	wait_queue_head_t ctrlr_wait;
	107	struct work_struct task;
	108
2ba162b9 EM	109	struct completion disable_done;
2ba162b9 EM	110
1da177e4 LT	111	#ifdef CONFIG_CPU_FREQ
	112	struct notifier_block freq_transition;
	113	struct notifier_block freq_policy;
	114	#endif
	115	};
	116
	117	#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
	118
	119	/*
	120	* These are the actions for set_ctrlr_state
	121	*/
	122	#define C_DISABLE (0)
	123	#define C_ENABLE (1)
	124	#define C_DISABLE_CLKCHANGE (2)
	125	#define C_ENABLE_CLKCHANGE (3)
	126	#define C_REENABLE (4)
	127	#define C_DISABLE_PM (5)
	128	#define C_ENABLE_PM (6)
	129	#define C_STARTUP (7)
	130
	131	#define PXA_NAME "PXA"
	132
1da177e4 LT	133	/*
	134	* Minimum X and Y resolutions
	135	*/
	136	#define MIN_XRES 64
	137	#define MIN_YRES 64
	138
	139	#endif /* __PXAFB_H__ */