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pxafb: introduce lcd_{read,write}l() to wrap the __raw_{read,write}l()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
33#include <linux/fb.h>
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/ioport.h>
37#include <linux/cpufreq.h>
d052d1be 38#include <linux/platform_device.h>
1da177e4 39#include <linux/dma-mapping.h>
72e3524c
RK		 40#include <linux/clk.h>
41#include <linux/err.h>
1da177e4
LT		 42
43#include <asm/hardware.h>
44#include <asm/io.h>
45#include <asm/irq.h>
bf1b8ab6 46#include <asm/div64.h>
1da177e4 47#include <asm/arch/pxa-regs.h>
a683b14d 48#include <asm/arch/pxa2xx-gpio.h>
1da177e4
LT		 49#include <asm/arch/bitfield.h>
50#include <asm/arch/pxafb.h>
51
52/*
53 * Complain if VAR is out of range.
54 */
55#define DEBUG_VAR 1
56
57#include "pxafb.h"
58
59/* Bits which should not be set in machine configuration structures */
b0086efb 60#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
61 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
62 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
63
64#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
65 LCCR3_PCD | LCCR3_BPP)
1da177e4
LT		 66
67static void (*pxafb_backlight_power)(int);
d14b272b 68static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
1da177e4 69
b0086efb 70static int pxafb_activate_var(struct fb_var_screeninfo *var,
71 struct pxafb_info *);
1da177e4
LT		 72static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
73
a7535ba7
EM		 74static inline unsigned long
75lcd_readl(struct pxafb_info *fbi, unsigned int off)
76{
77 return __raw_readl(fbi->mmio_base + off);
78}
79
80static inline void
81lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
82{
83 __raw_writel(val, fbi->mmio_base + off);
84}
85
1da177e4
LT		 86static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
87{
88 unsigned long flags;
89
90 local_irq_save(flags);
91 /*
92 * We need to handle two requests being made at the same time.
93 * There are two important cases:
b0086efb 94 * 1. When we are changing VT (C_REENABLE) while unblanking
95 * (C_ENABLE) We must perform the unblanking, which will
96 * do our REENABLE for us.
97 * 2. When we are blanking, but immediately unblank before
98 * we have blanked. We do the "REENABLE" thing here as
99 * well, just to be sure.
1da177e4
LT		 100 */
101 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
102 state = (u_int) -1;
103 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
104 state = C_REENABLE;
105
106 if (state != (u_int)-1) {
107 fbi->task_state = state;
108 schedule_work(&fbi->task);
109 }
110 local_irq_restore(flags);
111}
112
113static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
114{
115 chan &= 0xffff;
116 chan >>= 16 - bf->length;
117 return chan << bf->offset;
118}
119
120static int
121pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
122 u_int trans, struct fb_info *info)
123{
124 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 125 u_int val;
126
127 if (regno >= fbi->palette_size)
128 return 1;
129
130 if (fbi->fb.var.grayscale) {
131 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
132 return 0;
133 }
134
135 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
136 case LCCR4_PAL_FOR_0:
137 val = ((red >> 0) & 0xf800);
138 val |= ((green >> 5) & 0x07e0);
139 val |= ((blue >> 11) & 0x001f);
1da177e4 140 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 141 break;
142 case LCCR4_PAL_FOR_1:
143 val = ((red << 8) & 0x00f80000);
144 val |= ((green >> 0) & 0x0000fc00);
145 val |= ((blue >> 8) & 0x000000f8);
b0086efb 146 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 147 break;
148 case LCCR4_PAL_FOR_2:
149 val = ((red << 8) & 0x00fc0000);
150 val |= ((green >> 0) & 0x0000fc00);
151 val |= ((blue >> 8) & 0x000000fc);
b0086efb 152 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 153 break;
1da177e4 154 }
9ffa7396
HK		 155
156 return 0;
1da177e4
LT		 157}
158
159static int
160pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
161 u_int trans, struct fb_info *info)
162{
163 struct pxafb_info *fbi = (struct pxafb_info *)info;
164 unsigned int val;
165 int ret = 1;
166
167 /*
168 * If inverse mode was selected, invert all the colours
169 * rather than the register number. The register number
170 * is what you poke into the framebuffer to produce the
171 * colour you requested.
172 */
173 if (fbi->cmap_inverse) {
174 red = 0xffff - red;
175 green = 0xffff - green;
176 blue = 0xffff - blue;
177 }
178
179 /*
180 * If greyscale is true, then we convert the RGB value
181 * to greyscale no matter what visual we are using.
182 */
183 if (fbi->fb.var.grayscale)
184 red = green = blue = (19595 * red + 38470 * green +
185 7471 * blue) >> 16;
186
187 switch (fbi->fb.fix.visual) {
188 case FB_VISUAL_TRUECOLOR:
189 /*
190 * 16-bit True Colour. We encode the RGB value
191 * according to the RGB bitfield information.
192 */
193 if (regno < 16) {
194 u32 *pal = fbi->fb.pseudo_palette;
195
196 val = chan_to_field(red, &fbi->fb.var.red);
197 val |= chan_to_field(green, &fbi->fb.var.green);
198 val |= chan_to_field(blue, &fbi->fb.var.blue);
199
200 pal[regno] = val;
201 ret = 0;
202 }
203 break;
204
205 case FB_VISUAL_STATIC_PSEUDOCOLOR:
206 case FB_VISUAL_PSEUDOCOLOR:
207 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
208 break;
209 }
210
211 return ret;
212}
213
214/*
215 * pxafb_bpp_to_lccr3():
216 * Convert a bits per pixel value to the correct bit pattern for LCCR3
217 */
218static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
219{
b0086efb 220 int ret = 0;
221 switch (var->bits_per_pixel) {
222 case 1: ret = LCCR3_1BPP; break;
223 case 2: ret = LCCR3_2BPP; break;
224 case 4: ret = LCCR3_4BPP; break;
225 case 8: ret = LCCR3_8BPP; break;
226 case 16: ret = LCCR3_16BPP; break;
227 }
228 return ret;
1da177e4
LT		 229}
230
231#ifdef CONFIG_CPU_FREQ
232/*
233 * pxafb_display_dma_period()
234 * Calculate the minimum period (in picoseconds) between two DMA
235 * requests for the LCD controller. If we hit this, it means we're
236 * doing nothing but LCD DMA.
237 */
238static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
239{
b0086efb 240 /*
241 * Period = pixclock * bits_per_byte * bytes_per_transfer
242 * / memory_bits_per_pixel;
243 */
244 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 245}
1da177e4
LT		 246#endif
247
d14b272b
RP		 248/*
249 * Select the smallest mode that allows the desired resolution to be
250 * displayed. If desired parameters can be rounded up.
251 */
b0086efb 252static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
253 struct fb_var_screeninfo *var)
d14b272b
RP		 254{
255 struct pxafb_mode_info *mode = NULL;
256 struct pxafb_mode_info *modelist = mach->modes;
257 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
258 unsigned int i;
259
b0086efb 260 for (i = 0; i < mach->num_modes; i++) {
261 if (modelist[i].xres >= var->xres &&
262 modelist[i].yres >= var->yres &&
263 modelist[i].xres < best_x &&
264 modelist[i].yres < best_y &&
265 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 266 best_x = modelist[i].xres;
267 best_y = modelist[i].yres;
268 mode = &modelist[i];
269 }
270 }
271
272 return mode;
273}
274
b0086efb 275static void pxafb_setmode(struct fb_var_screeninfo *var,
276 struct pxafb_mode_info *mode)
d14b272b
RP		 277{
278 var->xres = mode->xres;
279 var->yres = mode->yres;
280 var->bits_per_pixel = mode->bpp;
281 var->pixclock = mode->pixclock;
282 var->hsync_len = mode->hsync_len;
283 var->left_margin = mode->left_margin;
284 var->right_margin = mode->right_margin;
285 var->vsync_len = mode->vsync_len;
286 var->upper_margin = mode->upper_margin;
287 var->lower_margin = mode->lower_margin;
288 var->sync = mode->sync;
289 var->grayscale = mode->cmap_greyscale;
290 var->xres_virtual = var->xres;
291 var->yres_virtual = var->yres;
292}
293
1da177e4
LT		 294/*
295 * pxafb_check_var():
296 * Get the video params out of 'var'. If a value doesn't fit, round it up,
297 * if it's too big, return -EINVAL.
298 *
299 * Round up in the following order: bits_per_pixel, xres,
300 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
301 * bitfields, horizontal timing, vertical timing.
302 */
303static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
304{
305 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 306 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1da177e4
LT		 307
308 if (var->xres < MIN_XRES)
309 var->xres = MIN_XRES;
310 if (var->yres < MIN_YRES)
311 var->yres = MIN_YRES;
d14b272b
RP		 312
313 if (inf->fixed_modes) {
314 struct pxafb_mode_info *mode;
315
316 mode = pxafb_getmode(inf, var);
317 if (!mode)
318 return -EINVAL;
319 pxafb_setmode(var, mode);
320 } else {
321 if (var->xres > inf->modes->xres)
322 return -EINVAL;
323 if (var->yres > inf->modes->yres)
324 return -EINVAL;
325 if (var->bits_per_pixel > inf->modes->bpp)
326 return -EINVAL;
327 }
328
1da177e4
LT		 329 var->xres_virtual =
330 max(var->xres_virtual, var->xres);
331 var->yres_virtual =
332 max(var->yres_virtual, var->yres);
333
b0086efb 334 /*
1da177e4
LT		 335 * Setup the RGB parameters for this display.
336 *
337 * The pixel packing format is described on page 7-11 of the
338 * PXA2XX Developer's Manual.
b0086efb 339 */
1da177e4
LT		 340 if (var->bits_per_pixel == 16) {
341 var->red.offset = 11; var->red.length = 5;
342 var->green.offset = 5; var->green.length = 6;
343 var->blue.offset = 0; var->blue.length = 5;
344 var->transp.offset = var->transp.length = 0;
345 } else {
b0086efb 346 var->red.offset = var->green.offset = 0;
347 var->blue.offset = var->transp.offset = 0;
1da177e4
LT		 348 var->red.length = 8;
349 var->green.length = 8;
350 var->blue.length = 8;
351 var->transp.length = 0;
352 }
353
354#ifdef CONFIG_CPU_FREQ
ca5da710
RK		 355 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
356 pxafb_display_dma_period(var),
357 get_clk_frequency_khz(0));
1da177e4
LT		 358#endif
359
360 return 0;
361}
362
363static inline void pxafb_set_truecolor(u_int is_true_color)
364{
b0086efb 365 /* do your machine-specific setup if needed */
1da177e4
LT		 366}
367
368/*
369 * pxafb_set_par():
370 * Set the user defined part of the display for the specified console
371 */
372static int pxafb_set_par(struct fb_info *info)
373{
374 struct pxafb_info *fbi = (struct pxafb_info *)info;
375 struct fb_var_screeninfo *var = &info->var;
1da177e4 376
1da177e4
LT		 377 if (var->bits_per_pixel == 16)
378 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
379 else if (!fbi->cmap_static)
380 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
381 else {
382 /*
383 * Some people have weird ideas about wanting static
384 * pseudocolor maps. I suspect their user space
385 * applications are broken.
386 */
387 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
388 }
389
390 fbi->fb.fix.line_length = var->xres_virtual *
391 var->bits_per_pixel / 8;
392 if (var->bits_per_pixel == 16)
393 fbi->palette_size = 0;
394 else
b0086efb 395 fbi->palette_size = var->bits_per_pixel == 1 ?
396 4 : 1 << var->bits_per_pixel;
1da177e4 397
2c42dd8e 398 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4
LT		 399
400 /*
401 * Set (any) board control register to handle new color depth
402 */
403 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
404
405 if (fbi->fb.var.bits_per_pixel == 16)
406 fb_dealloc_cmap(&fbi->fb.cmap);
407 else
408 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
409
410 pxafb_activate_var(var, fbi);
411
412 return 0;
413}
414
1da177e4
LT		 415/*
416 * pxafb_blank():
417 * Blank the display by setting all palette values to zero. Note, the
418 * 16 bpp mode does not really use the palette, so this will not
419 * blank the display in all modes.
420 */
421static int pxafb_blank(int blank, struct fb_info *info)
422{
423 struct pxafb_info *fbi = (struct pxafb_info *)info;
424 int i;
425
1da177e4
LT		 426 switch (blank) {
427 case FB_BLANK_POWERDOWN:
428 case FB_BLANK_VSYNC_SUSPEND:
429 case FB_BLANK_HSYNC_SUSPEND:
430 case FB_BLANK_NORMAL:
431 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
432 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
433 for (i = 0; i < fbi->palette_size; i++)
434 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
435
436 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 437 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 438 break;
439
440 case FB_BLANK_UNBLANK:
b0086efb 441 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 442 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
443 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
444 fb_set_cmap(&fbi->fb.cmap, info);
445 pxafb_schedule_work(fbi, C_ENABLE);
446 }
447 return 0;
448}
449
216d526c 450static int pxafb_mmap(struct fb_info *info,
1da177e4
LT		 451 struct vm_area_struct *vma)
452{
453 struct pxafb_info *fbi = (struct pxafb_info *)info;
454 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
455
456 if (off < info->fix.smem_len) {
457 vma->vm_pgoff += 1;
458 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
459 fbi->map_dma, fbi->map_size);
460 }
461 return -EINVAL;
462}
463
464static struct fb_ops pxafb_ops = {
465 .owner = THIS_MODULE,
466 .fb_check_var = pxafb_check_var,
467 .fb_set_par = pxafb_set_par,
468 .fb_setcolreg = pxafb_setcolreg,
469 .fb_fillrect = cfb_fillrect,
470 .fb_copyarea = cfb_copyarea,
471 .fb_imageblit = cfb_imageblit,
472 .fb_blank = pxafb_blank,
1da177e4
LT		 473 .fb_mmap = pxafb_mmap,
474};
475
476/*
477 * Calculate the PCD value from the clock rate (in picoseconds).
478 * We take account of the PPCR clock setting.
479 * From PXA Developer's Manual:
480 *
481 * PixelClock = LCLK
482 * -------------
483 * 2 ( PCD + 1 )
484 *
485 * PCD = LCLK
486 * ------------- - 1
487 * 2(PixelClock)
488 *
489 * Where:
490 * LCLK = LCD/Memory Clock
491 * PCD = LCCR3[7:0]
492 *
493 * PixelClock here is in Hz while the pixclock argument given is the
494 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
495 *
496 * The function get_lclk_frequency_10khz returns LCLK in units of
497 * 10khz. Calling the result of this function lclk gives us the
498 * following
499 *
500 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
501 * -------------------------------------- - 1
502 * 2
503 *
504 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
505 */
b0086efb 506static inline unsigned int get_pcd(struct pxafb_info *fbi,
507 unsigned int pixclock)
1da177e4
LT		 508{
509 unsigned long long pcd;
510
511 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 512 * (DPC) bit? or perhaps set it based on the various clock
513 * speeds */
514 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
515 pcd *= pixclock;
bf1b8ab6 516 do_div(pcd, 100000000 * 2);
1da177e4
LT		 517 /* no need for this, since we should subtract 1 anyway. they cancel */
518 /* pcd += 1; */ /* make up for integer math truncations */
519 return (unsigned int)pcd;
520}
521
ba44cd2d
RP		 522/*
523 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 524 * function correctly. We export it here. Note that 'hsync_time' and
525 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
526 * of the hsync period in seconds.
ba44cd2d
RP		 527 */
528static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
529{
72e3524c 530 unsigned long htime;
ba44cd2d
RP		 531
532 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 533 fbi->hsync_time = 0;
ba44cd2d
RP		 534 return;
535 }
536
72e3524c
RK		 537 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
538
ba44cd2d
RP		 539 fbi->hsync_time = htime;
540}
541
542unsigned long pxafb_get_hsync_time(struct device *dev)
543{
544 struct pxafb_info *fbi = dev_get_drvdata(dev);
545
546 /* If display is blanked/suspended, hsync isn't active */
547 if (!fbi || (fbi->state != C_ENABLE))
548 return 0;
549
550 return fbi->hsync_time;
551}
552EXPORT_SYMBOL(pxafb_get_hsync_time);
553
2c42dd8e 554static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
555 unsigned int offset, size_t size)
556{
557 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
558 unsigned int dma_desc_off, pal_desc_off;
559
560 if (dma < 0 || dma >= DMA_MAX)
561 return -EINVAL;
562
563 dma_desc = &fbi->dma_buff->dma_desc[dma];
564 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
565
566 dma_desc->fsadr = fbi->screen_dma + offset;
567 dma_desc->fidr = 0;
568 dma_desc->ldcmd = size;
569
570 if (pal < 0 || pal >= PAL_MAX) {
571 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
572 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
573 } else {
574 pal_desc = &fbi->dma_buff->pal_desc[dma];
575 pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]);
576
577 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
578 pal_desc->fidr = 0;
579
580 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
581 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
582 else
583 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
584
585 pal_desc->ldcmd |= LDCMD_PAL;
586
587 /* flip back and forth between palette and frame buffer */
588 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
589 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
590 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
591 }
592
593 return 0;
594}
595
1da177e4
LT		 596/*
597 * pxafb_activate_var():
b0086efb 598 * Configures LCD Controller based on entries in var parameter.
599 * Settings are only written to the controller if changes were made.
1da177e4 600 */
b0086efb 601static int pxafb_activate_var(struct fb_var_screeninfo *var,
602 struct pxafb_info *fbi)
1da177e4
LT		 603{
604 struct pxafb_lcd_reg new_regs;
605 u_long flags;
72e3524c 606 u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
2c42dd8e 607 size_t nbytes;
1da177e4 608
1da177e4 609#if DEBUG_VAR
b0086efb 610 if (var->xres < 16 || var->xres > 1024)
1da177e4
LT		 611 printk(KERN_ERR "%s: invalid xres %d\n",
612 fbi->fb.fix.id, var->xres);
b0086efb 613 switch (var->bits_per_pixel) {
1da177e4
LT		 614 case 1:
615 case 2:
616 case 4:
617 case 8:
618 case 16:
619 break;
620 default:
621 printk(KERN_ERR "%s: invalid bit depth %d\n",
622 fbi->fb.fix.id, var->bits_per_pixel);
623 break;
624 }
b0086efb 625 if (var->hsync_len < 1 || var->hsync_len > 64)
1da177e4
LT		 626 printk(KERN_ERR "%s: invalid hsync_len %d\n",
627 fbi->fb.fix.id, var->hsync_len);
b0086efb 628 if (var->left_margin < 1 || var->left_margin > 255)
1da177e4
LT		 629 printk(KERN_ERR "%s: invalid left_margin %d\n",
630 fbi->fb.fix.id, var->left_margin);
631 if (var->right_margin < 1 || var->right_margin > 255)
632 printk(KERN_ERR "%s: invalid right_margin %d\n",
633 fbi->fb.fix.id, var->right_margin);
b0086efb 634 if (var->yres < 1 || var->yres > 1024)
1da177e4
LT		 635 printk(KERN_ERR "%s: invalid yres %d\n",
636 fbi->fb.fix.id, var->yres);
b0086efb 637 if (var->vsync_len < 1 || var->vsync_len > 64)
1da177e4
LT		 638 printk(KERN_ERR "%s: invalid vsync_len %d\n",
639 fbi->fb.fix.id, var->vsync_len);
640 if (var->upper_margin < 0 || var->upper_margin > 255)
641 printk(KERN_ERR "%s: invalid upper_margin %d\n",
642 fbi->fb.fix.id, var->upper_margin);
643 if (var->lower_margin < 0 || var->lower_margin > 255)
644 printk(KERN_ERR "%s: invalid lower_margin %d\n",
645 fbi->fb.fix.id, var->lower_margin);
646#endif
647
648 new_regs.lccr0 = fbi->lccr0 |
649 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 650 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4
LT		 651
652 new_regs.lccr1 =
653 LCCR1_DisWdth(var->xres) +
654 LCCR1_HorSnchWdth(var->hsync_len) +
655 LCCR1_BegLnDel(var->left_margin) +
656 LCCR1_EndLnDel(var->right_margin);
657
658 /*
659 * If we have a dual scan LCD, we need to halve
660 * the YRES parameter.
661 */
662 lines_per_panel = var->yres;
663 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
664 lines_per_panel /= 2;
665
666 new_regs.lccr2 =
667 LCCR2_DisHght(lines_per_panel) +
668 LCCR2_VrtSnchWdth(var->vsync_len) +
669 LCCR2_BegFrmDel(var->upper_margin) +
670 LCCR2_EndFrmDel(var->lower_margin);
671
672 new_regs.lccr3 = fbi->lccr3 |
673 pxafb_bpp_to_lccr3(var) |
b0086efb 674 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
675 LCCR3_HorSnchH : LCCR3_HorSnchL) |
676 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
677 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1da177e4
LT		 678
679 if (pcd)
680 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
681
1da177e4
LT		 682 /* Update shadow copy atomically */
683 local_irq_save(flags);
684
2c42dd8e 685 nbytes = lines_per_panel * fbi->fb.fix.line_length;
1da177e4 686
2c42dd8e 687 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
688 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
689
690 if (var->bits_per_pixel >= 16)
691 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
692 else
693 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
1da177e4 694
1da177e4
LT		 695 fbi->reg_lccr0 = new_regs.lccr0;
696 fbi->reg_lccr1 = new_regs.lccr1;
697 fbi->reg_lccr2 = new_regs.lccr2;
698 fbi->reg_lccr3 = new_regs.lccr3;
a7535ba7 699 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 700 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
ba44cd2d 701 set_hsync_time(fbi, pcd);
1da177e4
LT		 702 local_irq_restore(flags);
703
704 /*
705 * Only update the registers if the controller is enabled
706 * and something has changed.
707 */
a7535ba7
EM		 708 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
709 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
710 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
711 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
712 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
713 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 714 pxafb_schedule_work(fbi, C_REENABLE);
715
716 return 0;
717}
718
719/*
720 * NOTE! The following functions are purely helpers for set_ctrlr_state.
721 * Do not call them directly; set_ctrlr_state does the correct serialisation
722 * to ensure that things happen in the right way 100% of time time.
723 * -- rmk
724 */
725static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
726{
ca5da710 727 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 728
b0086efb 729 if (pxafb_backlight_power)
730 pxafb_backlight_power(on);
1da177e4
LT		 731}
732
733static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
734{
ca5da710 735 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4
LT		 736
737 if (pxafb_lcd_power)
d14b272b 738 pxafb_lcd_power(on, &fbi->fb.var);
1da177e4
LT		 739}
740
741static void pxafb_setup_gpio(struct pxafb_info *fbi)
742{
743 int gpio, ldd_bits;
b0086efb 744 unsigned int lccr0 = fbi->lccr0;
1da177e4
LT		 745
746 /*
747 * setup is based on type of panel supported
b0086efb 748 */
1da177e4
LT		 749
750 /* 4 bit interface */
751 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
752 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
753 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
754 ldd_bits = 4;
755
756 /* 8 bit interface */
b0086efb 757 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
758 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
759 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
760 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
761 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
762 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1da177e4
LT		 763 ldd_bits = 8;
764
765 /* 16 bit interface */
766 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
b0086efb 767 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
768 (lccr0 & LCCR0_PAS) == LCCR0_Act))
1da177e4
LT		 769 ldd_bits = 16;
770
771 else {
b0086efb 772 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
773 "bits per pixel\n");
1da177e4 774 return;
b0086efb 775 }
1da177e4
LT		 776
777 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
778 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
779 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
780 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
781 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
782 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
783}
784
785static void pxafb_enable_controller(struct pxafb_info *fbi)
786{
ca5da710 787 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 788 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
789 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 790 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
791 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
792 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
793 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 794
8d372266 795 /* enable LCD controller clock */
72e3524c 796 clk_enable(fbi->clk);
8d372266 797
1da177e4 798 /* Sequence from 11.7.10 */
a7535ba7
EM		 799 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
800 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
801 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
802 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
803
804 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
805 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
806 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 807}
808
809static void pxafb_disable_controller(struct pxafb_info *fbi)
810{
ce4fb7b8 811 uint32_t lccr0;
812
1da177e4
LT		 813 DECLARE_WAITQUEUE(wait, current);
814
1da177e4
LT		 815 set_current_state(TASK_UNINTERRUPTIBLE);
816 add_wait_queue(&fbi->ctrlr_wait, &wait);
817
ce4fb7b8 818 /* Clear LCD Status Register */
a7535ba7 819 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 820
a7535ba7
EM		 821 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
822 lcd_writel(fbi, LCCR0, lccr0);
823 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 824
2cbbb3b5 825 schedule_timeout(200 * HZ / 1000);
1da177e4 826 remove_wait_queue(&fbi->ctrlr_wait, &wait);
8d372266
NP		 827
828 /* disable LCD controller clock */
72e3524c 829 clk_disable(fbi->clk);
1da177e4
LT		 830}
831
832/*
833 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
834 */
7d12e780 835static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 836{
837 struct pxafb_info *fbi = dev_id;
a7535ba7 838 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 839
840 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 841 lccr0 = lcd_readl(fbi, LCCR0);
842 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1da177e4
LT		 843 wake_up(&fbi->ctrlr_wait);
844 }
845
a7535ba7 846 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 847 return IRQ_HANDLED;
848}
849
850/*
851 * This function must be called from task context only, since it will
852 * sleep when disabling the LCD controller, or if we get two contending
853 * processes trying to alter state.
854 */
855static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
856{
857 u_int old_state;
858
859 down(&fbi->ctrlr_sem);
860
861 old_state = fbi->state;
862
863 /*
864 * Hack around fbcon initialisation.
865 */
866 if (old_state == C_STARTUP && state == C_REENABLE)
867 state = C_ENABLE;
868
869 switch (state) {
870 case C_DISABLE_CLKCHANGE:
871 /*
872 * Disable controller for clock change. If the
873 * controller is already disabled, then do nothing.
874 */
875 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
876 fbi->state = state;
b0086efb 877 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 878 pxafb_disable_controller(fbi);
879 }
880 break;
881
882 case C_DISABLE_PM:
883 case C_DISABLE:
884 /*
885 * Disable controller
886 */
887 if (old_state != C_DISABLE) {
888 fbi->state = state;
889 __pxafb_backlight_power(fbi, 0);
890 __pxafb_lcd_power(fbi, 0);
891 if (old_state != C_DISABLE_CLKCHANGE)
892 pxafb_disable_controller(fbi);
893 }
894 break;
895
896 case C_ENABLE_CLKCHANGE:
897 /*
898 * Enable the controller after clock change. Only
899 * do this if we were disabled for the clock change.
900 */
901 if (old_state == C_DISABLE_CLKCHANGE) {
902 fbi->state = C_ENABLE;
903 pxafb_enable_controller(fbi);
b0086efb 904 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 905 }
906 break;
907
908 case C_REENABLE:
909 /*
910 * Re-enable the controller only if it was already
911 * enabled. This is so we reprogram the control
912 * registers.
913 */
914 if (old_state == C_ENABLE) {
d14b272b 915 __pxafb_lcd_power(fbi, 0);
1da177e4
LT		 916 pxafb_disable_controller(fbi);
917 pxafb_setup_gpio(fbi);
918 pxafb_enable_controller(fbi);
d14b272b 919 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 920 }
921 break;
922
923 case C_ENABLE_PM:
924 /*
925 * Re-enable the controller after PM. This is not
926 * perfect - think about the case where we were doing
927 * a clock change, and we suspended half-way through.
928 */
929 if (old_state != C_DISABLE_PM)
930 break;
931 /* fall through */
932
933 case C_ENABLE:
934 /*
935 * Power up the LCD screen, enable controller, and
936 * turn on the backlight.
937 */
938 if (old_state != C_ENABLE) {
939 fbi->state = C_ENABLE;
940 pxafb_setup_gpio(fbi);
941 pxafb_enable_controller(fbi);
942 __pxafb_lcd_power(fbi, 1);
943 __pxafb_backlight_power(fbi, 1);
944 }
945 break;
946 }
947 up(&fbi->ctrlr_sem);
948}
949
950/*
951 * Our LCD controller task (which is called when we blank or unblank)
952 * via keventd.
953 */
6d5aefb8 954static void pxafb_task(struct work_struct *work)
1da177e4 955{
6d5aefb8
DH		 956 struct pxafb_info *fbi =
957 container_of(work, struct pxafb_info, task);
1da177e4
LT		 958 u_int state = xchg(&fbi->task_state, -1);
959
960 set_ctrlr_state(fbi, state);
961}
962
963#ifdef CONFIG_CPU_FREQ
964/*
965 * CPU clock speed change handler. We need to adjust the LCD timing
966 * parameters when the CPU clock is adjusted by the power management
967 * subsystem.
968 *
969 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
970 */
971static int
972pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
973{
974 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 975 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 976 u_int pcd;
977
978 switch (val) {
979 case CPUFREQ_PRECHANGE:
980 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
981 break;
982
983 case CPUFREQ_POSTCHANGE:
72e3524c 984 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 985 set_hsync_time(fbi, pcd);
b0086efb 986 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
987 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 988 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
989 break;
990 }
991 return 0;
992}
993
994static int
995pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
996{
997 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
998 struct fb_var_screeninfo *var = &fbi->fb.var;
999 struct cpufreq_policy *policy = data;
1000
1001 switch (val) {
1002 case CPUFREQ_ADJUST:
1003 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1004 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1005 "new clock %d kHz\n", pxafb_display_dma_period(var),
1006 policy->max);
b0086efb 1007 /* TODO: fill in min/max values */
1da177e4 1008 break;
1da177e4
LT		 1009 }
1010 return 0;
1011}
1012#endif
1013
1014#ifdef CONFIG_PM
1015/*
1016 * Power management hooks. Note that we won't be called from IRQ context,
1017 * unlike the blank functions above, so we may sleep.
1018 */
3ae5eaec 1019static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1020{
3ae5eaec 1021 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1022
9480e307 1023 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1024 return 0;
1025}
1026
3ae5eaec 1027static int pxafb_resume(struct platform_device *dev)
1da177e4 1028{
3ae5eaec 1029 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1030
9480e307 1031 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1032 return 0;
1033}
1034#else
1035#define pxafb_suspend NULL
1036#define pxafb_resume NULL
1037#endif
1038
1039/*
1040 * pxafb_map_video_memory():
1041 * Allocates the DRAM memory for the frame buffer. This buffer is
1042 * remapped into a non-cached, non-buffered, memory region to
1043 * allow palette and pixel writes to occur without flushing the
1044 * cache. Once this area is remapped, all virtual memory
1045 * access to the video memory should occur at the new region.
1046 */
1047static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1048{
1da177e4
LT		 1049 /*
1050 * We reserve one page for the palette, plus the size
1051 * of the framebuffer.
1052 */
1053 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1054 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1055 &fbi->map_dma, GFP_KERNEL);
1056
1057 if (fbi->map_cpu) {
1058 /* prevent initial garbage on screen */
1059 memset(fbi->map_cpu, 0, fbi->map_size);
1060 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1061 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1062 /*
1063 * FIXME: this is actually the wrong thing to place in
1064 * smem_start. But fbdev suffers from the problem that
1065 * it needs an API which doesn't exist (in this case,
1066 * dma_writecombine_mmap)
1067 */
1068 fbi->fb.fix.smem_start = fbi->screen_dma;
1da177e4
LT		 1069 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1070
2c42dd8e 1071 fbi->dma_buff = (void *)fbi->map_cpu;
1072 fbi->dma_buff_phys = fbi->map_dma;
1073 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4
LT		 1074 }
1075
1076 return fbi->map_cpu ? 0 : -ENOMEM;
1077}
1078
84f43c30 1079static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1080 struct pxafb_mode_info *modes,
1081 unsigned int num_modes)
1082{
1083 unsigned int i, smemlen;
1084
1085 pxafb_setmode(&fbi->fb.var, &modes[0]);
1086
1087 for (i = 0; i < num_modes; i++) {
1088 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1089 if (smemlen > fbi->fb.fix.smem_len)
1090 fbi->fb.fix.smem_len = smemlen;
1091 }
1092}
1093
1094static int pxafb_decode_mach_info(struct pxafb_info *fbi,
1095 struct pxafb_mach_info *inf)
1096{
1097 unsigned int lcd_conn = inf->lcd_conn;
1098
1099 fbi->cmap_inverse = inf->cmap_inverse;
1100 fbi->cmap_static = inf->cmap_static;
1101
1102 switch (lcd_conn & 0xf) {
1103 case LCD_TYPE_MONO_STN:
1104 fbi->lccr0 = LCCR0_CMS;
1105 break;
1106 case LCD_TYPE_MONO_DSTN:
1107 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1108 break;
1109 case LCD_TYPE_COLOR_STN:
1110 fbi->lccr0 = 0;
1111 break;
1112 case LCD_TYPE_COLOR_DSTN:
1113 fbi->lccr0 = LCCR0_SDS;
1114 break;
1115 case LCD_TYPE_COLOR_TFT:
1116 fbi->lccr0 = LCCR0_PAS;
1117 break;
1118 case LCD_TYPE_SMART_PANEL:
1119 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1120 break;
1121 default:
1122 /* fall back to backward compatibility way */
1123 fbi->lccr0 = inf->lccr0;
1124 fbi->lccr3 = inf->lccr3;
1125 fbi->lccr4 = inf->lccr4;
1126 return -EINVAL;
1127 }
1128
1129 if (lcd_conn == LCD_MONO_STN_8BPP)
1130 fbi->lccr0 |= LCCR0_DPD;
1131
1132 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1133 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1134 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1135
1136 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1137 return 0;
1138}
1139
1da177e4
LT		 1140static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1141{
1142 struct pxafb_info *fbi;
1143 void *addr;
1144 struct pxafb_mach_info *inf = dev->platform_data;
d14b272b 1145 struct pxafb_mode_info *mode = inf->modes;
1da177e4
LT		 1146
1147 /* Alloc the pxafb_info and pseudo_palette in one step */
1148 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1149 if (!fbi)
1150 return NULL;
1151
1152 memset(fbi, 0, sizeof(struct pxafb_info));
1153 fbi->dev = dev;
1154
72e3524c
RK		 1155 fbi->clk = clk_get(dev, "LCDCLK");
1156 if (IS_ERR(fbi->clk)) {
1157 kfree(fbi);
1158 return NULL;
1159 }
1160
1da177e4
LT		 1161 strcpy(fbi->fb.fix.id, PXA_NAME);
1162
1163 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1164 fbi->fb.fix.type_aux = 0;
1165 fbi->fb.fix.xpanstep = 0;
1166 fbi->fb.fix.ypanstep = 0;
1167 fbi->fb.fix.ywrapstep = 0;
1168 fbi->fb.fix.accel = FB_ACCEL_NONE;
1169
1170 fbi->fb.var.nonstd = 0;
1171 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1172 fbi->fb.var.height = -1;
1173 fbi->fb.var.width = -1;
1174 fbi->fb.var.accel_flags = 0;
1175 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1176
1177 fbi->fb.fbops = &pxafb_ops;
1178 fbi->fb.flags = FBINFO_DEFAULT;
1179 fbi->fb.node = -1;
1180
1181 addr = fbi;
1182 addr = addr + sizeof(struct pxafb_info);
1183 fbi->fb.pseudo_palette = addr;
1184
b0086efb 1185 fbi->state = C_STARTUP;
1186 fbi->task_state = (u_char)-1;
d14b272b 1187
84f43c30 1188 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1189
1190 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1191 INIT_WORK(&fbi->task, pxafb_task);
1da177e4
LT		 1192 init_MUTEX(&fbi->ctrlr_sem);
1193
1194 return fbi;
1195}
1196
1197#ifdef CONFIG_FB_PXA_PARAMETERS
b0086efb 1198static int __init parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1199{
1200 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1201
1202 const char *name = this_opt+5;
1203 unsigned int namelen = strlen(name);
1204 int res_specified = 0, bpp_specified = 0;
1205 unsigned int xres = 0, yres = 0, bpp = 0;
1206 int yres_specified = 0;
1207 int i;
1208 for (i = namelen-1; i >= 0; i--) {
1209 switch (name[i]) {
1210 case '-':
1211 namelen = i;
1212 if (!bpp_specified && !yres_specified) {
1213 bpp = simple_strtoul(&name[i+1], NULL, 0);
1214 bpp_specified = 1;
1215 } else
1216 goto done;
1217 break;
1218 case 'x':
1219 if (!yres_specified) {
1220 yres = simple_strtoul(&name[i+1], NULL, 0);
1221 yres_specified = 1;
1222 } else
1223 goto done;
1224 break;
1225 case '0' ... '9':
1226 break;
1227 default:
1228 goto done;
1229 }
1230 }
1231 if (i < 0 && yres_specified) {
1232 xres = simple_strtoul(name, NULL, 0);
1233 res_specified = 1;
1234 }
1235done:
1236 if (res_specified) {
1237 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1238 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1239 }
1240 if (bpp_specified)
1241 switch (bpp) {
1242 case 1:
1243 case 2:
1244 case 4:
1245 case 8:
1246 case 16:
1247 inf->modes[0].bpp = bpp;
1248 dev_info(dev, "overriding bit depth: %d\n", bpp);
1249 break;
1250 default:
1251 dev_err(dev, "Depth %d is not valid\n", bpp);
1252 return -EINVAL;
1253 }
1254 return 0;
1255}
1256
b0086efb 1257static int __init parse_opt(struct device *dev, char *this_opt)
817daf14 1258{
1259 struct pxafb_mach_info *inf = dev->platform_data;
1260 struct pxafb_mode_info *mode = &inf->modes[0];
1261 char s[64];
1262
1263 s[0] = '\0';
1264
1265 if (!strncmp(this_opt, "mode:", 5)) {
1266 return parse_opt_mode(dev, this_opt);
1267 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1268 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1269 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1270 } else if (!strncmp(this_opt, "left:", 5)) {
1271 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1272 sprintf(s, "left: %u\n", mode->left_margin);
1273 } else if (!strncmp(this_opt, "right:", 6)) {
1274 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1275 sprintf(s, "right: %u\n", mode->right_margin);
1276 } else if (!strncmp(this_opt, "upper:", 6)) {
1277 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1278 sprintf(s, "upper: %u\n", mode->upper_margin);
1279 } else if (!strncmp(this_opt, "lower:", 6)) {
1280 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1281 sprintf(s, "lower: %u\n", mode->lower_margin);
1282 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1283 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1284 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1285 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1286 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1287 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1288 } else if (!strncmp(this_opt, "hsync:", 6)) {
1289 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1290 sprintf(s, "hsync: Active Low\n");
1291 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1292 } else {
1293 sprintf(s, "hsync: Active High\n");
1294 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1295 }
1296 } else if (!strncmp(this_opt, "vsync:", 6)) {
1297 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1298 sprintf(s, "vsync: Active Low\n");
1299 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1300 } else {
1301 sprintf(s, "vsync: Active High\n");
1302 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1303 }
1304 } else if (!strncmp(this_opt, "dpc:", 4)) {
1305 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1306 sprintf(s, "double pixel clock: false\n");
1307 inf->lccr3 &= ~LCCR3_DPC;
1308 } else {
1309 sprintf(s, "double pixel clock: true\n");
1310 inf->lccr3 |= LCCR3_DPC;
1311 }
1312 } else if (!strncmp(this_opt, "outputen:", 9)) {
1313 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1314 sprintf(s, "output enable: active low\n");
1315 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1316 } else {
1317 sprintf(s, "output enable: active high\n");
1318 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1319 }
1320 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1321 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1322 sprintf(s, "pixel clock polarity: falling edge\n");
1323 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1324 } else {
1325 sprintf(s, "pixel clock polarity: rising edge\n");
1326 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1327 }
1328 } else if (!strncmp(this_opt, "color", 5)) {
1329 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1330 } else if (!strncmp(this_opt, "mono", 4)) {
1331 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1332 } else if (!strncmp(this_opt, "active", 6)) {
1333 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1334 } else if (!strncmp(this_opt, "passive", 7)) {
1335 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1336 } else if (!strncmp(this_opt, "single", 6)) {
1337 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1338 } else if (!strncmp(this_opt, "dual", 4)) {
1339 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1340 } else if (!strncmp(this_opt, "4pix", 4)) {
1341 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1342 } else if (!strncmp(this_opt, "8pix", 4)) {
1343 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1344 } else {
1345 dev_err(dev, "unknown option: %s\n", this_opt);
1346 return -EINVAL;
1347 }
1348
1349 if (s[0] != '\0')
1350 dev_info(dev, "override %s", s);
1351
1352 return 0;
1353}
1354
1355static int __init pxafb_parse_options(struct device *dev, char *options)
1356{
1da177e4 1357 char *this_opt;
817daf14 1358 int ret;
1da177e4 1359
817daf14 1360 if (!options || !*options)
1361 return 0;
1da177e4
LT		 1362
1363 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1364
1365 /* could be made table driven or similar?... */
817daf14 1366 while ((this_opt = strsep(&options, ",")) != NULL) {
1367 ret = parse_opt(dev, this_opt);
1368 if (ret)
1369 return ret;
1370 }
1371 return 0;
1da177e4 1372}
92ac73c1 1373
1374static char g_options[256] __devinitdata = "";
1375
1376#ifndef CONFIG_MODULES
1377static int __devinit pxafb_setup_options(void)
1378{
1379 char *options = NULL;
1380
1381 if (fb_get_options("pxafb", &options))
1382 return -ENODEV;
1383
1384 if (options)
1385 strlcpy(g_options, options, sizeof(g_options));
1386
1387 return 0;
1388}
1389#else
1390#define pxafb_setup_options() (0)
1391
1392module_param_string(options, g_options, sizeof(g_options), 0);
1393MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1394#endif
1395
1396#else
1397#define pxafb_parse_options(...) (0)
1398#define pxafb_setup_options() (0)
1da177e4
LT		 1399#endif
1400
ac2bf5bd 1401static int __init pxafb_probe(struct platform_device *dev)
1da177e4
LT		 1402{
1403 struct pxafb_info *fbi;
1404 struct pxafb_mach_info *inf;
ce4fb7b8 1405 struct resource *r;
1406 int irq, ret;
1da177e4 1407
2cbbb3b5 1408 dev_dbg(&dev->dev, "pxafb_probe\n");
1da177e4 1409
3ae5eaec 1410 inf = dev->dev.platform_data;
1da177e4
LT		 1411 ret = -ENOMEM;
1412 fbi = NULL;
1413 if (!inf)
1414 goto failed;
1415
3ae5eaec 1416 ret = pxafb_parse_options(&dev->dev, g_options);
1da177e4
LT		 1417 if (ret < 0)
1418 goto failed;
1da177e4
LT		 1419
1420#ifdef DEBUG_VAR
b0086efb 1421 /* Check for various illegal bit-combinations. Currently only
1da177e4
LT		 1422 * a warning is given. */
1423
b0086efb 1424 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1425 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1426 "illegal bits: %08x\n",
1427 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1428 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1429 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1430 "illegal bits: %08x\n",
1431 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1432 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1433 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1434 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1435 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
b0086efb 1436 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1437 "only valid in passive mono"
1438 " single panel mode\n");
1439 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1440 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
b0086efb 1441 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1442 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1443 (inf->modes->upper_margin || inf->modes->lower_margin))
1444 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1445 "passive mode\n");
1da177e4
LT		 1446#endif
1447
b0086efb 1448 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1449 inf->modes->xres,
1450 inf->modes->yres,
1451 inf->modes->bpp);
1452 if (inf->modes->xres == 0 ||
1453 inf->modes->yres == 0 ||
1454 inf->modes->bpp == 0) {
3ae5eaec 1455 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1456 ret = -EINVAL;
1457 goto failed;
1458 }
1459 pxafb_backlight_power = inf->pxafb_backlight_power;
1460 pxafb_lcd_power = inf->pxafb_lcd_power;
3ae5eaec 1461 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1462 if (!fbi) {
b0086efb 1463 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1464 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1465 ret = -ENOMEM;
1da177e4
LT		 1466 goto failed;
1467 }
1468
ce4fb7b8 1469 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1470 if (r == NULL) {
1471 dev_err(&dev->dev, "no I/O memory resource defined\n");
1472 ret = -ENODEV;
1473 goto failed;
1474 }
1475
1476 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1477 if (r == NULL) {
1478 dev_err(&dev->dev, "failed to request I/O memory\n");
1479 ret = -EBUSY;
1480 goto failed;
1481 }
1482
1483 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1484 if (fbi->mmio_base == NULL) {
1485 dev_err(&dev->dev, "failed to map I/O memory\n");
1486 ret = -EBUSY;
1487 goto failed_free_res;
1488 }
1489
1da177e4
LT		 1490 /* Initialize video memory */
1491 ret = pxafb_map_video_memory(fbi);
1492 if (ret) {
3ae5eaec 1493 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1494 ret = -ENOMEM;
ce4fb7b8 1495 goto failed_free_io;
1da177e4 1496 }
1da177e4 1497
ce4fb7b8 1498 irq = platform_get_irq(dev, 0);
1499 if (irq < 0) {
1500 dev_err(&dev->dev, "no IRQ defined\n");
1501 ret = -ENODEV;
1502 goto failed_free_mem;
1503 }
1504
1505 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1506 if (ret) {
3ae5eaec 1507 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1508 ret = -EBUSY;
ce4fb7b8 1509 goto failed_free_mem;
1da177e4
LT		 1510 }
1511
1512 /*
1513 * This makes sure that our colour bitfield
1514 * descriptors are correctly initialised.
1515 */
1516 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1517 pxafb_set_par(&fbi->fb);
1518
3ae5eaec 1519 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1520
1521 ret = register_framebuffer(&fbi->fb);
1522 if (ret < 0) {
b0086efb 1523 dev_err(&dev->dev,
1524 "Failed to register framebuffer device: %d\n", ret);
ce4fb7b8 1525 goto failed_free_irq;
1da177e4
LT		 1526 }
1527
1da177e4
LT		 1528#ifdef CONFIG_CPU_FREQ
1529 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1530 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1531 cpufreq_register_notifier(&fbi->freq_transition,
1532 CPUFREQ_TRANSITION_NOTIFIER);
1533 cpufreq_register_notifier(&fbi->freq_policy,
1534 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1535#endif
1536
1537 /*
1538 * Ok, now enable the LCD controller
1539 */
1540 set_ctrlr_state(fbi, C_ENABLE);
1541
1542 return 0;
1543
ce4fb7b8 1544failed_free_irq:
1545 free_irq(irq, fbi);
1546failed_free_res:
1547 release_mem_region(r->start, r->end - r->start + 1);
1548failed_free_io:
1549 iounmap(fbi->mmio_base);
1550failed_free_mem:
1551 dma_free_writecombine(&dev->dev, fbi->map_size,
1552 fbi->map_cpu, fbi->map_dma);
1da177e4 1553failed:
3ae5eaec 1554 platform_set_drvdata(dev, NULL);
1da177e4
LT		 1555 kfree(fbi);
1556 return ret;
1557}
1558
3ae5eaec 1559static struct platform_driver pxafb_driver = {
1da177e4 1560 .probe = pxafb_probe,
1da177e4
LT		 1561 .suspend = pxafb_suspend,
1562 .resume = pxafb_resume,
3ae5eaec
RK		 1563 .driver = {
1564 .name = "pxa2xx-fb",
1565 },
1da177e4
LT		 1566};
1567
ac2bf5bd 1568static int __devinit pxafb_init(void)
1da177e4 1569{
92ac73c1 1570 if (pxafb_setup_options())
1571 return -EINVAL;
1da177e4 1572
3ae5eaec 1573 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1574}
1575
1576module_init(pxafb_init);
1577
1578MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1579MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)