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[ARM] pxafb: cleanup of the timing checking code
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
27ac792c 33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/fb.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37#include <linux/ioport.h>
38#include <linux/cpufreq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4 40#include <linux/dma-mapping.h>
72e3524c
RK		 41#include <linux/clk.h>
42#include <linux/err.h>
2ba162b9 43#include <linux/completion.h>
b91dbce5 44#include <linux/mutex.h>
3c42a449
EM		 45#include <linux/kthread.h>
46#include <linux/freezer.h>
1da177e4 47
a09e64fb 48#include <mach/hardware.h>
1da177e4
LT		 49#include <asm/io.h>
50#include <asm/irq.h>
bf1b8ab6 51#include <asm/div64.h>
a09e64fb 52#include <mach/pxa-regs.h>
a09e64fb
RK		 53#include <mach/bitfield.h>
54#include <mach/pxafb.h>
1da177e4
LT		 55
56/*
57 * Complain if VAR is out of range.
58 */
59#define DEBUG_VAR 1
60
61#include "pxafb.h"
62
63/* Bits which should not be set in machine configuration structures */
b0086efb 64#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67
68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
878f5783 69 LCCR3_PCD | LCCR3_BPP(0xf))
1da177e4 70
b0086efb 71static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 struct pxafb_info *);
1da177e4 73static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
6e354846 74static void setup_base_frame(struct pxafb_info *fbi, int branch);
1da177e4 75
77e19675
EM		 76static unsigned long video_mem_size = 0;
77
a7535ba7
EM		 78static inline unsigned long
79lcd_readl(struct pxafb_info *fbi, unsigned int off)
80{
81 return __raw_readl(fbi->mmio_base + off);
82}
83
84static inline void
85lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
86{
87 __raw_writel(val, fbi->mmio_base + off);
88}
89
1da177e4
LT		 90static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
91{
92 unsigned long flags;
93
94 local_irq_save(flags);
95 /*
96 * We need to handle two requests being made at the same time.
97 * There are two important cases:
b0086efb 98 * 1. When we are changing VT (C_REENABLE) while unblanking
99 * (C_ENABLE) We must perform the unblanking, which will
100 * do our REENABLE for us.
101 * 2. When we are blanking, but immediately unblank before
102 * we have blanked. We do the "REENABLE" thing here as
103 * well, just to be sure.
1da177e4
LT		 104 */
105 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
106 state = (u_int) -1;
107 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
108 state = C_REENABLE;
109
110 if (state != (u_int)-1) {
111 fbi->task_state = state;
112 schedule_work(&fbi->task);
113 }
114 local_irq_restore(flags);
115}
116
117static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
118{
119 chan &= 0xffff;
120 chan >>= 16 - bf->length;
121 return chan << bf->offset;
122}
123
124static int
125pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
126 u_int trans, struct fb_info *info)
127{
128 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 129 u_int val;
130
131 if (regno >= fbi->palette_size)
132 return 1;
133
134 if (fbi->fb.var.grayscale) {
135 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
136 return 0;
137 }
138
139 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
140 case LCCR4_PAL_FOR_0:
141 val = ((red >> 0) & 0xf800);
142 val |= ((green >> 5) & 0x07e0);
143 val |= ((blue >> 11) & 0x001f);
1da177e4 144 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 145 break;
146 case LCCR4_PAL_FOR_1:
147 val = ((red << 8) & 0x00f80000);
148 val |= ((green >> 0) & 0x0000fc00);
149 val |= ((blue >> 8) & 0x000000f8);
b0086efb 150 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 151 break;
152 case LCCR4_PAL_FOR_2:
153 val = ((red << 8) & 0x00fc0000);
154 val |= ((green >> 0) & 0x0000fc00);
155 val |= ((blue >> 8) & 0x000000fc);
b0086efb 156 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 157 break;
a0427509
EM		 158 case LCCR4_PAL_FOR_3:
159 val = ((red << 8) & 0x00ff0000);
160 val |= ((green >> 0) & 0x0000ff00);
161 val |= ((blue >> 8) & 0x000000ff);
162 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 break;
1da177e4 164 }
9ffa7396
HK		 165
166 return 0;
1da177e4
LT		 167}
168
169static int
170pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
171 u_int trans, struct fb_info *info)
172{
173 struct pxafb_info *fbi = (struct pxafb_info *)info;
174 unsigned int val;
175 int ret = 1;
176
177 /*
178 * If inverse mode was selected, invert all the colours
179 * rather than the register number. The register number
180 * is what you poke into the framebuffer to produce the
181 * colour you requested.
182 */
183 if (fbi->cmap_inverse) {
184 red = 0xffff - red;
185 green = 0xffff - green;
186 blue = 0xffff - blue;
187 }
188
189 /*
190 * If greyscale is true, then we convert the RGB value
191 * to greyscale no matter what visual we are using.
192 */
193 if (fbi->fb.var.grayscale)
194 red = green = blue = (19595 * red + 38470 * green +
195 7471 * blue) >> 16;
196
197 switch (fbi->fb.fix.visual) {
198 case FB_VISUAL_TRUECOLOR:
199 /*
200 * 16-bit True Colour. We encode the RGB value
201 * according to the RGB bitfield information.
202 */
203 if (regno < 16) {
204 u32 *pal = fbi->fb.pseudo_palette;
205
206 val = chan_to_field(red, &fbi->fb.var.red);
207 val |= chan_to_field(green, &fbi->fb.var.green);
208 val |= chan_to_field(blue, &fbi->fb.var.blue);
209
210 pal[regno] = val;
211 ret = 0;
212 }
213 break;
214
215 case FB_VISUAL_STATIC_PSEUDOCOLOR:
216 case FB_VISUAL_PSEUDOCOLOR:
217 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
218 break;
219 }
220
221 return ret;
222}
223
878f5783
EM		 224/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
225static inline int var_to_depth(struct fb_var_screeninfo *var)
1da177e4 226{
878f5783
EM		 227 return var->red.length + var->green.length +
228 var->blue.length + var->transp.length;
229}
230
231/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
232static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
233{
234 int bpp = -EINVAL;
235
b0086efb 236 switch (var->bits_per_pixel) {
878f5783
EM		 237 case 1: bpp = 0; break;
238 case 2: bpp = 1; break;
239 case 4: bpp = 2; break;
240 case 8: bpp = 3; break;
241 case 16: bpp = 4; break;
c1450f15 242 case 24:
878f5783
EM		 243 switch (var_to_depth(var)) {
244 case 18: bpp = 6; break; /* 18-bits/pixel packed */
245 case 19: bpp = 8; break; /* 19-bits/pixel packed */
246 case 24: bpp = 9; break;
c1450f15
SS		 247 }
248 break;
249 case 32:
878f5783
EM		 250 switch (var_to_depth(var)) {
251 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
252 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
253 case 25: bpp = 10; break;
c1450f15
SS		 254 }
255 break;
b0086efb 256 }
878f5783
EM		 257 return bpp;
258}
259
260/*
261 * pxafb_var_to_lccr3():
262 * Convert a bits per pixel value to the correct bit pattern for LCCR3
263 *
264 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
265 * implication of the acutal use of transparency bit, which we handle it
266 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
267 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
268 *
269 * Transparency for palette pixel formats is not supported at the moment.
270 */
271static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
272{
273 int bpp = pxafb_var_to_bpp(var);
274 uint32_t lccr3;
275
276 if (bpp < 0)
277 return 0;
278
279 lccr3 = LCCR3_BPP(bpp);
280
281 switch (var_to_depth(var)) {
282 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
283 case 18: lccr3 |= LCCR3_PDFOR_3; break;
284 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
285 break;
286 case 19:
287 case 25: lccr3 |= LCCR3_PDFOR_0; break;
288 }
289 return lccr3;
290}
291
292#define SET_PIXFMT(v, r, g, b, t) \
293({ \
294 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
295 (v)->transp.length = (t) ? (t) : 0; \
296 (v)->blue.length = (b); (v)->blue.offset = 0; \
297 (v)->green.length = (g); (v)->green.offset = (b); \
298 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
299})
300
301/* set the RGBT bitfields of fb_var_screeninf according to
302 * var->bits_per_pixel and given depth
303 */
304static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
305{
306 if (depth == 0)
307 depth = var->bits_per_pixel;
308
309 if (var->bits_per_pixel < 16) {
310 /* indexed pixel formats */
311 var->red.offset = 0; var->red.length = 8;
312 var->green.offset = 0; var->green.length = 8;
313 var->blue.offset = 0; var->blue.length = 8;
314 var->transp.offset = 0; var->transp.length = 8;
315 }
316
317 switch (depth) {
318 case 16: var->transp.length ?
319 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
320 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
321 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
322 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
323 case 24: var->transp.length ?
324 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
325 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
326 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
327 }
1da177e4
LT		 328}
329
330#ifdef CONFIG_CPU_FREQ
331/*
332 * pxafb_display_dma_period()
333 * Calculate the minimum period (in picoseconds) between two DMA
334 * requests for the LCD controller. If we hit this, it means we're
335 * doing nothing but LCD DMA.
336 */
337static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
338{
b0086efb 339 /*
340 * Period = pixclock * bits_per_byte * bytes_per_transfer
341 * / memory_bits_per_pixel;
342 */
343 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 344}
1da177e4
LT		 345#endif
346
d14b272b
RP		 347/*
348 * Select the smallest mode that allows the desired resolution to be
349 * displayed. If desired parameters can be rounded up.
350 */
b0086efb 351static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
352 struct fb_var_screeninfo *var)
d14b272b
RP		 353{
354 struct pxafb_mode_info *mode = NULL;
355 struct pxafb_mode_info *modelist = mach->modes;
356 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
357 unsigned int i;
358
b0086efb 359 for (i = 0; i < mach->num_modes; i++) {
360 if (modelist[i].xres >= var->xres &&
361 modelist[i].yres >= var->yres &&
362 modelist[i].xres < best_x &&
363 modelist[i].yres < best_y &&
364 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 365 best_x = modelist[i].xres;
366 best_y = modelist[i].yres;
367 mode = &modelist[i];
368 }
369 }
370
371 return mode;
372}
373
b0086efb 374static void pxafb_setmode(struct fb_var_screeninfo *var,
375 struct pxafb_mode_info *mode)
d14b272b
RP		 376{
377 var->xres = mode->xres;
378 var->yres = mode->yres;
379 var->bits_per_pixel = mode->bpp;
380 var->pixclock = mode->pixclock;
381 var->hsync_len = mode->hsync_len;
382 var->left_margin = mode->left_margin;
383 var->right_margin = mode->right_margin;
384 var->vsync_len = mode->vsync_len;
385 var->upper_margin = mode->upper_margin;
386 var->lower_margin = mode->lower_margin;
387 var->sync = mode->sync;
388 var->grayscale = mode->cmap_greyscale;
878f5783
EM		 389
390 /* set the initial RGBA bitfields */
391 pxafb_set_pixfmt(var, mode->depth);
d14b272b
RP		 392}
393
3f16ff60
EM		 394static int pxafb_adjust_timing(struct pxafb_info *fbi,
395 struct fb_var_screeninfo *var)
396{
397 int line_length;
398
399 var->xres = max_t(int, var->xres, MIN_XRES);
400 var->yres = max_t(int, var->yres, MIN_YRES);
401
402 if (!(fbi->lccr0 & LCCR0_LCDT)) {
403 clamp_val(var->hsync_len, 1, 64);
404 clamp_val(var->vsync_len, 1, 64);
405 clamp_val(var->left_margin, 1, 255);
406 clamp_val(var->right_margin, 1, 255);
407 clamp_val(var->upper_margin, 1, 255);
408 clamp_val(var->lower_margin, 1, 255);
409 }
410
411 /* make sure each line is aligned on word boundary */
412 line_length = var->xres * var->bits_per_pixel / 8;
413 line_length = ALIGN(line_length, 4);
414 var->xres = line_length * 8 / var->bits_per_pixel;
415
416 /* we don't support xpan, force xres_virtual to be equal to xres */
417 var->xres_virtual = var->xres;
418
419 if (var->accel_flags & FB_ACCELF_TEXT)
420 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
421 else
422 var->yres_virtual = max(var->yres_virtual, var->yres);
423
424 /* check for limits */
425 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
426 return -EINVAL;
427
428 if (var->yres > var->yres_virtual)
429 return -EINVAL;
430
431 return 0;
432}
433
1da177e4
LT		 434/*
435 * pxafb_check_var():
436 * Get the video params out of 'var'. If a value doesn't fit, round it up,
437 * if it's too big, return -EINVAL.
438 *
439 * Round up in the following order: bits_per_pixel, xres,
440 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
441 * bitfields, horizontal timing, vertical timing.
442 */
443static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
444{
445 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 446 struct pxafb_mach_info *inf = fbi->dev->platform_data;
878f5783 447 int err;
1da177e4 448
d14b272b
RP		 449 if (inf->fixed_modes) {
450 struct pxafb_mode_info *mode;
451
452 mode = pxafb_getmode(inf, var);
453 if (!mode)
454 return -EINVAL;
455 pxafb_setmode(var, mode);
d14b272b
RP		 456 }
457
878f5783
EM		 458 /* do a test conversion to BPP fields to check the color formats */
459 err = pxafb_var_to_bpp(var);
460 if (err < 0)
461 return err;
c1450f15 462
878f5783 463 pxafb_set_pixfmt(var, var_to_depth(var));
1da177e4 464
3f16ff60
EM		 465 err = pxafb_adjust_timing(fbi, var);
466 if (err)
467 return err;
468
1da177e4 469#ifdef CONFIG_CPU_FREQ
78d3cfd3
RK		 470 pr_debug("pxafb: dma period = %d ps\n",
471 pxafb_display_dma_period(var));
1da177e4
LT		 472#endif
473
474 return 0;
475}
476
1da177e4
LT		 477/*
478 * pxafb_set_par():
479 * Set the user defined part of the display for the specified console
480 */
481static int pxafb_set_par(struct fb_info *info)
482{
483 struct pxafb_info *fbi = (struct pxafb_info *)info;
484 struct fb_var_screeninfo *var = &info->var;
1da177e4 485
c1450f15 486 if (var->bits_per_pixel >= 16)
1da177e4
LT		 487 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
488 else if (!fbi->cmap_static)
489 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
490 else {
491 /*
492 * Some people have weird ideas about wanting static
493 * pseudocolor maps. I suspect their user space
494 * applications are broken.
495 */
496 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
497 }
498
499 fbi->fb.fix.line_length = var->xres_virtual *
500 var->bits_per_pixel / 8;
c1450f15 501 if (var->bits_per_pixel >= 16)
1da177e4
LT		 502 fbi->palette_size = 0;
503 else
b0086efb 504 fbi->palette_size = var->bits_per_pixel == 1 ?
505 4 : 1 << var->bits_per_pixel;
1da177e4 506
2c42dd8e 507 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4 508
c1450f15 509 if (fbi->fb.var.bits_per_pixel >= 16)
1da177e4
LT		 510 fb_dealloc_cmap(&fbi->fb.cmap);
511 else
512 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
513
514 pxafb_activate_var(var, fbi);
515
516 return 0;
517}
518
6e354846
EM		 519static int pxafb_pan_display(struct fb_var_screeninfo *var,
520 struct fb_info *info)
521{
522 struct pxafb_info *fbi = (struct pxafb_info *)info;
523 int dma = DMA_MAX + DMA_BASE;
524
525 if (fbi->state != C_ENABLE)
526 return 0;
527
528 setup_base_frame(fbi, 1);
529
530 if (fbi->lccr0 & LCCR0_SDS)
531 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
532
533 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
534 return 0;
535}
536
1da177e4
LT		 537/*
538 * pxafb_blank():
539 * Blank the display by setting all palette values to zero. Note, the
540 * 16 bpp mode does not really use the palette, so this will not
541 * blank the display in all modes.
542 */
543static int pxafb_blank(int blank, struct fb_info *info)
544{
545 struct pxafb_info *fbi = (struct pxafb_info *)info;
546 int i;
547
1da177e4
LT		 548 switch (blank) {
549 case FB_BLANK_POWERDOWN:
550 case FB_BLANK_VSYNC_SUSPEND:
551 case FB_BLANK_HSYNC_SUSPEND:
552 case FB_BLANK_NORMAL:
553 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
554 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
555 for (i = 0; i < fbi->palette_size; i++)
556 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
557
558 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 559 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 560 break;
561
562 case FB_BLANK_UNBLANK:
b0086efb 563 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 564 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
565 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
566 fb_set_cmap(&fbi->fb.cmap, info);
567 pxafb_schedule_work(fbi, C_ENABLE);
568 }
569 return 0;
570}
571
1da177e4
LT		 572static struct fb_ops pxafb_ops = {
573 .owner = THIS_MODULE,
574 .fb_check_var = pxafb_check_var,
575 .fb_set_par = pxafb_set_par,
6e354846 576 .fb_pan_display = pxafb_pan_display,
1da177e4
LT		 577 .fb_setcolreg = pxafb_setcolreg,
578 .fb_fillrect = cfb_fillrect,
579 .fb_copyarea = cfb_copyarea,
580 .fb_imageblit = cfb_imageblit,
581 .fb_blank = pxafb_blank,
1da177e4
LT		 582};
583
584/*
585 * Calculate the PCD value from the clock rate (in picoseconds).
586 * We take account of the PPCR clock setting.
587 * From PXA Developer's Manual:
588 *
589 * PixelClock = LCLK
590 * -------------
591 * 2 ( PCD + 1 )
592 *
593 * PCD = LCLK
594 * ------------- - 1
595 * 2(PixelClock)
596 *
597 * Where:
598 * LCLK = LCD/Memory Clock
599 * PCD = LCCR3[7:0]
600 *
601 * PixelClock here is in Hz while the pixclock argument given is the
602 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
603 *
604 * The function get_lclk_frequency_10khz returns LCLK in units of
605 * 10khz. Calling the result of this function lclk gives us the
606 * following
607 *
608 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
609 * -------------------------------------- - 1
610 * 2
611 *
612 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
613 */
b0086efb 614static inline unsigned int get_pcd(struct pxafb_info *fbi,
615 unsigned int pixclock)
1da177e4
LT		 616{
617 unsigned long long pcd;
618
619 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 620 * (DPC) bit? or perhaps set it based on the various clock
621 * speeds */
622 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
623 pcd *= pixclock;
bf1b8ab6 624 do_div(pcd, 100000000 * 2);
1da177e4
LT		 625 /* no need for this, since we should subtract 1 anyway. they cancel */
626 /* pcd += 1; */ /* make up for integer math truncations */
627 return (unsigned int)pcd;
628}
629
ba44cd2d
RP		 630/*
631 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 632 * function correctly. We export it here. Note that 'hsync_time' and
633 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
634 * of the hsync period in seconds.
ba44cd2d
RP		 635 */
636static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
637{
72e3524c 638 unsigned long htime;
ba44cd2d
RP		 639
640 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 641 fbi->hsync_time = 0;
ba44cd2d
RP		 642 return;
643 }
644
72e3524c
RK		 645 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
646
ba44cd2d
RP		 647 fbi->hsync_time = htime;
648}
649
650unsigned long pxafb_get_hsync_time(struct device *dev)
651{
652 struct pxafb_info *fbi = dev_get_drvdata(dev);
653
654 /* If display is blanked/suspended, hsync isn't active */
655 if (!fbi || (fbi->state != C_ENABLE))
656 return 0;
657
658 return fbi->hsync_time;
659}
660EXPORT_SYMBOL(pxafb_get_hsync_time);
661
2c42dd8e 662static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
663 unsigned int offset, size_t size)
664{
665 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
666 unsigned int dma_desc_off, pal_desc_off;
667
6e354846 668 if (dma < 0 || dma >= DMA_MAX * 2)
2c42dd8e 669 return -EINVAL;
670
671 dma_desc = &fbi->dma_buff->dma_desc[dma];
672 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
673
77e19675 674 dma_desc->fsadr = fbi->video_mem_phys + offset;
2c42dd8e 675 dma_desc->fidr = 0;
676 dma_desc->ldcmd = size;
677
6e354846 678 if (pal < 0 || pal >= PAL_MAX * 2) {
2c42dd8e 679 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
680 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
681 } else {
62cfcf4f
JS		 682 pal_desc = &fbi->dma_buff->pal_desc[pal];
683 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
2c42dd8e 684
685 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
686 pal_desc->fidr = 0;
687
688 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
689 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
690 else
691 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
692
693 pal_desc->ldcmd |= LDCMD_PAL;
694
695 /* flip back and forth between palette and frame buffer */
696 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
697 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
698 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
699 }
700
701 return 0;
702}
703
6e354846
EM		 704static void setup_base_frame(struct pxafb_info *fbi, int branch)
705{
706 struct fb_var_screeninfo *var = &fbi->fb.var;
707 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
708 unsigned int nbytes, offset;
709 int dma, pal, bpp = var->bits_per_pixel;
710
711 dma = DMA_BASE + (branch ? DMA_MAX : 0);
712 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
713
714 nbytes = fix->line_length * var->yres;
715 offset = fix->line_length * var->yoffset;
716
717 if (fbi->lccr0 & LCCR0_SDS) {
718 nbytes = nbytes / 2;
719 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
720 }
721
722 setup_frame_dma(fbi, dma, pal, offset, nbytes);
723}
724
3c42a449
EM		 725#ifdef CONFIG_FB_PXA_SMARTPANEL
726static int setup_smart_dma(struct pxafb_info *fbi)
727{
728 struct pxafb_dma_descriptor *dma_desc;
729 unsigned long dma_desc_off, cmd_buff_off;
730
731 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
732 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
733 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
734
735 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
736 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
737 dma_desc->fidr = 0;
738 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
739
740 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
741 return 0;
742}
743
744int pxafb_smart_flush(struct fb_info *info)
745{
746 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
747 uint32_t prsr;
748 int ret = 0;
749
750 /* disable controller until all registers are set up */
751 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
752
753 /* 1. make it an even number of commands to align on 32-bit boundary
754 * 2. add the interrupt command to the end of the chain so we can
755 * keep track of the end of the transfer
756 */
757
758 while (fbi->n_smart_cmds & 1)
759 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
760
761 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
762 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
763 setup_smart_dma(fbi);
764
765 /* continue to execute next command */
766 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
767 lcd_writel(fbi, PRSR, prsr);
768
769 /* stop the processor in case it executed "wait for sync" cmd */
770 lcd_writel(fbi, CMDCR, 0x0001);
771
772 /* don't send interrupts for fifo underruns on channel 6 */
773 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
774
775 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
776 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
777 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
a0427509 778 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
3c42a449
EM		 779 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
780 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
781
782 /* begin sending */
783 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
784
785 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
786 pr_warning("%s: timeout waiting for command done\n",
787 __func__);
788 ret = -ETIMEDOUT;
789 }
790
791 /* quick disable */
792 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
793 lcd_writel(fbi, PRSR, prsr);
794 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
795 lcd_writel(fbi, FDADR6, 0);
796 fbi->n_smart_cmds = 0;
797 return ret;
798}
799
800int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
801{
802 int i;
803 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
804
69bdea70
EM		 805 for (i = 0; i < n_cmds; i++, cmds++) {
806 /* if it is a software delay, flush and delay */
807 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
808 pxafb_smart_flush(info);
809 mdelay(*cmds & 0xff);
810 continue;
811 }
812
813 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
3c42a449
EM		 814 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
815 pxafb_smart_flush(info);
816
69bdea70 817 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
3c42a449
EM		 818 }
819
820 return 0;
821}
822
823static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
824{
825 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
826 return (t == 0) ? 1 : t;
827}
828
829static void setup_smart_timing(struct pxafb_info *fbi,
830 struct fb_var_screeninfo *var)
831{
832 struct pxafb_mach_info *inf = fbi->dev->platform_data;
833 struct pxafb_mode_info *mode = &inf->modes[0];
834 unsigned long lclk = clk_get_rate(fbi->clk);
835 unsigned t1, t2, t3, t4;
836
837 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
838 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
839 t3 = mode->op_hold_time;
840 t4 = mode->cmd_inh_time;
841
842 fbi->reg_lccr1 =
843 LCCR1_DisWdth(var->xres) |
844 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
845 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
846 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
847
848 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
c1f99c21
EM		 849 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
850 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
851 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
3c42a449
EM		 852
853 /* FIXME: make this configurable */
854 fbi->reg_cmdcr = 1;
855}
856
857static int pxafb_smart_thread(void *arg)
858{
7f1133cb 859 struct pxafb_info *fbi = arg;
3c42a449
EM		 860 struct pxafb_mach_info *inf = fbi->dev->platform_data;
861
862 if (!fbi || !inf->smart_update) {
863 pr_err("%s: not properly initialized, thread terminated\n",
864 __func__);
865 return -EINVAL;
866 }
867
868 pr_debug("%s(): task starting\n", __func__);
869
870 set_freezable();
871 while (!kthread_should_stop()) {
872
873 if (try_to_freeze())
874 continue;
875
07f651c7
EM		 876 mutex_lock(&fbi->ctrlr_lock);
877
3c42a449
EM		 878 if (fbi->state == C_ENABLE) {
879 inf->smart_update(&fbi->fb);
880 complete(&fbi->refresh_done);
881 }
882
07f651c7
EM		 883 mutex_unlock(&fbi->ctrlr_lock);
884
3c42a449
EM		 885 set_current_state(TASK_INTERRUPTIBLE);
886 schedule_timeout(30 * HZ / 1000);
887 }
888
889 pr_debug("%s(): task ending\n", __func__);
890 return 0;
891}
892
893static int pxafb_smart_init(struct pxafb_info *fbi)
894{
07df1c4f 895 if (!(fbi->lccr0 & LCCR0_LCDT))
6cc4abe4
EM		 896 return 0;
897
07df1c4f
EM		 898 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
899 fbi->n_smart_cmds = 0;
900
901 init_completion(&fbi->command_done);
902 init_completion(&fbi->refresh_done);
903
3c42a449
EM		 904 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
905 "lcd_refresh");
906 if (IS_ERR(fbi->smart_thread)) {
07df1c4f 907 pr_err("%s: unable to create kernel thread\n", __func__);
3c42a449
EM		 908 return PTR_ERR(fbi->smart_thread);
909 }
a5718a14 910
3c42a449
EM		 911 return 0;
912}
913#else
914int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
915{
916 return 0;
917}
918
919int pxafb_smart_flush(struct fb_info *info)
920{
921 return 0;
922}
07df1c4f
EM		 923
924static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
925#endif /* CONFIG_FB_PXA_SMARTPANEL */
3c42a449 926
90eabbf0
EM		 927static void setup_parallel_timing(struct pxafb_info *fbi,
928 struct fb_var_screeninfo *var)
929{
930 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
931
932 fbi->reg_lccr1 =
933 LCCR1_DisWdth(var->xres) +
934 LCCR1_HorSnchWdth(var->hsync_len) +
935 LCCR1_BegLnDel(var->left_margin) +
936 LCCR1_EndLnDel(var->right_margin);
937
938 /*
939 * If we have a dual scan LCD, we need to halve
940 * the YRES parameter.
941 */
942 lines_per_panel = var->yres;
943 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
944 lines_per_panel /= 2;
945
946 fbi->reg_lccr2 =
947 LCCR2_DisHght(lines_per_panel) +
948 LCCR2_VrtSnchWdth(var->vsync_len) +
949 LCCR2_BegFrmDel(var->upper_margin) +
950 LCCR2_EndFrmDel(var->lower_margin);
951
952 fbi->reg_lccr3 = fbi->lccr3 |
953 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
954 LCCR3_HorSnchH : LCCR3_HorSnchL) |
955 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
956 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
957
958 if (pcd) {
959 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
960 set_hsync_time(fbi, pcd);
961 }
962}
963
1da177e4
LT		 964/*
965 * pxafb_activate_var():
b0086efb 966 * Configures LCD Controller based on entries in var parameter.
967 * Settings are only written to the controller if changes were made.
1da177e4 968 */
b0086efb 969static int pxafb_activate_var(struct fb_var_screeninfo *var,
970 struct pxafb_info *fbi)
1da177e4 971{
1da177e4 972 u_long flags;
1da177e4 973
90eabbf0
EM		 974 /* Update shadow copy atomically */
975 local_irq_save(flags);
1da177e4 976
3c42a449
EM		 977#ifdef CONFIG_FB_PXA_SMARTPANEL
978 if (fbi->lccr0 & LCCR0_LCDT)
979 setup_smart_timing(fbi, var);
980 else
981#endif
982 setup_parallel_timing(fbi, var);
90eabbf0 983
6e354846
EM		 984 setup_base_frame(fbi, 0);
985
90eabbf0 986 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 987 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 988 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 989
878f5783 990 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1da177e4 991
a7535ba7 992 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 993 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 994 local_irq_restore(flags);
995
996 /*
997 * Only update the registers if the controller is enabled
998 * and something has changed.
999 */
a7535ba7
EM		 1000 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1001 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1002 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1003 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
a0427509 1004 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
a7535ba7
EM		 1005 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1006 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 1007 pxafb_schedule_work(fbi, C_REENABLE);
1008
1009 return 0;
1010}
1011
1012/*
1013 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1014 * Do not call them directly; set_ctrlr_state does the correct serialisation
1015 * to ensure that things happen in the right way 100% of time time.
1016 * -- rmk
1017 */
1018static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1019{
ca5da710 1020 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 1021
a5718a14
EM		 1022 if (fbi->backlight_power)
1023 fbi->backlight_power(on);
1da177e4
LT		 1024}
1025
1026static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1027{
ca5da710 1028 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4 1029
a5718a14
EM		 1030 if (fbi->lcd_power)
1031 fbi->lcd_power(on, &fbi->fb.var);
1da177e4
LT		 1032}
1033
1da177e4
LT		 1034static void pxafb_enable_controller(struct pxafb_info *fbi)
1035{
ca5da710 1036 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 1037 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1038 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 1039 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1040 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1041 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1042 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 1043
8d372266 1044 /* enable LCD controller clock */
72e3524c 1045 clk_enable(fbi->clk);
8d372266 1046
3c42a449
EM		 1047 if (fbi->lccr0 & LCCR0_LCDT)
1048 return;
1049
1da177e4 1050 /* Sequence from 11.7.10 */
a0427509 1051 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
a7535ba7
EM		 1052 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1053 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1054 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1055 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1056
1057 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1058 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1059 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1060}
1061
1062static void pxafb_disable_controller(struct pxafb_info *fbi)
1063{
ce4fb7b8 1064 uint32_t lccr0;
1065
3c42a449
EM		 1066#ifdef CONFIG_FB_PXA_SMARTPANEL
1067 if (fbi->lccr0 & LCCR0_LCDT) {
1068 wait_for_completion_timeout(&fbi->refresh_done,
1069 200 * HZ / 1000);
1070 return;
1071 }
1072#endif
1073
ce4fb7b8 1074 /* Clear LCD Status Register */
a7535ba7 1075 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1076
a7535ba7
EM		 1077 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1078 lcd_writel(fbi, LCCR0, lccr0);
1079 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1080
2ba162b9 1081 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1082
1083 /* disable LCD controller clock */
72e3524c 1084 clk_disable(fbi->clk);
1da177e4
LT		 1085}
1086
1087/*
1088 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1089 */
7d12e780 1090static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1091{
1092 struct pxafb_info *fbi = dev_id;
a7535ba7 1093 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 1094
1095 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1096 lccr0 = lcd_readl(fbi, LCCR0);
1097 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1098 complete(&fbi->disable_done);
1da177e4
LT		 1099 }
1100
3c42a449
EM		 1101#ifdef CONFIG_FB_PXA_SMARTPANEL
1102 if (lcsr & LCSR_CMD_INT)
1103 complete(&fbi->command_done);
1104#endif
1105
a7535ba7 1106 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 1107 return IRQ_HANDLED;
1108}
1109
1110/*
1111 * This function must be called from task context only, since it will
1112 * sleep when disabling the LCD controller, or if we get two contending
1113 * processes trying to alter state.
1114 */
1115static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1116{
1117 u_int old_state;
1118
b91dbce5 1119 mutex_lock(&fbi->ctrlr_lock);
1da177e4
LT		 1120
1121 old_state = fbi->state;
1122
1123 /*
1124 * Hack around fbcon initialisation.
1125 */
1126 if (old_state == C_STARTUP && state == C_REENABLE)
1127 state = C_ENABLE;
1128
1129 switch (state) {
1130 case C_DISABLE_CLKCHANGE:
1131 /*
1132 * Disable controller for clock change. If the
1133 * controller is already disabled, then do nothing.
1134 */
1135 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1136 fbi->state = state;
b0086efb 1137 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1138 pxafb_disable_controller(fbi);
1139 }
1140 break;
1141
1142 case C_DISABLE_PM:
1143 case C_DISABLE:
1144 /*
1145 * Disable controller
1146 */
1147 if (old_state != C_DISABLE) {
1148 fbi->state = state;
1149 __pxafb_backlight_power(fbi, 0);
1150 __pxafb_lcd_power(fbi, 0);
1151 if (old_state != C_DISABLE_CLKCHANGE)
1152 pxafb_disable_controller(fbi);
1153 }
1154 break;
1155
1156 case C_ENABLE_CLKCHANGE:
1157 /*
1158 * Enable the controller after clock change. Only
1159 * do this if we were disabled for the clock change.
1160 */
1161 if (old_state == C_DISABLE_CLKCHANGE) {
1162 fbi->state = C_ENABLE;
1163 pxafb_enable_controller(fbi);
b0086efb 1164 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1165 }
1166 break;
1167
1168 case C_REENABLE:
1169 /*
1170 * Re-enable the controller only if it was already
1171 * enabled. This is so we reprogram the control
1172 * registers.
1173 */
1174 if (old_state == C_ENABLE) {
d14b272b 1175 __pxafb_lcd_power(fbi, 0);
1da177e4 1176 pxafb_disable_controller(fbi);
1da177e4 1177 pxafb_enable_controller(fbi);
d14b272b 1178 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1179 }
1180 break;
1181
1182 case C_ENABLE_PM:
1183 /*
1184 * Re-enable the controller after PM. This is not
1185 * perfect - think about the case where we were doing
1186 * a clock change, and we suspended half-way through.
1187 */
1188 if (old_state != C_DISABLE_PM)
1189 break;
1190 /* fall through */
1191
1192 case C_ENABLE:
1193 /*
1194 * Power up the LCD screen, enable controller, and
1195 * turn on the backlight.
1196 */
1197 if (old_state != C_ENABLE) {
1198 fbi->state = C_ENABLE;
1da177e4
LT		 1199 pxafb_enable_controller(fbi);
1200 __pxafb_lcd_power(fbi, 1);
1201 __pxafb_backlight_power(fbi, 1);
1202 }
1203 break;
1204 }
b91dbce5 1205 mutex_unlock(&fbi->ctrlr_lock);
1da177e4
LT		 1206}
1207
1208/*
1209 * Our LCD controller task (which is called when we blank or unblank)
1210 * via keventd.
1211 */
6d5aefb8 1212static void pxafb_task(struct work_struct *work)
1da177e4 1213{
6d5aefb8
DH		 1214 struct pxafb_info *fbi =
1215 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1216 u_int state = xchg(&fbi->task_state, -1);
1217
1218 set_ctrlr_state(fbi, state);
1219}
1220
1221#ifdef CONFIG_CPU_FREQ
1222/*
1223 * CPU clock speed change handler. We need to adjust the LCD timing
1224 * parameters when the CPU clock is adjusted by the power management
1225 * subsystem.
1226 *
1227 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1228 */
1229static int
1230pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1231{
1232 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1233 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1234 u_int pcd;
1235
1236 switch (val) {
1237 case CPUFREQ_PRECHANGE:
1238 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1239 break;
1240
1241 case CPUFREQ_POSTCHANGE:
72e3524c 1242 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1243 set_hsync_time(fbi, pcd);
b0086efb 1244 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1245 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1246 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1247 break;
1248 }
1249 return 0;
1250}
1251
1252static int
1253pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1254{
1255 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1256 struct fb_var_screeninfo *var = &fbi->fb.var;
1257 struct cpufreq_policy *policy = data;
1258
1259 switch (val) {
1260 case CPUFREQ_ADJUST:
1261 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1262 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1263 "new clock %d kHz\n", pxafb_display_dma_period(var),
1264 policy->max);
b0086efb 1265 /* TODO: fill in min/max values */
1da177e4 1266 break;
1da177e4
LT		 1267 }
1268 return 0;
1269}
1270#endif
1271
1272#ifdef CONFIG_PM
1273/*
1274 * Power management hooks. Note that we won't be called from IRQ context,
1275 * unlike the blank functions above, so we may sleep.
1276 */
3ae5eaec 1277static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1278{
3ae5eaec 1279 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1280
9480e307 1281 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1282 return 0;
1283}
1284
3ae5eaec 1285static int pxafb_resume(struct platform_device *dev)
1da177e4 1286{
3ae5eaec 1287 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1288
9480e307 1289 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1290 return 0;
1291}
1292#else
1293#define pxafb_suspend NULL
1294#define pxafb_resume NULL
1295#endif
1296
77e19675 1297static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1da177e4 1298{
77e19675 1299 int size = PAGE_ALIGN(fbi->video_mem_size);
3c42a449 1300
77e19675
EM		 1301 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1302 if (fbi->video_mem == NULL)
1303 return -ENOMEM;
1da177e4 1304
77e19675
EM		 1305 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1306 fbi->video_mem_size = size;
84f43c30 1307
77e19675
EM		 1308 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1309 fbi->fb.fix.smem_len = fbi->video_mem_size;
1310 fbi->fb.screen_base = fbi->video_mem;
84f43c30 1311
77e19675 1312 return fbi->video_mem ? 0 : -ENOMEM;
84f43c30 1313}
1314
ebdf982a
GL		 1315static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1316 struct pxafb_mach_info *inf)
84f43c30 1317{
1318 unsigned int lcd_conn = inf->lcd_conn;
77e19675
EM		 1319 struct pxafb_mode_info *m;
1320 int i;
84f43c30 1321
1322 fbi->cmap_inverse = inf->cmap_inverse;
1323 fbi->cmap_static = inf->cmap_static;
a0427509 1324 fbi->lccr4 = inf->lccr4;
84f43c30 1325
1ec26db1 1326 switch (lcd_conn & LCD_TYPE_MASK) {
84f43c30 1327 case LCD_TYPE_MONO_STN:
1328 fbi->lccr0 = LCCR0_CMS;
1329 break;
1330 case LCD_TYPE_MONO_DSTN:
1331 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1332 break;
1333 case LCD_TYPE_COLOR_STN:
1334 fbi->lccr0 = 0;
1335 break;
1336 case LCD_TYPE_COLOR_DSTN:
1337 fbi->lccr0 = LCCR0_SDS;
1338 break;
1339 case LCD_TYPE_COLOR_TFT:
1340 fbi->lccr0 = LCCR0_PAS;
1341 break;
1342 case LCD_TYPE_SMART_PANEL:
1343 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1344 break;
1345 default:
1346 /* fall back to backward compatibility way */
1347 fbi->lccr0 = inf->lccr0;
1348 fbi->lccr3 = inf->lccr3;
ebdf982a 1349 goto decode_mode;
84f43c30 1350 }
1351
1352 if (lcd_conn == LCD_MONO_STN_8BPP)
1353 fbi->lccr0 |= LCCR0_DPD;
1354
9a1ac7e4
EM		 1355 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1356
84f43c30 1357 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1358 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1359 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1360
ebdf982a 1361decode_mode:
77e19675
EM		 1362 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1363
1364 /* decide video memory size as follows:
1365 * 1. default to mode of maximum resolution
1366 * 2. allow platform to override
1367 * 3. allow module parameter to override
1368 */
1369 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1370 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1371 m->xres * m->yres * m->bpp / 8);
1372
1373 if (inf->video_mem_size > fbi->video_mem_size)
1374 fbi->video_mem_size = inf->video_mem_size;
1375
1376 if (video_mem_size > fbi->video_mem_size)
1377 fbi->video_mem_size = video_mem_size;
84f43c30 1378}
1379
9e6c2976 1380static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1da177e4
LT		 1381{
1382 struct pxafb_info *fbi;
1383 void *addr;
1384 struct pxafb_mach_info *inf = dev->platform_data;
1385
1386 /* Alloc the pxafb_info and pseudo_palette in one step */
1387 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1388 if (!fbi)
1389 return NULL;
1390
1391 memset(fbi, 0, sizeof(struct pxafb_info));
1392 fbi->dev = dev;
1393
72e3524c
RK		 1394 fbi->clk = clk_get(dev, "LCDCLK");
1395 if (IS_ERR(fbi->clk)) {
1396 kfree(fbi);
1397 return NULL;
1398 }
1399
1da177e4
LT		 1400 strcpy(fbi->fb.fix.id, PXA_NAME);
1401
1402 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1403 fbi->fb.fix.type_aux = 0;
1404 fbi->fb.fix.xpanstep = 0;
7e4b19c9 1405 fbi->fb.fix.ypanstep = 1;
1da177e4
LT		 1406 fbi->fb.fix.ywrapstep = 0;
1407 fbi->fb.fix.accel = FB_ACCEL_NONE;
1408
1409 fbi->fb.var.nonstd = 0;
1410 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1411 fbi->fb.var.height = -1;
1412 fbi->fb.var.width = -1;
7e4b19c9 1413 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1da177e4
LT		 1414 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1415
1416 fbi->fb.fbops = &pxafb_ops;
1417 fbi->fb.flags = FBINFO_DEFAULT;
1418 fbi->fb.node = -1;
1419
1420 addr = fbi;
1421 addr = addr + sizeof(struct pxafb_info);
1422 fbi->fb.pseudo_palette = addr;
1423
b0086efb 1424 fbi->state = C_STARTUP;
1425 fbi->task_state = (u_char)-1;
d14b272b 1426
84f43c30 1427 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1428
1429 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1430 INIT_WORK(&fbi->task, pxafb_task);
b91dbce5 1431 mutex_init(&fbi->ctrlr_lock);
2ba162b9 1432 init_completion(&fbi->disable_done);
1da177e4
LT		 1433
1434 return fbi;
1435}
1436
1437#ifdef CONFIG_FB_PXA_PARAMETERS
9e6c2976 1438static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1439{
1440 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1441
1442 const char *name = this_opt+5;
1443 unsigned int namelen = strlen(name);
1444 int res_specified = 0, bpp_specified = 0;
1445 unsigned int xres = 0, yres = 0, bpp = 0;
1446 int yres_specified = 0;
1447 int i;
1448 for (i = namelen-1; i >= 0; i--) {
1449 switch (name[i]) {
1450 case '-':
1451 namelen = i;
1452 if (!bpp_specified && !yres_specified) {
1453 bpp = simple_strtoul(&name[i+1], NULL, 0);
1454 bpp_specified = 1;
1455 } else
1456 goto done;
1457 break;
1458 case 'x':
1459 if (!yres_specified) {
1460 yres = simple_strtoul(&name[i+1], NULL, 0);
1461 yres_specified = 1;
1462 } else
1463 goto done;
1464 break;
1465 case '0' ... '9':
1466 break;
1467 default:
1468 goto done;
1469 }
1470 }
1471 if (i < 0 && yres_specified) {
1472 xres = simple_strtoul(name, NULL, 0);
1473 res_specified = 1;
1474 }
1475done:
1476 if (res_specified) {
1477 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1478 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1479 }
1480 if (bpp_specified)
1481 switch (bpp) {
1482 case 1:
1483 case 2:
1484 case 4:
1485 case 8:
1486 case 16:
1487 inf->modes[0].bpp = bpp;
1488 dev_info(dev, "overriding bit depth: %d\n", bpp);
1489 break;
1490 default:
1491 dev_err(dev, "Depth %d is not valid\n", bpp);
1492 return -EINVAL;
1493 }
1494 return 0;
1495}
1496
9e6c2976 1497static int __devinit parse_opt(struct device *dev, char *this_opt)
817daf14 1498{
1499 struct pxafb_mach_info *inf = dev->platform_data;
1500 struct pxafb_mode_info *mode = &inf->modes[0];
1501 char s[64];
1502
1503 s[0] = '\0';
1504
77e19675
EM		 1505 if (!strncmp(this_opt, "vmem:", 5)) {
1506 video_mem_size = memparse(this_opt + 5, NULL);
1507 } else if (!strncmp(this_opt, "mode:", 5)) {
817daf14 1508 return parse_opt_mode(dev, this_opt);
1509 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1510 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1511 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1512 } else if (!strncmp(this_opt, "left:", 5)) {
1513 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1514 sprintf(s, "left: %u\n", mode->left_margin);
1515 } else if (!strncmp(this_opt, "right:", 6)) {
1516 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1517 sprintf(s, "right: %u\n", mode->right_margin);
1518 } else if (!strncmp(this_opt, "upper:", 6)) {
1519 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1520 sprintf(s, "upper: %u\n", mode->upper_margin);
1521 } else if (!strncmp(this_opt, "lower:", 6)) {
1522 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1523 sprintf(s, "lower: %u\n", mode->lower_margin);
1524 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1525 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1526 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1527 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1528 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1529 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1530 } else if (!strncmp(this_opt, "hsync:", 6)) {
1531 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1532 sprintf(s, "hsync: Active Low\n");
1533 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1534 } else {
1535 sprintf(s, "hsync: Active High\n");
1536 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1537 }
1538 } else if (!strncmp(this_opt, "vsync:", 6)) {
1539 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1540 sprintf(s, "vsync: Active Low\n");
1541 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1542 } else {
1543 sprintf(s, "vsync: Active High\n");
1544 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1545 }
1546 } else if (!strncmp(this_opt, "dpc:", 4)) {
1547 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1548 sprintf(s, "double pixel clock: false\n");
1549 inf->lccr3 &= ~LCCR3_DPC;
1550 } else {
1551 sprintf(s, "double pixel clock: true\n");
1552 inf->lccr3 |= LCCR3_DPC;
1553 }
1554 } else if (!strncmp(this_opt, "outputen:", 9)) {
1555 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1556 sprintf(s, "output enable: active low\n");
1557 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1558 } else {
1559 sprintf(s, "output enable: active high\n");
1560 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1561 }
1562 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1563 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1564 sprintf(s, "pixel clock polarity: falling edge\n");
1565 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1566 } else {
1567 sprintf(s, "pixel clock polarity: rising edge\n");
1568 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1569 }
1570 } else if (!strncmp(this_opt, "color", 5)) {
1571 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1572 } else if (!strncmp(this_opt, "mono", 4)) {
1573 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1574 } else if (!strncmp(this_opt, "active", 6)) {
1575 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1576 } else if (!strncmp(this_opt, "passive", 7)) {
1577 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1578 } else if (!strncmp(this_opt, "single", 6)) {
1579 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1580 } else if (!strncmp(this_opt, "dual", 4)) {
1581 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1582 } else if (!strncmp(this_opt, "4pix", 4)) {
1583 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1584 } else if (!strncmp(this_opt, "8pix", 4)) {
1585 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1586 } else {
1587 dev_err(dev, "unknown option: %s\n", this_opt);
1588 return -EINVAL;
1589 }
1590
1591 if (s[0] != '\0')
1592 dev_info(dev, "override %s", s);
1593
1594 return 0;
1595}
1596
9e6c2976 1597static int __devinit pxafb_parse_options(struct device *dev, char *options)
817daf14 1598{
1da177e4 1599 char *this_opt;
817daf14 1600 int ret;
1da177e4 1601
817daf14 1602 if (!options || !*options)
1603 return 0;
1da177e4
LT		 1604
1605 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1606
1607 /* could be made table driven or similar?... */
817daf14 1608 while ((this_opt = strsep(&options, ",")) != NULL) {
1609 ret = parse_opt(dev, this_opt);
1610 if (ret)
1611 return ret;
1612 }
1613 return 0;
1da177e4 1614}
92ac73c1 1615
1616static char g_options[256] __devinitdata = "";
1617
f1edfc42 1618#ifndef MODULE
9e6c2976 1619static int __init pxafb_setup_options(void)
92ac73c1 1620{
1621 char *options = NULL;
1622
1623 if (fb_get_options("pxafb", &options))
1624 return -ENODEV;
1625
1626 if (options)
1627 strlcpy(g_options, options, sizeof(g_options));
1628
1629 return 0;
1630}
1631#else
1632#define pxafb_setup_options() (0)
1633
1634module_param_string(options, g_options, sizeof(g_options), 0);
1635MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1636#endif
1637
1638#else
1639#define pxafb_parse_options(...) (0)
1640#define pxafb_setup_options() (0)
1da177e4
LT		 1641#endif
1642
1da177e4 1643#ifdef DEBUG_VAR
4f3e2664
EM		 1644/* Check for various illegal bit-combinations. Currently only
1645 * a warning is given. */
1646static void __devinit pxafb_check_options(struct device *dev,
1647 struct pxafb_mach_info *inf)
1648{
1649 if (inf->lcd_conn)
1650 return;
1da177e4 1651
b0086efb 1652 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
4f3e2664 1653 dev_warn(dev, "machine LCCR0 setting contains "
b0086efb 1654 "illegal bits: %08x\n",
1655 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1656 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
4f3e2664 1657 dev_warn(dev, "machine LCCR3 setting contains "
b0086efb 1658 "illegal bits: %08x\n",
1659 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1660 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1661 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1662 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1663 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
4f3e2664 1664 dev_warn(dev, "Double Pixel Data (DPD) mode is "
b0086efb 1665 "only valid in passive mono"
1666 " single panel mode\n");
1667 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1668 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
4f3e2664 1669 dev_warn(dev, "Dual panel only valid in passive mode\n");
b0086efb 1670 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1671 (inf->modes->upper_margin || inf->modes->lower_margin))
4f3e2664 1672 dev_warn(dev, "Upper and lower margins must be 0 in "
b0086efb 1673 "passive mode\n");
4f3e2664
EM		 1674}
1675#else
1676#define pxafb_check_options(...) do {} while (0)
1da177e4
LT		 1677#endif
1678
4f3e2664
EM		 1679static int __devinit pxafb_probe(struct platform_device *dev)
1680{
1681 struct pxafb_info *fbi;
1682 struct pxafb_mach_info *inf;
1683 struct resource *r;
1684 int irq, ret;
1685
1686 dev_dbg(&dev->dev, "pxafb_probe\n");
1687
1688 inf = dev->dev.platform_data;
1689 ret = -ENOMEM;
1690 fbi = NULL;
1691 if (!inf)
1692 goto failed;
1693
1694 ret = pxafb_parse_options(&dev->dev, g_options);
1695 if (ret < 0)
1696 goto failed;
1697
1698 pxafb_check_options(&dev->dev, inf);
1699
b0086efb 1700 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1701 inf->modes->xres,
1702 inf->modes->yres,
1703 inf->modes->bpp);
1704 if (inf->modes->xres == 0 ||
1705 inf->modes->yres == 0 ||
1706 inf->modes->bpp == 0) {
3ae5eaec 1707 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1708 ret = -EINVAL;
1709 goto failed;
1710 }
a5718a14 1711
3ae5eaec 1712 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1713 if (!fbi) {
b0086efb 1714 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1715 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1716 ret = -ENOMEM;
1da177e4
LT		 1717 goto failed;
1718 }
1719
a5718a14
EM		 1720 fbi->backlight_power = inf->pxafb_backlight_power;
1721 fbi->lcd_power = inf->pxafb_lcd_power;
1722
ce4fb7b8 1723 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1724 if (r == NULL) {
1725 dev_err(&dev->dev, "no I/O memory resource defined\n");
1726 ret = -ENODEV;
ee98476b 1727 goto failed_fbi;
ce4fb7b8 1728 }
1729
1730 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1731 if (r == NULL) {
1732 dev_err(&dev->dev, "failed to request I/O memory\n");
1733 ret = -EBUSY;
ee98476b 1734 goto failed_fbi;
ce4fb7b8 1735 }
1736
1737 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1738 if (fbi->mmio_base == NULL) {
1739 dev_err(&dev->dev, "failed to map I/O memory\n");
1740 ret = -EBUSY;
1741 goto failed_free_res;
1742 }
1743
77e19675
EM		 1744 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1745 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
1746 &fbi->dma_buff_phys, GFP_KERNEL);
1747 if (fbi->dma_buff == NULL) {
1748 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
1749 ret = -ENOMEM;
1750 goto failed_free_io;
1751 }
1752
1753 ret = pxafb_init_video_memory(fbi);
1da177e4 1754 if (ret) {
3ae5eaec 1755 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1756 ret = -ENOMEM;
77e19675 1757 goto failed_free_dma;
1da177e4 1758 }
1da177e4 1759
ce4fb7b8 1760 irq = platform_get_irq(dev, 0);
1761 if (irq < 0) {
1762 dev_err(&dev->dev, "no IRQ defined\n");
1763 ret = -ENODEV;
1764 goto failed_free_mem;
1765 }
1766
1767 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1768 if (ret) {
3ae5eaec 1769 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1770 ret = -EBUSY;
ce4fb7b8 1771 goto failed_free_mem;
1da177e4
LT		 1772 }
1773
3c42a449
EM		 1774 ret = pxafb_smart_init(fbi);
1775 if (ret) {
1776 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1777 goto failed_free_irq;
1778 }
07df1c4f 1779
1da177e4
LT		 1780 /*
1781 * This makes sure that our colour bitfield
1782 * descriptors are correctly initialised.
1783 */
ee98476b
JK		 1784 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1785 if (ret) {
1786 dev_err(&dev->dev, "failed to get suitable mode\n");
1787 goto failed_free_irq;
1788 }
1789
1790 ret = pxafb_set_par(&fbi->fb);
1791 if (ret) {
1792 dev_err(&dev->dev, "Failed to set parameters\n");
1793 goto failed_free_irq;
1794 }
1da177e4 1795
3ae5eaec 1796 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1797
1798 ret = register_framebuffer(&fbi->fb);
1799 if (ret < 0) {
b0086efb 1800 dev_err(&dev->dev,
1801 "Failed to register framebuffer device: %d\n", ret);
ee98476b 1802 goto failed_free_cmap;
1da177e4
LT		 1803 }
1804
1da177e4
LT		 1805#ifdef CONFIG_CPU_FREQ
1806 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1807 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1808 cpufreq_register_notifier(&fbi->freq_transition,
1809 CPUFREQ_TRANSITION_NOTIFIER);
1810 cpufreq_register_notifier(&fbi->freq_policy,
1811 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1812#endif
1813
1814 /*
1815 * Ok, now enable the LCD controller
1816 */
1817 set_ctrlr_state(fbi, C_ENABLE);
1818
1819 return 0;
1820
ee98476b
JK		 1821failed_free_cmap:
1822 if (fbi->fb.cmap.len)
1823 fb_dealloc_cmap(&fbi->fb.cmap);
ce4fb7b8 1824failed_free_irq:
1825 free_irq(irq, fbi);
ce4fb7b8 1826failed_free_mem:
77e19675
EM		 1827 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1828failed_free_dma:
1829 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
1830 fbi->dma_buff, fbi->dma_buff_phys);
ee98476b
JK		 1831failed_free_io:
1832 iounmap(fbi->mmio_base);
1833failed_free_res:
1834 release_mem_region(r->start, r->end - r->start + 1);
1835failed_fbi:
1836 clk_put(fbi->clk);
3ae5eaec 1837 platform_set_drvdata(dev, NULL);
1da177e4 1838 kfree(fbi);
ee98476b 1839failed:
1da177e4
LT		 1840 return ret;
1841}
1842
9f17f287
JK		 1843static int __devexit pxafb_remove(struct platform_device *dev)
1844{
1845 struct pxafb_info *fbi = platform_get_drvdata(dev);
1846 struct resource *r;
1847 int irq;
1848 struct fb_info *info;
1849
1850 if (!fbi)
1851 return 0;
1852
1853 info = &fbi->fb;
1854
1855 unregister_framebuffer(info);
1856
1857 pxafb_disable_controller(fbi);
1858
1859 if (fbi->fb.cmap.len)
1860 fb_dealloc_cmap(&fbi->fb.cmap);
1861
1862 irq = platform_get_irq(dev, 0);
1863 free_irq(irq, fbi);
1864
77e19675
EM		 1865 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1866
1867 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
1868 fbi->dma_buff, fbi->dma_buff_phys);
9f17f287
JK		 1869
1870 iounmap(fbi->mmio_base);
1871
1872 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1873 release_mem_region(r->start, r->end - r->start + 1);
1874
1875 clk_put(fbi->clk);
1876 kfree(fbi);
1877
1878 return 0;
1879}
1880
3ae5eaec 1881static struct platform_driver pxafb_driver = {
1da177e4 1882 .probe = pxafb_probe,
9f17f287 1883 .remove = pxafb_remove,
1da177e4
LT		 1884 .suspend = pxafb_suspend,
1885 .resume = pxafb_resume,
3ae5eaec 1886 .driver = {
9f17f287 1887 .owner = THIS_MODULE,
3ae5eaec
RK		 1888 .name = "pxa2xx-fb",
1889 },
1da177e4
LT		 1890};
1891
9e6c2976 1892static int __init pxafb_init(void)
1da177e4 1893{
92ac73c1 1894 if (pxafb_setup_options())
1895 return -EINVAL;
1da177e4 1896
3ae5eaec 1897 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1898}
1899
9f17f287
JK		 1900static void __exit pxafb_exit(void)
1901{
1902 platform_driver_unregister(&pxafb_driver);
1903}
1904
1da177e4 1905module_init(pxafb_init);
9f17f287 1906module_exit(pxafb_exit);
1da177e4
LT		 1907
1908MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1909MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)