Commit | Line | Data |
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1da177e4 LT |
1 | /* drivers/video/pvr2fb.c |
2 | * | |
3 | * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega | |
4 | * Dreamcast. | |
5 | * | |
6 | * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org> | |
7 | * Copyright (c) 2001, 2002, 2003, 2004, 2005 Paul Mundt <lethal@linux-sh.org> | |
8 | * | |
9 | * This file is part of the LinuxDC project (linuxdc.sourceforge.net). | |
10 | * | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This driver is mostly based on the excellent amifb and vfb sources. It uses | |
15 | * an odd scheme for converting hardware values to/from framebuffer values, | |
16 | * here are some hacked-up formulas: | |
17 | * | |
18 | * The Dreamcast has screen offsets from each side of its four borders and | |
19 | * the start offsets of the display window. I used these values to calculate | |
20 | * 'pseudo' values (think of them as placeholders) for the fb video mode, so | |
21 | * that when it came time to convert these values back into their hardware | |
22 | * values, I could just add mode- specific offsets to get the correct mode | |
23 | * settings: | |
24 | * | |
25 | * left_margin = diwstart_h - borderstart_h; | |
26 | * right_margin = borderstop_h - (diwstart_h + xres); | |
27 | * upper_margin = diwstart_v - borderstart_v; | |
28 | * lower_margin = borderstop_v - (diwstart_h + yres); | |
29 | * | |
30 | * hsync_len = borderstart_h + (hsync_total - borderstop_h); | |
31 | * vsync_len = borderstart_v + (vsync_total - borderstop_v); | |
32 | * | |
33 | * Then, when it's time to convert back to hardware settings, the only | |
34 | * constants are the borderstart_* offsets, all other values are derived from | |
35 | * the fb video mode: | |
36 | * | |
37 | * // PAL | |
38 | * borderstart_h = 116; | |
39 | * borderstart_v = 44; | |
40 | * ... | |
41 | * borderstop_h = borderstart_h + hsync_total - hsync_len; | |
42 | * ... | |
43 | * diwstart_v = borderstart_v - upper_margin; | |
44 | * | |
45 | * However, in the current implementation, the borderstart values haven't had | |
46 | * the benefit of being fully researched, so some modes may be broken. | |
47 | */ | |
48 | ||
49 | #undef DEBUG | |
50 | ||
51 | #include <linux/module.h> | |
52 | #include <linux/kernel.h> | |
53 | #include <linux/errno.h> | |
54 | #include <linux/string.h> | |
55 | #include <linux/mm.h> | |
1da177e4 LT |
56 | #include <linux/slab.h> |
57 | #include <linux/delay.h> | |
1da177e4 LT |
58 | #include <linux/interrupt.h> |
59 | #include <linux/fb.h> | |
60 | #include <linux/init.h> | |
61 | #include <linux/pci.h> | |
62 | ||
63 | #ifdef CONFIG_SH_DREAMCAST | |
64 | #include <asm/machvec.h> | |
65 | #include <asm/mach/sysasic.h> | |
66 | #endif | |
67 | ||
68 | #ifdef CONFIG_SH_DMA | |
69 | #include <linux/pagemap.h> | |
70 | #include <asm/mach/dma.h> | |
71 | #include <asm/dma.h> | |
72 | #endif | |
73 | ||
74 | #ifdef CONFIG_SH_STORE_QUEUES | |
75 | #include <asm/uaccess.h> | |
76 | #include <asm/cpu/sq.h> | |
77 | #endif | |
78 | ||
79 | #ifndef PCI_DEVICE_ID_NEC_NEON250 | |
80 | # define PCI_DEVICE_ID_NEC_NEON250 0x0067 | |
81 | #endif | |
82 | ||
83 | /* 2D video registers */ | |
84 | #define DISP_BASE par->mmio_base | |
85 | #define DISP_BRDRCOLR (DISP_BASE + 0x40) | |
86 | #define DISP_DIWMODE (DISP_BASE + 0x44) | |
87 | #define DISP_DIWADDRL (DISP_BASE + 0x50) | |
88 | #define DISP_DIWADDRS (DISP_BASE + 0x54) | |
89 | #define DISP_DIWSIZE (DISP_BASE + 0x5c) | |
90 | #define DISP_SYNCCONF (DISP_BASE + 0xd0) | |
91 | #define DISP_BRDRHORZ (DISP_BASE + 0xd4) | |
92 | #define DISP_SYNCSIZE (DISP_BASE + 0xd8) | |
93 | #define DISP_BRDRVERT (DISP_BASE + 0xdc) | |
94 | #define DISP_DIWCONF (DISP_BASE + 0xe8) | |
95 | #define DISP_DIWHSTRT (DISP_BASE + 0xec) | |
96 | #define DISP_DIWVSTRT (DISP_BASE + 0xf0) | |
306c869c | 97 | #define DISP_PIXDEPTH (DISP_BASE + 0x108) |
1da177e4 LT |
98 | |
99 | /* Pixel clocks, one for TV output, doubled for VGA output */ | |
100 | #define TV_CLK 74239 | |
101 | #define VGA_CLK 37119 | |
102 | ||
103 | /* This is for 60Hz - the VTOTAL is doubled for interlaced modes */ | |
104 | #define PAL_HTOTAL 863 | |
105 | #define PAL_VTOTAL 312 | |
106 | #define NTSC_HTOTAL 857 | |
107 | #define NTSC_VTOTAL 262 | |
108 | ||
109 | /* Supported cable types */ | |
110 | enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE }; | |
111 | ||
112 | /* Supported video output types */ | |
113 | enum { VO_PAL, VO_NTSC, VO_VGA }; | |
114 | ||
115 | /* Supported palette types */ | |
116 | enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 }; | |
117 | ||
118 | struct pvr2_params { unsigned int val; char *name; }; | |
7e7ec0d4 | 119 | static struct pvr2_params cables[] __devinitdata = { |
1da177e4 LT |
120 | { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" }, |
121 | }; | |
122 | ||
7e7ec0d4 | 123 | static struct pvr2_params outputs[] __devinitdata = { |
1da177e4 LT |
124 | { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" }, |
125 | }; | |
126 | ||
127 | /* | |
128 | * This describes the current video mode | |
129 | */ | |
130 | ||
131 | static struct pvr2fb_par { | |
132 | unsigned int hsync_total; /* Clocks/line */ | |
133 | unsigned int vsync_total; /* Lines/field */ | |
134 | unsigned int borderstart_h; | |
135 | unsigned int borderstop_h; | |
136 | unsigned int borderstart_v; | |
137 | unsigned int borderstop_v; | |
138 | unsigned int diwstart_h; /* Horizontal offset of the display field */ | |
139 | unsigned int diwstart_v; /* Vertical offset of the display field, for | |
140 | interlaced modes, this is the long field */ | |
141 | unsigned long disp_start; /* Address of image within VRAM */ | |
142 | unsigned char is_interlaced; /* Is the display interlaced? */ | |
143 | unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */ | |
144 | unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */ | |
145 | ||
146 | unsigned long mmio_base; /* MMIO base */ | |
9cd1c674 | 147 | u32 palette[16]; |
1da177e4 LT |
148 | } *currentpar; |
149 | ||
150 | static struct fb_info *fb_info; | |
151 | ||
e9705a77 | 152 | static struct fb_fix_screeninfo pvr2_fix __devinitdata = { |
1da177e4 | 153 | .id = "NEC PowerVR2", |
e9705a77 PM |
154 | .type = FB_TYPE_PACKED_PIXELS, |
155 | .visual = FB_VISUAL_TRUECOLOR, | |
1da177e4 LT |
156 | .ypanstep = 1, |
157 | .ywrapstep = 1, | |
e9705a77 | 158 | .accel = FB_ACCEL_NONE, |
1da177e4 LT |
159 | }; |
160 | ||
e9705a77 | 161 | static struct fb_var_screeninfo pvr2_var __devinitdata = { |
1da177e4 LT |
162 | .xres = 640, |
163 | .yres = 480, | |
164 | .xres_virtual = 640, | |
165 | .yres_virtual = 480, | |
166 | .bits_per_pixel =16, | |
167 | .red = { 11, 5, 0 }, | |
168 | .green = { 5, 6, 0 }, | |
169 | .blue = { 0, 5, 0 }, | |
170 | .activate = FB_ACTIVATE_NOW, | |
171 | .height = -1, | |
172 | .width = -1, | |
173 | .vmode = FB_VMODE_NONINTERLACED, | |
174 | }; | |
175 | ||
176 | static int cable_type = CT_VGA; | |
177 | static int video_output = VO_VGA; | |
178 | ||
179 | static int nopan = 0; | |
180 | static int nowrap = 1; | |
181 | ||
182 | /* | |
183 | * We do all updating, blanking, etc. during the vertical retrace period | |
184 | */ | |
185 | static unsigned int do_vmode_full = 0; /* Change the video mode */ | |
186 | static unsigned int do_vmode_pan = 0; /* Update the video mode */ | |
187 | static short do_blank = 0; /* (Un)Blank the screen */ | |
188 | ||
189 | static unsigned int is_blanked = 0; /* Is the screen blanked? */ | |
190 | ||
191 | #ifdef CONFIG_SH_STORE_QUEUES | |
d2b06a8b | 192 | static unsigned long pvr2fb_map; |
1da177e4 LT |
193 | #endif |
194 | ||
195 | #ifdef CONFIG_SH_DMA | |
196 | static unsigned int shdma = PVR2_CASCADE_CHAN; | |
197 | static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS; | |
198 | #endif | |
199 | ||
1da177e4 LT |
200 | static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue, |
201 | unsigned int transp, struct fb_info *info); | |
202 | static int pvr2fb_blank(int blank, struct fb_info *info); | |
203 | static unsigned long get_line_length(int xres_virtual, int bpp); | |
204 | static void set_color_bitfields(struct fb_var_screeninfo *var); | |
205 | static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info); | |
206 | static int pvr2fb_set_par(struct fb_info *info); | |
207 | static void pvr2_update_display(struct fb_info *info); | |
208 | static void pvr2_init_display(struct fb_info *info); | |
209 | static void pvr2_do_blank(void); | |
7d12e780 | 210 | static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id); |
1da177e4 LT |
211 | static int pvr2_init_cable(void); |
212 | static int pvr2_get_param(const struct pvr2_params *p, const char *s, | |
213 | int val, int size); | |
d2b06a8b | 214 | #ifdef CONFIG_SH_DMA |
3f9b0880 | 215 | static ssize_t pvr2fb_write(struct fb_info *info, const char *buf, |
1da177e4 | 216 | size_t count, loff_t *ppos); |
d2b06a8b | 217 | #endif |
1da177e4 LT |
218 | |
219 | static struct fb_ops pvr2fb_ops = { | |
d2b06a8b PM |
220 | .owner = THIS_MODULE, |
221 | .fb_setcolreg = pvr2fb_setcolreg, | |
222 | .fb_blank = pvr2fb_blank, | |
223 | .fb_check_var = pvr2fb_check_var, | |
224 | .fb_set_par = pvr2fb_set_par, | |
1da177e4 LT |
225 | #ifdef CONFIG_SH_DMA |
226 | .fb_write = pvr2fb_write, | |
227 | #endif | |
e9705a77 | 228 | .fb_fillrect = cfb_fillrect, |
1da177e4 LT |
229 | .fb_copyarea = cfb_copyarea, |
230 | .fb_imageblit = cfb_imageblit, | |
1da177e4 LT |
231 | }; |
232 | ||
7e7ec0d4 | 233 | static struct fb_videomode pvr2_modedb[] __devinitdata = { |
1da177e4 LT |
234 | /* |
235 | * Broadcast video modes (PAL and NTSC). I'm unfamiliar with | |
236 | * PAL-M and PAL-N, but from what I've read both modes parallel PAL and | |
237 | * NTSC, so it shouldn't be a problem (I hope). | |
238 | */ | |
239 | ||
240 | { | |
241 | /* 640x480 @ 60Hz interlaced (NTSC) */ | |
242 | "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26, | |
243 | FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP | |
244 | }, { | |
245 | /* 640x240 @ 60Hz (NTSC) */ | |
246 | /* XXX: Broken! Don't use... */ | |
247 | "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22, | |
248 | FB_SYNC_BROADCAST, FB_VMODE_YWRAP | |
249 | }, { | |
250 | /* 640x480 @ 60hz (VGA) */ | |
251 | "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26, | |
252 | 0, FB_VMODE_YWRAP | |
e9705a77 | 253 | }, |
1da177e4 LT |
254 | }; |
255 | ||
256 | #define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb) | |
257 | ||
258 | #define DEFMODE_NTSC 0 | |
259 | #define DEFMODE_PAL 0 | |
260 | #define DEFMODE_VGA 2 | |
261 | ||
262 | static int defmode = DEFMODE_NTSC; | |
7e7ec0d4 | 263 | static char *mode_option __devinitdata = NULL; |
1da177e4 LT |
264 | |
265 | static inline void pvr2fb_set_pal_type(unsigned int type) | |
266 | { | |
267 | struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par; | |
268 | ||
269 | fb_writel(type, par->mmio_base + 0x108); | |
270 | } | |
271 | ||
272 | static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par, | |
273 | unsigned int regno, | |
274 | unsigned int val) | |
275 | { | |
276 | fb_writel(val, par->mmio_base + 0x1000 + (4 * regno)); | |
277 | } | |
278 | ||
279 | static int pvr2fb_blank(int blank, struct fb_info *info) | |
280 | { | |
281 | do_blank = blank ? blank : -1; | |
282 | return 0; | |
283 | } | |
284 | ||
285 | static inline unsigned long get_line_length(int xres_virtual, int bpp) | |
286 | { | |
287 | return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3); | |
288 | } | |
289 | ||
290 | static void set_color_bitfields(struct fb_var_screeninfo *var) | |
291 | { | |
292 | switch (var->bits_per_pixel) { | |
293 | case 16: /* RGB 565 */ | |
e9705a77 | 294 | pvr2fb_set_pal_type(PAL_RGB565); |
1da177e4 LT |
295 | var->red.offset = 11; var->red.length = 5; |
296 | var->green.offset = 5; var->green.length = 6; | |
297 | var->blue.offset = 0; var->blue.length = 5; | |
298 | var->transp.offset = 0; var->transp.length = 0; | |
299 | break; | |
300 | case 24: /* RGB 888 */ | |
301 | var->red.offset = 16; var->red.length = 8; | |
302 | var->green.offset = 8; var->green.length = 8; | |
303 | var->blue.offset = 0; var->blue.length = 8; | |
304 | var->transp.offset = 0; var->transp.length = 0; | |
305 | break; | |
306 | case 32: /* ARGB 8888 */ | |
e9705a77 | 307 | pvr2fb_set_pal_type(PAL_ARGB8888); |
1da177e4 LT |
308 | var->red.offset = 16; var->red.length = 8; |
309 | var->green.offset = 8; var->green.length = 8; | |
310 | var->blue.offset = 0; var->blue.length = 8; | |
311 | var->transp.offset = 24; var->transp.length = 8; | |
312 | break; | |
313 | } | |
314 | } | |
315 | ||
316 | static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, | |
317 | unsigned int green, unsigned int blue, | |
318 | unsigned int transp, struct fb_info *info) | |
319 | { | |
320 | struct pvr2fb_par *par = (struct pvr2fb_par *)info->par; | |
321 | unsigned int tmp; | |
322 | ||
323 | if (regno > info->cmap.len) | |
324 | return 1; | |
325 | ||
326 | /* | |
327 | * We only support the hardware palette for 16 and 32bpp. It's also | |
328 | * expected that the palette format has been set by the time we get | |
329 | * here, so we don't waste time setting it again. | |
330 | */ | |
331 | switch (info->var.bits_per_pixel) { | |
332 | case 16: /* RGB 565 */ | |
333 | tmp = (red & 0xf800) | | |
334 | ((green & 0xfc00) >> 5) | | |
335 | ((blue & 0xf800) >> 11); | |
336 | ||
337 | pvr2fb_set_pal_entry(par, regno, tmp); | |
1da177e4 LT |
338 | break; |
339 | case 24: /* RGB 888 */ | |
340 | red >>= 8; green >>= 8; blue >>= 8; | |
a66ad56e | 341 | tmp = (red << 16) | (green << 8) | blue; |
1da177e4 LT |
342 | break; |
343 | case 32: /* ARGB 8888 */ | |
344 | red >>= 8; green >>= 8; blue >>= 8; | |
345 | tmp = (transp << 24) | (red << 16) | (green << 8) | blue; | |
346 | ||
347 | pvr2fb_set_pal_entry(par, regno, tmp); | |
1da177e4 LT |
348 | break; |
349 | default: | |
350 | pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel); | |
351 | return 1; | |
352 | } | |
353 | ||
a66ad56e AD |
354 | if (regno < 16) |
355 | ((u32*)(info->pseudo_palette))[regno] = tmp; | |
356 | ||
1da177e4 LT |
357 | return 0; |
358 | } | |
359 | ||
360 | static int pvr2fb_set_par(struct fb_info *info) | |
361 | { | |
362 | struct pvr2fb_par *par = (struct pvr2fb_par *)info->par; | |
363 | struct fb_var_screeninfo *var = &info->var; | |
364 | unsigned long line_length; | |
365 | unsigned int vtotal; | |
366 | ||
367 | /* | |
368 | * XXX: It's possible that a user could use a VGA box, change the cable | |
369 | * type in hardware (i.e. switch from VGA<->composite), then change | |
370 | * modes (i.e. switching to another VT). If that happens we should | |
371 | * automagically change the output format to cope, but currently I | |
372 | * don't have a VGA box to make sure this works properly. | |
373 | */ | |
374 | cable_type = pvr2_init_cable(); | |
375 | if (cable_type == CT_VGA && video_output != VO_VGA) | |
376 | video_output = VO_VGA; | |
377 | ||
378 | var->vmode &= FB_VMODE_MASK; | |
379 | if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA) | |
380 | par->is_interlaced = 1; | |
e9705a77 | 381 | /* |
1da177e4 LT |
382 | * XXX: Need to be more creative with this (i.e. allow doublecan for |
383 | * PAL/NTSC output). | |
384 | */ | |
385 | if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA) | |
386 | par->is_doublescan = 1; | |
e9705a77 | 387 | |
1da177e4 LT |
388 | par->hsync_total = var->left_margin + var->xres + var->right_margin + |
389 | var->hsync_len; | |
390 | par->vsync_total = var->upper_margin + var->yres + var->lower_margin + | |
391 | var->vsync_len; | |
392 | ||
393 | if (var->sync & FB_SYNC_BROADCAST) { | |
394 | vtotal = par->vsync_total; | |
395 | if (par->is_interlaced) | |
396 | vtotal /= 2; | |
397 | if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) { | |
398 | /* XXX: Check for start values here... */ | |
399 | /* XXX: Check hardware for PAL-compatibility */ | |
400 | par->borderstart_h = 116; | |
401 | par->borderstart_v = 44; | |
402 | } else { | |
403 | /* NTSC video output */ | |
404 | par->borderstart_h = 126; | |
405 | par->borderstart_v = 18; | |
406 | } | |
407 | } else { | |
408 | /* VGA mode */ | |
409 | /* XXX: What else needs to be checked? */ | |
e9705a77 | 410 | /* |
1da177e4 LT |
411 | * XXX: We have a little freedom in VGA modes, what ranges |
412 | * should be here (i.e. hsync/vsync totals, etc.)? | |
413 | */ | |
414 | par->borderstart_h = 126; | |
415 | par->borderstart_v = 40; | |
416 | } | |
417 | ||
418 | /* Calculate the remainding offsets */ | |
419 | par->diwstart_h = par->borderstart_h + var->left_margin; | |
420 | par->diwstart_v = par->borderstart_v + var->upper_margin; | |
e9705a77 PM |
421 | par->borderstop_h = par->diwstart_h + var->xres + |
422 | var->right_margin; | |
1da177e4 LT |
423 | par->borderstop_v = par->diwstart_v + var->yres + |
424 | var->lower_margin; | |
425 | ||
426 | if (!par->is_interlaced) | |
427 | par->borderstop_v /= 2; | |
428 | if (info->var.xres < 640) | |
429 | par->is_lowres = 1; | |
430 | ||
431 | line_length = get_line_length(var->xres_virtual, var->bits_per_pixel); | |
432 | par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length; | |
433 | info->fix.line_length = line_length; | |
434 | return 0; | |
435 | } | |
436 | ||
437 | static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
438 | { | |
439 | struct pvr2fb_par *par = (struct pvr2fb_par *)info->par; | |
440 | unsigned int vtotal, hsync_total; | |
441 | unsigned long line_length; | |
442 | ||
443 | if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) { | |
444 | pr_debug("Invalid pixclock value %d\n", var->pixclock); | |
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | if (var->xres < 320) | |
449 | var->xres = 320; | |
450 | if (var->yres < 240) | |
451 | var->yres = 240; | |
452 | if (var->xres_virtual < var->xres) | |
453 | var->xres_virtual = var->xres; | |
454 | if (var->yres_virtual < var->yres) | |
455 | var->yres_virtual = var->yres; | |
456 | ||
457 | if (var->bits_per_pixel <= 16) | |
458 | var->bits_per_pixel = 16; | |
459 | else if (var->bits_per_pixel <= 24) | |
460 | var->bits_per_pixel = 24; | |
461 | else if (var->bits_per_pixel <= 32) | |
462 | var->bits_per_pixel = 32; | |
463 | ||
464 | set_color_bitfields(var); | |
465 | ||
466 | if (var->vmode & FB_VMODE_YWRAP) { | |
e9705a77 | 467 | if (var->xoffset || var->yoffset < 0 || |
1da177e4 LT |
468 | var->yoffset >= var->yres_virtual) { |
469 | var->xoffset = var->yoffset = 0; | |
470 | } else { | |
471 | if (var->xoffset > var->xres_virtual - var->xres || | |
e9705a77 | 472 | var->yoffset > var->yres_virtual - var->yres || |
1da177e4 LT |
473 | var->xoffset < 0 || var->yoffset < 0) |
474 | var->xoffset = var->yoffset = 0; | |
475 | } | |
476 | } else { | |
477 | var->xoffset = var->yoffset = 0; | |
478 | } | |
479 | ||
e9705a77 | 480 | /* |
1da177e4 LT |
481 | * XXX: Need to be more creative with this (i.e. allow doublecan for |
482 | * PAL/NTSC output). | |
483 | */ | |
484 | if (var->yres < 480 && video_output == VO_VGA) | |
485 | var->vmode |= FB_VMODE_DOUBLE; | |
486 | ||
487 | if (video_output != VO_VGA) { | |
488 | var->sync |= FB_SYNC_BROADCAST; | |
489 | var->vmode |= FB_VMODE_INTERLACED; | |
490 | } else { | |
491 | var->sync &= ~FB_SYNC_BROADCAST; | |
492 | var->vmode &= ~FB_VMODE_INTERLACED; | |
493 | var->vmode |= pvr2_var.vmode; | |
494 | } | |
495 | ||
496 | if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) { | |
497 | var->right_margin = par->borderstop_h - | |
498 | (par->diwstart_h + var->xres); | |
499 | var->left_margin = par->diwstart_h - par->borderstart_h; | |
500 | var->hsync_len = par->borderstart_h + | |
501 | (par->hsync_total - par->borderstop_h); | |
502 | ||
503 | var->upper_margin = par->diwstart_v - par->borderstart_v; | |
504 | var->lower_margin = par->borderstop_v - | |
505 | (par->diwstart_v + var->yres); | |
506 | var->vsync_len = par->borderstop_v + | |
507 | (par->vsync_total - par->borderstop_v); | |
508 | } | |
e9705a77 | 509 | |
1da177e4 LT |
510 | hsync_total = var->left_margin + var->xres + var->right_margin + |
511 | var->hsync_len; | |
512 | vtotal = var->upper_margin + var->yres + var->lower_margin + | |
513 | var->vsync_len; | |
514 | ||
515 | if (var->sync & FB_SYNC_BROADCAST) { | |
516 | if (var->vmode & FB_VMODE_INTERLACED) | |
517 | vtotal /= 2; | |
518 | if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) { | |
519 | /* PAL video output */ | |
520 | /* XXX: Should be using a range here ... ? */ | |
521 | if (hsync_total != PAL_HTOTAL) { | |
522 | pr_debug("invalid hsync total for PAL\n"); | |
523 | return -EINVAL; | |
524 | } | |
525 | } else { | |
526 | /* NTSC video output */ | |
527 | if (hsync_total != NTSC_HTOTAL) { | |
528 | pr_debug("invalid hsync total for NTSC\n"); | |
529 | return -EINVAL; | |
530 | } | |
531 | } | |
532 | } | |
e9705a77 | 533 | |
1da177e4 LT |
534 | /* Check memory sizes */ |
535 | line_length = get_line_length(var->xres_virtual, var->bits_per_pixel); | |
536 | if (line_length * var->yres_virtual > info->fix.smem_len) | |
537 | return -ENOMEM; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static void pvr2_update_display(struct fb_info *info) | |
543 | { | |
544 | struct pvr2fb_par *par = (struct pvr2fb_par *) info->par; | |
545 | struct fb_var_screeninfo *var = &info->var; | |
546 | ||
547 | /* Update the start address of the display image */ | |
548 | fb_writel(par->disp_start, DISP_DIWADDRL); | |
549 | fb_writel(par->disp_start + | |
550 | get_line_length(var->xoffset+var->xres, var->bits_per_pixel), | |
551 | DISP_DIWADDRS); | |
552 | } | |
553 | ||
e9705a77 | 554 | /* |
1da177e4 LT |
555 | * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't |
556 | * very stable. It's probably due to the fact that a lot of the 2D video | |
557 | * registers are still undocumented. | |
558 | */ | |
559 | ||
560 | static void pvr2_init_display(struct fb_info *info) | |
561 | { | |
562 | struct pvr2fb_par *par = (struct pvr2fb_par *) info->par; | |
563 | struct fb_var_screeninfo *var = &info->var; | |
564 | unsigned int diw_height, diw_width, diw_modulo = 1; | |
565 | unsigned int bytesperpixel = var->bits_per_pixel >> 3; | |
566 | ||
567 | /* hsync and vsync totals */ | |
568 | fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE); | |
569 | ||
570 | /* column height, modulo, row width */ | |
571 | /* since we're "panning" within vram, we need to offset things based | |
572 | * on the offset from the virtual x start to our real gfx. */ | |
573 | if (video_output != VO_VGA && par->is_interlaced) | |
574 | diw_modulo += info->fix.line_length / 4; | |
575 | diw_height = (par->is_interlaced ? var->yres / 2 : var->yres); | |
576 | diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4; | |
577 | fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width, | |
578 | DISP_DIWSIZE); | |
579 | ||
580 | /* display address, long and short fields */ | |
581 | fb_writel(par->disp_start, DISP_DIWADDRL); | |
582 | fb_writel(par->disp_start + | |
583 | get_line_length(var->xoffset+var->xres, var->bits_per_pixel), | |
584 | DISP_DIWADDRS); | |
585 | ||
586 | /* border horizontal, border vertical, border color */ | |
587 | fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ); | |
588 | fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT); | |
589 | fb_writel(0, DISP_BRDRCOLR); | |
590 | ||
591 | /* display window start position */ | |
592 | fb_writel(par->diwstart_h, DISP_DIWHSTRT); | |
593 | fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT); | |
e9705a77 | 594 | |
1da177e4 LT |
595 | /* misc. settings */ |
596 | fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF); | |
597 | ||
598 | /* clock doubler (for VGA), scan doubler, display enable */ | |
e9705a77 | 599 | fb_writel(((video_output == VO_VGA) << 23) | |
1da177e4 LT |
600 | (par->is_doublescan << 1) | 1, DISP_DIWMODE); |
601 | ||
602 | /* bits per pixel */ | |
603 | fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE); | |
306c869c | 604 | fb_writel(bytesperpixel << 2, DISP_PIXDEPTH); |
1da177e4 | 605 | |
e9705a77 | 606 | /* video enable, color sync, interlace, |
1da177e4 LT |
607 | * hsync and vsync polarity (currently unused) */ |
608 | fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF); | |
609 | } | |
610 | ||
611 | /* Simulate blanking by making the border cover the entire screen */ | |
612 | ||
613 | #define BLANK_BIT (1<<3) | |
614 | ||
615 | static void pvr2_do_blank(void) | |
616 | { | |
617 | struct pvr2fb_par *par = currentpar; | |
618 | unsigned long diwconf; | |
619 | ||
620 | diwconf = fb_readl(DISP_DIWCONF); | |
621 | if (do_blank > 0) | |
622 | fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF); | |
623 | else | |
624 | fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF); | |
625 | ||
626 | is_blanked = do_blank > 0 ? do_blank : 0; | |
627 | } | |
628 | ||
7d12e780 | 629 | static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id) |
1da177e4 LT |
630 | { |
631 | struct fb_info *info = dev_id; | |
632 | ||
633 | if (do_vmode_pan || do_vmode_full) | |
634 | pvr2_update_display(info); | |
635 | if (do_vmode_full) | |
636 | pvr2_init_display(info); | |
637 | if (do_vmode_pan) | |
638 | do_vmode_pan = 0; | |
639 | if (do_vmode_full) | |
640 | do_vmode_full = 0; | |
641 | if (do_blank) { | |
642 | pvr2_do_blank(); | |
643 | do_blank = 0; | |
644 | } | |
645 | return IRQ_HANDLED; | |
646 | } | |
647 | ||
648 | /* | |
649 | * Determine the cable type and initialize the cable output format. Don't do | |
650 | * anything if the cable type has been overidden (via "cable:XX"). | |
651 | */ | |
652 | ||
653 | #define PCTRA 0xff80002c | |
654 | #define PDTRA 0xff800030 | |
655 | #define VOUTC 0xa0702c00 | |
656 | ||
657 | static int pvr2_init_cable(void) | |
658 | { | |
659 | if (cable_type < 0) { | |
e9705a77 | 660 | fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000, |
1da177e4 LT |
661 | PCTRA); |
662 | cable_type = (fb_readw(PDTRA) >> 8) & 3; | |
663 | } | |
664 | ||
665 | /* Now select the output format (either composite or other) */ | |
666 | /* XXX: Save the previous val first, as this reg is also AICA | |
667 | related */ | |
668 | if (cable_type == CT_COMPOSITE) | |
669 | fb_writel(3 << 8, VOUTC); | |
670 | else | |
671 | fb_writel(0, VOUTC); | |
672 | ||
673 | return cable_type; | |
674 | } | |
675 | ||
676 | #ifdef CONFIG_SH_DMA | |
3f9b0880 | 677 | static ssize_t pvr2fb_write(struct fb_info *info, const char *buf, |
1da177e4 LT |
678 | size_t count, loff_t *ppos) |
679 | { | |
680 | unsigned long dst, start, end, len; | |
681 | unsigned int nr_pages; | |
682 | struct page **pages; | |
683 | int ret, i; | |
684 | ||
685 | nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT; | |
686 | ||
687 | pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); | |
688 | if (!pages) | |
689 | return -ENOMEM; | |
e9705a77 | 690 | |
1da177e4 LT |
691 | down_read(¤t->mm->mmap_sem); |
692 | ret = get_user_pages(current, current->mm, (unsigned long)buf, | |
693 | nr_pages, WRITE, 0, pages, NULL); | |
694 | up_read(¤t->mm->mmap_sem); | |
695 | ||
696 | if (ret < nr_pages) { | |
697 | nr_pages = ret; | |
698 | ret = -EINVAL; | |
699 | goto out_unmap; | |
700 | } | |
701 | ||
702 | dma_configure_channel(shdma, 0x12c1); | |
e9705a77 | 703 | |
1da177e4 LT |
704 | dst = (unsigned long)fb_info->screen_base + *ppos; |
705 | start = (unsigned long)page_address(pages[0]); | |
706 | end = (unsigned long)page_address(pages[nr_pages]); | |
707 | len = nr_pages << PAGE_SHIFT; | |
708 | ||
709 | /* Half-assed contig check */ | |
710 | if (start + len == end) { | |
711 | /* As we do this in one shot, it's either all or nothing.. */ | |
712 | if ((*ppos + len) > fb_info->fix.smem_len) { | |
713 | ret = -ENOSPC; | |
714 | goto out_unmap; | |
715 | } | |
716 | ||
717 | dma_write(shdma, start, 0, len); | |
718 | dma_write(pvr2dma, 0, dst, len); | |
719 | dma_wait_for_completion(pvr2dma); | |
720 | ||
721 | goto out; | |
722 | } | |
723 | ||
724 | /* Not contiguous, writeout per-page instead.. */ | |
725 | for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) { | |
726 | if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) { | |
727 | ret = -ENOSPC; | |
728 | goto out_unmap; | |
729 | } | |
730 | ||
731 | dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0); | |
732 | dma_write_page(pvr2dma, 0, dst); | |
733 | dma_wait_for_completion(pvr2dma); | |
734 | } | |
735 | ||
736 | out: | |
737 | *ppos += count; | |
738 | ret = count; | |
739 | ||
740 | out_unmap: | |
741 | for (i = 0; i < nr_pages; i++) | |
742 | page_cache_release(pages[i]); | |
743 | ||
744 | kfree(pages); | |
745 | ||
746 | return ret; | |
e9705a77 | 747 | } |
1da177e4 LT |
748 | #endif /* CONFIG_SH_DMA */ |
749 | ||
750 | /** | |
751 | * pvr2fb_common_init | |
752 | * | |
753 | * Common init code for the PVR2 chips. | |
754 | * | |
755 | * This mostly takes care of the common aspects of the fb setup and | |
756 | * registration. It's expected that the board-specific init code has | |
757 | * already setup pvr2_fix with something meaningful at this point. | |
758 | * | |
759 | * Device info reporting is also done here, as well as picking a sane | |
760 | * default from the modedb. For board-specific modelines, simply define | |
761 | * a per-board modedb. | |
762 | * | |
763 | * Also worth noting is that the cable and video output types are likely | |
764 | * always going to be VGA for the PCI-based PVR2 boards, but we leave this | |
765 | * in for flexibility anyways. Who knows, maybe someone has tv-out on a | |
766 | * PCI-based version of these things ;-) | |
767 | */ | |
7e7ec0d4 | 768 | static int __devinit pvr2fb_common_init(void) |
1da177e4 LT |
769 | { |
770 | struct pvr2fb_par *par = currentpar; | |
771 | unsigned long modememused, rev; | |
772 | ||
773 | fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start, | |
774 | pvr2_fix.smem_len); | |
e9705a77 | 775 | |
1da177e4 LT |
776 | if (!fb_info->screen_base) { |
777 | printk(KERN_ERR "pvr2fb: Failed to remap smem space\n"); | |
778 | goto out_err; | |
779 | } | |
780 | ||
781 | par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start, | |
e9705a77 | 782 | pvr2_fix.mmio_len); |
1da177e4 LT |
783 | if (!par->mmio_base) { |
784 | printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n"); | |
785 | goto out_err; | |
786 | } | |
787 | ||
d2b06a8b | 788 | fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len); |
1da177e4 LT |
789 | |
790 | pvr2_fix.ypanstep = nopan ? 0 : 1; | |
791 | pvr2_fix.ywrapstep = nowrap ? 0 : 1; | |
792 | ||
793 | fb_info->fbops = &pvr2fb_ops; | |
794 | fb_info->fix = pvr2_fix; | |
795 | fb_info->par = currentpar; | |
9cd1c674 | 796 | fb_info->pseudo_palette = currentpar->palette; |
1da177e4 LT |
797 | fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
798 | ||
799 | if (video_output == VO_VGA) | |
800 | defmode = DEFMODE_VGA; | |
801 | ||
802 | if (!mode_option) | |
803 | mode_option = "640x480@60"; | |
804 | ||
805 | if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb, | |
806 | NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16)) | |
807 | fb_info->var = pvr2_var; | |
808 | ||
809 | fb_alloc_cmap(&fb_info->cmap, 256, 0); | |
810 | ||
811 | if (register_framebuffer(fb_info) < 0) | |
812 | goto out_err; | |
306c869c AM |
813 | /*Must write PIXDEPTH to register before anything is displayed - so force init */ |
814 | pvr2_init_display(fb_info); | |
1da177e4 LT |
815 | |
816 | modememused = get_line_length(fb_info->var.xres_virtual, | |
817 | fb_info->var.bits_per_pixel); | |
818 | modememused *= fb_info->var.yres_virtual; | |
819 | ||
820 | rev = fb_readl(par->mmio_base + 0x04); | |
821 | ||
822 | printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n", | |
823 | fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f, | |
824 | modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10)); | |
e9705a77 | 825 | printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n", |
1da177e4 | 826 | fb_info->node, fb_info->var.xres, fb_info->var.yres, |
d2b06a8b | 827 | fb_info->var.bits_per_pixel, |
1da177e4 LT |
828 | get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel), |
829 | (char *)pvr2_get_param(cables, NULL, cable_type, 3), | |
830 | (char *)pvr2_get_param(outputs, NULL, video_output, 3)); | |
831 | ||
832 | #ifdef CONFIG_SH_STORE_QUEUES | |
833 | printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node); | |
834 | ||
835 | pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len, | |
d2b06a8b | 836 | fb_info->fix.id, pgprot_val(PAGE_SHARED)); |
1da177e4 LT |
837 | |
838 | printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n", | |
d2b06a8b | 839 | fb_info->node, pvr2fb_map); |
1da177e4 LT |
840 | #endif |
841 | ||
842 | return 0; | |
843 | ||
844 | out_err: | |
845 | if (fb_info->screen_base) | |
846 | iounmap(fb_info->screen_base); | |
847 | if (par->mmio_base) | |
848 | iounmap((void *)par->mmio_base); | |
849 | ||
850 | return -ENXIO; | |
851 | } | |
852 | ||
853 | #ifdef CONFIG_SH_DREAMCAST | |
854 | static int __init pvr2fb_dc_init(void) | |
855 | { | |
856 | if (!mach_is_dreamcast()) | |
857 | return -ENXIO; | |
858 | ||
859 | /* Make a guess at the monitor based on the attached cable */ | |
860 | if (pvr2_init_cable() == CT_VGA) { | |
861 | fb_info->monspecs.hfmin = 30000; | |
862 | fb_info->monspecs.hfmax = 70000; | |
863 | fb_info->monspecs.vfmin = 60; | |
864 | fb_info->monspecs.vfmax = 60; | |
865 | } else { | |
866 | /* Not VGA, using a TV (taken from acornfb) */ | |
867 | fb_info->monspecs.hfmin = 15469; | |
868 | fb_info->monspecs.hfmax = 15781; | |
869 | fb_info->monspecs.vfmin = 49; | |
870 | fb_info->monspecs.vfmax = 51; | |
871 | } | |
872 | ||
873 | /* | |
874 | * XXX: This needs to pull default video output via BIOS or other means | |
875 | */ | |
876 | if (video_output < 0) { | |
877 | if (cable_type == CT_VGA) { | |
878 | video_output = VO_VGA; | |
879 | } else { | |
880 | video_output = VO_NTSC; | |
881 | } | |
882 | } | |
e9705a77 PM |
883 | |
884 | /* | |
1da177e4 LT |
885 | * Nothing exciting about the DC PVR2 .. only a measly 8MiB. |
886 | */ | |
887 | pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */ | |
888 | pvr2_fix.smem_len = 8 << 20; | |
889 | ||
890 | pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */ | |
891 | pvr2_fix.mmio_len = 0x2000; | |
892 | ||
893 | if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, 0, | |
894 | "pvr2 VBL handler", fb_info)) { | |
895 | return -EBUSY; | |
896 | } | |
897 | ||
898 | #ifdef CONFIG_SH_DMA | |
899 | if (request_dma(pvr2dma, "pvr2") != 0) { | |
900 | free_irq(HW_EVENT_VSYNC, 0); | |
901 | return -EBUSY; | |
902 | } | |
903 | #endif | |
904 | ||
905 | return pvr2fb_common_init(); | |
906 | } | |
907 | ||
e9705a77 | 908 | static void __exit pvr2fb_dc_exit(void) |
1da177e4 | 909 | { |
295a1b47 AL |
910 | if (fb_info->screen_base) { |
911 | iounmap(fb_info->screen_base); | |
912 | fb_info->screen_base = NULL; | |
913 | } | |
914 | if (currentpar->mmio_base) { | |
915 | iounmap((void *)currentpar->mmio_base); | |
916 | currentpar->mmio_base = 0; | |
917 | } | |
918 | ||
1da177e4 LT |
919 | free_irq(HW_EVENT_VSYNC, 0); |
920 | #ifdef CONFIG_SH_DMA | |
921 | free_dma(pvr2dma); | |
922 | #endif | |
923 | } | |
924 | #endif /* CONFIG_SH_DREAMCAST */ | |
925 | ||
926 | #ifdef CONFIG_PCI | |
927 | static int __devinit pvr2fb_pci_probe(struct pci_dev *pdev, | |
928 | const struct pci_device_id *ent) | |
929 | { | |
930 | int ret; | |
931 | ||
932 | ret = pci_enable_device(pdev); | |
933 | if (ret) { | |
934 | printk(KERN_ERR "pvr2fb: PCI enable failed\n"); | |
935 | return ret; | |
936 | } | |
937 | ||
938 | ret = pci_request_regions(pdev, "pvr2fb"); | |
939 | if (ret) { | |
940 | printk(KERN_ERR "pvr2fb: PCI request regions failed\n"); | |
941 | return ret; | |
942 | } | |
943 | ||
944 | /* | |
945 | * Slightly more exciting than the DC PVR2 .. 16MiB! | |
946 | */ | |
947 | pvr2_fix.smem_start = pci_resource_start(pdev, 0); | |
948 | pvr2_fix.smem_len = pci_resource_len(pdev, 0); | |
949 | ||
950 | pvr2_fix.mmio_start = pci_resource_start(pdev, 1); | |
951 | pvr2_fix.mmio_len = pci_resource_len(pdev, 1); | |
952 | ||
953 | fb_info->device = &pdev->dev; | |
954 | ||
955 | return pvr2fb_common_init(); | |
956 | } | |
957 | ||
958 | static void __devexit pvr2fb_pci_remove(struct pci_dev *pdev) | |
959 | { | |
295a1b47 AL |
960 | if (fb_info->screen_base) { |
961 | iounmap(fb_info->screen_base); | |
962 | fb_info->screen_base = NULL; | |
963 | } | |
964 | if (currentpar->mmio_base) { | |
965 | iounmap((void *)currentpar->mmio_base); | |
966 | currentpar->mmio_base = 0; | |
967 | } | |
968 | ||
1da177e4 LT |
969 | pci_release_regions(pdev); |
970 | } | |
971 | ||
972 | static struct pci_device_id pvr2fb_pci_tbl[] __devinitdata = { | |
973 | { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250, | |
974 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
975 | { 0, }, | |
976 | }; | |
977 | ||
978 | MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl); | |
979 | ||
980 | static struct pci_driver pvr2fb_pci_driver = { | |
981 | .name = "pvr2fb", | |
982 | .id_table = pvr2fb_pci_tbl, | |
983 | .probe = pvr2fb_pci_probe, | |
984 | .remove = __devexit_p(pvr2fb_pci_remove), | |
985 | }; | |
986 | ||
987 | static int __init pvr2fb_pci_init(void) | |
988 | { | |
989 | return pci_register_driver(&pvr2fb_pci_driver); | |
990 | } | |
991 | ||
e9705a77 | 992 | static void __exit pvr2fb_pci_exit(void) |
1da177e4 LT |
993 | { |
994 | pci_unregister_driver(&pvr2fb_pci_driver); | |
995 | } | |
996 | #endif /* CONFIG_PCI */ | |
997 | ||
7e7ec0d4 | 998 | static int __devinit pvr2_get_param(const struct pvr2_params *p, const char *s, |
1da177e4 LT |
999 | int val, int size) |
1000 | { | |
1001 | int i; | |
1002 | ||
1003 | for (i = 0 ; i < size ; i++ ) { | |
1004 | if (s != NULL) { | |
1005 | if (!strnicmp(p[i].name, s, strlen(s))) | |
1006 | return p[i].val; | |
1007 | } else { | |
1008 | if (p[i].val == val) | |
1009 | return (int)p[i].name; | |
1010 | } | |
1011 | } | |
1012 | return -1; | |
1013 | } | |
1014 | ||
1015 | /* | |
1016 | * Parse command arguments. Supported arguments are: | |
1017 | * inverse Use inverse color maps | |
1018 | * cable:composite|rgb|vga Override the video cable type | |
1019 | * output:NTSC|PAL|VGA Override the video output format | |
1020 | * | |
1021 | * <xres>x<yres>[-<bpp>][@<refresh>] or, | |
1022 | * <name>[-<bpp>][@<refresh>] Startup using this video mode | |
1023 | */ | |
1024 | ||
1025 | #ifndef MODULE | |
e9705a77 | 1026 | static int __init pvr2fb_setup(char *options) |
1da177e4 LT |
1027 | { |
1028 | char *this_opt; | |
1029 | char cable_arg[80]; | |
1030 | char output_arg[80]; | |
1031 | ||
1032 | if (!options || !*options) | |
1033 | return 0; | |
1034 | ||
1035 | while ((this_opt = strsep(&options, ","))) { | |
1036 | if (!*this_opt) | |
1037 | continue; | |
1038 | if (!strcmp(this_opt, "inverse")) { | |
1039 | fb_invert_cmaps(); | |
1040 | } else if (!strncmp(this_opt, "cable:", 6)) { | |
1041 | strcpy(cable_arg, this_opt + 6); | |
1042 | } else if (!strncmp(this_opt, "output:", 7)) { | |
1043 | strcpy(output_arg, this_opt + 7); | |
1044 | } else if (!strncmp(this_opt, "nopan", 5)) { | |
1045 | nopan = 1; | |
1046 | } else if (!strncmp(this_opt, "nowrap", 6)) { | |
1047 | nowrap = 1; | |
1048 | } else { | |
1049 | mode_option = this_opt; | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | if (*cable_arg) | |
1054 | cable_type = pvr2_get_param(cables, cable_arg, 0, 3); | |
1055 | if (*output_arg) | |
1056 | video_output = pvr2_get_param(outputs, output_arg, 0, 3); | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | #endif | |
1061 | ||
1062 | static struct pvr2_board { | |
1063 | int (*init)(void); | |
1064 | void (*exit)(void); | |
1065 | char name[16]; | |
e9705a77 | 1066 | } board_driver[] = { |
1da177e4 LT |
1067 | #ifdef CONFIG_SH_DREAMCAST |
1068 | { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" }, | |
1069 | #endif | |
1070 | #ifdef CONFIG_PCI | |
1071 | { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" }, | |
1072 | #endif | |
1073 | { 0, }, | |
1074 | }; | |
1075 | ||
e9705a77 | 1076 | static int __init pvr2fb_init(void) |
1da177e4 LT |
1077 | { |
1078 | int i, ret = -ENODEV; | |
1079 | int size; | |
1080 | ||
1081 | #ifndef MODULE | |
1082 | char *option = NULL; | |
1083 | ||
1084 | if (fb_get_options("pvr2fb", &option)) | |
1085 | return -ENODEV; | |
1086 | pvr2fb_setup(option); | |
1087 | #endif | |
1088 | size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32); | |
1089 | ||
9cd1c674 AD |
1090 | fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL); |
1091 | ||
1da177e4 LT |
1092 | if (!fb_info) { |
1093 | printk(KERN_ERR "Failed to allocate memory for fb_info\n"); | |
1094 | return -ENOMEM; | |
1095 | } | |
1096 | ||
1da177e4 | 1097 | |
9cd1c674 | 1098 | currentpar = fb_info->par; |
1da177e4 | 1099 | |
e9705a77 PM |
1100 | for (i = 0; i < ARRAY_SIZE(board_driver); i++) { |
1101 | struct pvr2_board *pvr_board = board_driver + i; | |
1da177e4 LT |
1102 | |
1103 | if (!pvr_board->init) | |
1104 | continue; | |
1105 | ||
1106 | ret = pvr_board->init(); | |
1107 | ||
1108 | if (ret != 0) { | |
1109 | printk(KERN_ERR "pvr2fb: Failed init of %s device\n", | |
1110 | pvr_board->name); | |
9cd1c674 | 1111 | framebuffer_release(fb_info); |
1da177e4 LT |
1112 | break; |
1113 | } | |
1114 | } | |
1115 | ||
1116 | return ret; | |
1117 | } | |
1118 | ||
1119 | static void __exit pvr2fb_exit(void) | |
1120 | { | |
1121 | int i; | |
1122 | ||
e9705a77 PM |
1123 | for (i = 0; i < ARRAY_SIZE(board_driver); i++) { |
1124 | struct pvr2_board *pvr_board = board_driver + i; | |
1da177e4 LT |
1125 | |
1126 | if (pvr_board->exit) | |
1127 | pvr_board->exit(); | |
1128 | } | |
e9705a77 | 1129 | |
1da177e4 LT |
1130 | #ifdef CONFIG_SH_STORE_QUEUES |
1131 | sq_unmap(pvr2fb_map); | |
1132 | #endif | |
1133 | ||
1134 | unregister_framebuffer(fb_info); | |
9cd1c674 | 1135 | framebuffer_release(fb_info); |
1da177e4 LT |
1136 | } |
1137 | ||
1138 | module_init(pvr2fb_init); | |
1139 | module_exit(pvr2fb_exit); | |
1140 | ||
1141 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>"); | |
1142 | MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards"); | |
1143 | MODULE_LICENSE("GPL"); |