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pm3fb: 3 small fixes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pm3fb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
f23a06f0
KH		 3 *
4 * Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
5 *
6 * Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
7 * based on pm2fb.c
8 *
1da177e4 9 * Based on code written by:
f23a06f0
KH		 10 * Sven Luther, <luther@dpt-info.u-strasbg.fr>
11 * Alan Hourihane, <alanh@fairlite.demon.co.uk>
12 * Russell King, <rmk@arm.linux.org.uk>
1da177e4
LT		 13 * Based on linux/drivers/video/skeletonfb.c:
14 * Copyright (C) 1997 Geert Uytterhoeven
15 * Based on linux/driver/video/pm2fb.c:
f23a06f0
KH		 16 * Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
17 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
1da177e4
LT		 18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file COPYING in the main directory of this archive for
21 * more details.
22 *
1da177e4
LT		 23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/mm.h>
1da177e4 30#include <linux/slab.h>
1da177e4 31#include <linux/delay.h>
1da177e4
LT		 32#include <linux/fb.h>
33#include <linux/init.h>
34#include <linux/pci.h>
1da177e4 35
f23a06f0 36#include <video/pm3fb.h>
1da177e4 37
f23a06f0
KH		 38#if !defined(CONFIG_PCI)
39#error "Only generic PCI cards supported."
1da177e4
LT		 40#endif
41
f23a06f0
KH		 42#undef PM3FB_MASTER_DEBUG
43#ifdef PM3FB_MASTER_DEBUG
44#define DPRINTK(a,b...) printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
45#else
46#define DPRINTK(a,b...)
1da177e4 47#endif
1da177e4 48
b0a318e2
KH		 49#define PM3_PIXMAP_SIZE (2048 * 4)
50
f23a06f0
KH		 51/*
52 * Driver data
53 */
54static char *mode_option __devinitdata;
1da177e4 55
f23a06f0
KH		 56/*
57 * This structure defines the hardware state of the graphics card. Normally
58 * you place this in a header file in linux/include/video. This file usually
59 * also includes register information. That allows other driver subsystems
60 * and userland applications the ability to use the same header file to
61 * avoid duplicate work and easy porting of software.
62 */
63struct pm3_par {
64 unsigned char __iomem *v_regs;/* virtual address of p_regs */
65 u32 video; /* video flags before blanking */
66 u32 base; /* screen base (xoffset+yoffset) in 128 bits unit */
2686ba89 67 u32 palette[16];
1da177e4
LT		 68};
69
f23a06f0
KH		 70/*
71 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
72 * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
73 * to get a fb_var_screeninfo. Otherwise define a default var as well.
74 */
75static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
76 .id = "Permedia3",
77 .type = FB_TYPE_PACKED_PIXELS,
78 .visual = FB_VISUAL_PSEUDOCOLOR,
79 .xpanstep = 1,
80 .ypanstep = 1,
81 .ywrapstep = 0,
a58d67ce 82 .accel = FB_ACCEL_3DLABS_PERMEDIA3,
1da177e4
LT		 83};
84
f23a06f0
KH		 85/*
86 * Utility functions
87 */
1da177e4 88
f23a06f0
KH		 89static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
90{
91 return fb_readl(par->v_regs + off);
92}
1da177e4 93
f23a06f0
KH		 94static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
95{
96 fb_writel(v, par->v_regs + off);
97}
1da177e4 98
f23a06f0
KH		 99static inline void PM3_WAIT(struct pm3_par *par, u32 n)
100{
101 while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
1da177e4
LT		 102}
103
f23a06f0 104static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
1da177e4 105{
2686ba89
KH		 106 PM3_WAIT(par, 3);
107 PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
108 PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
f23a06f0
KH		 109 wmb();
110 PM3_WRITE_REG(par, PM3RD_IndexedData, v);
2686ba89 111 wmb();
1da177e4
LT		 112}
113
f23a06f0
KH		 114static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
115 unsigned char r, unsigned char g, unsigned char b)
1da177e4 116{
2686ba89
KH		 117 PM3_WAIT(par, 4);
118 PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
119 wmb();
120 PM3_WRITE_REG(par, PM3RD_PaletteData, r);
121 wmb();
122 PM3_WRITE_REG(par, PM3RD_PaletteData, g);
123 wmb();
124 PM3_WRITE_REG(par, PM3RD_PaletteData, b);
125 wmb();
f23a06f0
KH		 126}
127
128static void pm3fb_clear_colormap(struct pm3_par *par,
129 unsigned char r, unsigned char g, unsigned char b)
130{
131 int i;
132
2686ba89 133 for (i = 0; i < 256 ; i++)
f23a06f0
KH		 134 pm3fb_set_color(par, i, r, g, b);
135
1da177e4
LT		 136}
137
138/* Calculating various clock parameter */
f23a06f0
KH		 139static void pm3fb_calculate_clock(unsigned long reqclock,
140 unsigned char *prescale,
141 unsigned char *feedback,
142 unsigned char *postscale)
1da177e4
LT		 143{
144 int f, pre, post;
145 unsigned long freq;
146 long freqerr = 1000;
f23a06f0 147 long currerr;
1da177e4
LT		 148
149 for (f = 1; f < 256; f++) {
150 for (pre = 1; pre < 256; pre++) {
151 for (post = 0; post < 5; post++) {
f23a06f0
KH		 152 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
153 currerr = (reqclock > freq)
154 ? reqclock - freq
155 : freq - reqclock;
156 if (currerr < freqerr) {
157 freqerr = currerr;
1da177e4
LT		 158 *feedback = f;
159 *prescale = pre;
160 *postscale = post;
1da177e4
LT		 161 }
162 }
163 }
164 }
1da177e4
LT		 165}
166
2686ba89 167static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
1da177e4 168{
2686ba89
KH		 169 if ( var->bits_per_pixel == 16 )
170 return var->red.length + var->green.length
171 + var->blue.length;
172
173 return var->bits_per_pixel;
174}
175
176static inline int pm3fb_shift_bpp(unsigned bpp, int v)
177{
178 switch (bpp) {
1da177e4
LT		 179 case 8:
180 return (v >> 4);
1da177e4
LT		 181 case 16:
182 return (v >> 3);
183 case 32:
184 return (v >> 2);
185 }
2686ba89 186 DPRINTK("Unsupported depth %u\n", bpp);
f23a06f0 187 return 0;
1da177e4
LT		 188}
189
a58d67ce
KH		 190/* acceleration */
191static int pm3fb_sync(struct fb_info *info)
192{
193 struct pm3_par *par = info->par;
194
195 PM3_WAIT(par, 2);
196 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
197 PM3_WRITE_REG(par, PM3Sync, 0);
198 mb();
199 do {
200 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0);
201 rmb();
202 } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
203
204 return 0;
205}
206
207static void pm3fb_init_engine(struct fb_info *info)
208{
209 struct pm3_par *par = info->par;
210 const u32 width = (info->var.xres_virtual + 7) & ~7;
211
212 PM3_WAIT(par, 50);
213 PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
214 PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
215 PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
216 PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
217 PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
218 PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
219 PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
220 PM3_WRITE_REG(par, PM3GIDMode, 0x0);
221 PM3_WRITE_REG(par, PM3DepthMode, 0x0);
222 PM3_WRITE_REG(par, PM3StencilMode, 0x0);
223 PM3_WRITE_REG(par, PM3StencilData, 0x0);
224 PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
225 PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
226 PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
227 PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
228 PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
229 PM3_WRITE_REG(par, PM3LUTMode, 0x0);
230 PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
231 PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
232 PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
233 PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
234 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
235 PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
236 PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
237 PM3_WRITE_REG(par, PM3FogMode, 0x0);
238 PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
239 PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
240 PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
241 PM3_WRITE_REG(par, PM3YUVMode, 0x0);
242 PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
243 PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
244 PM3_WRITE_REG(par, PM3DitherMode, 0x0);
245 PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
246 PM3_WRITE_REG(par, PM3RouterMode, 0x0);
247 PM3_WRITE_REG(par, PM3Window, 0x0);
248
249 PM3_WRITE_REG(par, PM3Config2D, 0x0);
250
251 PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
252
253 PM3_WRITE_REG(par, PM3XBias, 0x0);
254 PM3_WRITE_REG(par, PM3YBias, 0x0);
255 PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
256
257 PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
258
259 PM3_WRITE_REG(par, PM3FBDestReadEnables,
260 PM3FBDestReadEnables_E(0xff) |
261 PM3FBDestReadEnables_R(0xff) |
262 PM3FBDestReadEnables_ReferenceAlpha(0xff));
263 PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
264 PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
265 PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
266 PM3FBDestReadBufferWidth_Width(width));
267
268 PM3_WRITE_REG(par, PM3FBDestReadMode,
269 PM3FBDestReadMode_ReadEnable |
270 PM3FBDestReadMode_Enable0);
271 PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
272 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
273 PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
274 PM3FBSourceReadBufferWidth_Width(width));
275 PM3_WRITE_REG(par, PM3FBSourceReadMode,
276 PM3FBSourceReadMode_Blocking |
277 PM3FBSourceReadMode_ReadEnable);
278
279 PM3_WAIT(par, 2);
280 {
e7f76df9
KH		 281 /* invert bits in bitmask */
282 unsigned long rm = 1 | (3 << 7);
a58d67ce
KH		 283 switch (info->var.bits_per_pixel) {
284 case 8:
285 PM3_WRITE_REG(par, PM3PixelSize,
286 PM3PixelSize_GLOBAL_8BIT);
e7f76df9
KH		 287#ifdef __BIG_ENDIAN
288 rm |= 3 << 15;
289#endif
a58d67ce
KH		 290 break;
291 case 16:
292 PM3_WRITE_REG(par, PM3PixelSize,
293 PM3PixelSize_GLOBAL_16BIT);
e7f76df9
KH		 294#ifdef __BIG_ENDIAN
295 rm |= 2 << 15;
296#endif
a58d67ce
KH		 297 break;
298 case 32:
299 PM3_WRITE_REG(par, PM3PixelSize,
300 PM3PixelSize_GLOBAL_32BIT);
301 break;
302 default:
303 DPRINTK(1, "Unsupported depth %d\n",
304 info->var.bits_per_pixel);
305 break;
306 }
307 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
308 }
309
310 PM3_WAIT(par, 20);
311 PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
312 PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
313 PM3_WRITE_REG(par, PM3FBWriteMode,
314 PM3FBWriteMode_WriteEnable |
315 PM3FBWriteMode_OpaqueSpan |
316 PM3FBWriteMode_Enable0);
317 PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
318 PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
319 PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
320 PM3FBWriteBufferWidth_Width(width));
321
322 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
323 {
324 /* size in lines of FB */
325 unsigned long sofb = info->screen_size /
326 info->fix.line_length;
327 if (sofb > 4095)
328 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
329 else
330 PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
331
332 switch (info->var.bits_per_pixel) {
333 case 8:
334 PM3_WRITE_REG(par, PM3DitherMode,
335 (1 << 10) | (2 << 3));
336 break;
337 case 16:
338 PM3_WRITE_REG(par, PM3DitherMode,
339 (1 << 10) | (1 << 3));
340 break;
341 case 32:
342 PM3_WRITE_REG(par, PM3DitherMode,
343 (1 << 10) | (0 << 3));
344 break;
345 default:
346 DPRINTK(1, "Unsupported depth %d\n",
347 info->current_par->depth);
348 break;
349 }
350 }
351
352 PM3_WRITE_REG(par, PM3dXDom, 0x0);
353 PM3_WRITE_REG(par, PM3dXSub, 0x0);
354 PM3_WRITE_REG(par, PM3dY, (1 << 16));
355 PM3_WRITE_REG(par, PM3StartXDom, 0x0);
356 PM3_WRITE_REG(par, PM3StartXSub, 0x0);
357 PM3_WRITE_REG(par, PM3StartY, 0x0);
358 PM3_WRITE_REG(par, PM3Count, 0x0);
359
360/* Disable LocalBuffer. better safe than sorry */
361 PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
362 PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
363 PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
364 PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
365
366 pm3fb_sync(info);
367}
368
369static void pm3fb_fillrect (struct fb_info *info,
370 const struct fb_fillrect *region)
371{
372 struct pm3_par *par = info->par;
373 struct fb_fillrect modded;
374 int vxres, vyres;
375 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
376 ((u32*)info->pseudo_palette)[region->color] : region->color;
377
378 if (info->state != FBINFO_STATE_RUNNING)
379 return;
380 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
381 region->rop != ROP_COPY ) {
382 cfb_fillrect(info, region);
383 return;
384 }
385
386 vxres = info->var.xres_virtual;
387 vyres = info->var.yres_virtual;
388
389 memcpy(&modded, region, sizeof(struct fb_fillrect));
390
391 if(!modded.width || !modded.height ||
392 modded.dx >= vxres || modded.dy >= vyres)
393 return;
394
395 if(modded.dx + modded.width > vxres)
396 modded.width = vxres - modded.dx;
397 if(modded.dy + modded.height > vyres)
398 modded.height = vyres - modded.dy;
399
400 if(info->var.bits_per_pixel == 8)
401 color |= color << 8;
402 if(info->var.bits_per_pixel <= 16)
403 color |= color << 16;
404
405 PM3_WAIT(par, 4);
e7f76df9 406 /* ROP Ox3 is GXcopy */
a58d67ce 407 PM3_WRITE_REG(par, PM3Config2D,
e7f76df9
KH		 408 PM3Config2D_UseConstantSource |
409 PM3Config2D_ForegroundROPEnable |
410 (PM3Config2D_ForegroundROP(0x3)) |
411 PM3Config2D_FBWriteEnable);
a58d67ce
KH		 412
413 PM3_WRITE_REG(par, PM3ForegroundColor, color);
414
415 PM3_WRITE_REG(par, PM3RectanglePosition,
e7f76df9
KH		 416 (PM3RectanglePosition_XOffset(modded.dx)) |
417 (PM3RectanglePosition_YOffset(modded.dy)));
a58d67ce
KH		 418
419 PM3_WRITE_REG(par, PM3Render2D,
420 PM3Render2D_XPositive |
421 PM3Render2D_YPositive |
422 PM3Render2D_Operation_Normal |
423 PM3Render2D_SpanOperation |
424 (PM3Render2D_Width(modded.width)) |
425 (PM3Render2D_Height(modded.height)));
426}
e7f76df9
KH		 427
428static void pm3fb_copyarea(struct fb_info *info,
429 const struct fb_copyarea *area)
430{
431 struct pm3_par *par = info->par;
432 struct fb_copyarea modded;
433 u32 vxres, vyres;
434 int x_align, o_x, o_y;
435
436 if (info->state != FBINFO_STATE_RUNNING)
437 return;
438 if (info->flags & FBINFO_HWACCEL_DISABLED) {
439 cfb_copyarea(info, area);
440 return;
441 }
442
443 memcpy(&modded, area, sizeof(struct fb_copyarea));
444
445 vxres = info->var.xres_virtual;
446 vyres = info->var.yres_virtual;
447
448 if(!modded.width || !modded.height ||
449 modded.sx >= vxres || modded.sy >= vyres ||
450 modded.dx >= vxres || modded.dy >= vyres)
451 return;
452
453 if(modded.sx + modded.width > vxres)
454 modded.width = vxres - modded.sx;
455 if(modded.dx + modded.width > vxres)
456 modded.width = vxres - modded.dx;
457 if(modded.sy + modded.height > vyres)
458 modded.height = vyres - modded.sy;
459 if(modded.dy + modded.height > vyres)
460 modded.height = vyres - modded.dy;
461
462 o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
463 o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
464
465 x_align = (modded.sx & 0x1f);
466
467 PM3_WAIT(par, 6);
468
469 PM3_WRITE_REG(par, PM3Config2D,
470 PM3Config2D_UserScissorEnable |
471 PM3Config2D_ForegroundROPEnable |
472 PM3Config2D_Blocking |
473 (PM3Config2D_ForegroundROP(0x3)) | /* Ox3 is GXcopy */
474 PM3Config2D_FBWriteEnable);
475
476 PM3_WRITE_REG(par, PM3ScissorMinXY,
477 ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
478 PM3_WRITE_REG(par, PM3ScissorMaxXY,
479 (((modded.dy + modded.height) & 0x0fff) << 16) |
480 ((modded.dx + modded.width) & 0x0fff));
481
482 PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
483 PM3FBSourceReadBufferOffset_XOffset(o_x) |
484 PM3FBSourceReadBufferOffset_YOffset(o_y));
485
486 PM3_WRITE_REG(par, PM3RectanglePosition,
487 (PM3RectanglePosition_XOffset(modded.dx - x_align)) |
488 (PM3RectanglePosition_YOffset(modded.dy)));
489
490 PM3_WRITE_REG(par, PM3Render2D,
491 ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
492 ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
493 PM3Render2D_Operation_Normal |
494 PM3Render2D_SpanOperation |
495 PM3Render2D_FBSourceReadEnable |
496 (PM3Render2D_Width(modded.width + x_align)) |
497 (PM3Render2D_Height(modded.height)));
498}
499
500static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
501{
502 struct pm3_par *par = info->par;
503 u32 height = image->height;
504 u32 fgx, bgx;
505 const u32 *src = (const u32*)image->data;
506
507 switch (info->fix.visual) {
508 case FB_VISUAL_PSEUDOCOLOR:
509 fgx = image->fg_color;
510 bgx = image->bg_color;
511 break;
512 case FB_VISUAL_TRUECOLOR:
513 default:
514 fgx = par->palette[image->fg_color];
515 bgx = par->palette[image->bg_color];
516 break;
517 }
b0a318e2 518 if (image->depth != 1) {
e7f76df9
KH		 519 return cfb_imageblit(info, image);
520 }
521 if (info->var.bits_per_pixel == 8) {
522 fgx |= fgx << 8;
523 bgx |= bgx << 8;
524 }
525 if (info->var.bits_per_pixel <= 16) {
526 fgx |= fgx << 16;
527 bgx |= bgx << 16;
528 }
529
b0a318e2 530 PM3_WAIT(par, 7);
e7f76df9
KH		 531
532 PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
533 PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
534
535 /* ROP Ox3 is GXcopy */
536 PM3_WRITE_REG(par, PM3Config2D,
b0a318e2 537 PM3Config2D_UserScissorEnable |
e7f76df9
KH		 538 PM3Config2D_UseConstantSource |
539 PM3Config2D_ForegroundROPEnable |
540 (PM3Config2D_ForegroundROP(0x3)) |
541 PM3Config2D_OpaqueSpan |
542 PM3Config2D_FBWriteEnable);
b0a318e2
KH		 543 PM3_WRITE_REG(par, PM3ScissorMinXY,
544 ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
545 PM3_WRITE_REG(par, PM3ScissorMaxXY,
546 (((image->dy + image->height) & 0x0fff) << 16) |
547 ((image->dx + image->width) & 0x0fff));
e7f76df9
KH		 548 PM3_WRITE_REG(par, PM3RectanglePosition,
549 (PM3RectanglePosition_XOffset(image->dx)) |
550 (PM3RectanglePosition_YOffset(image->dy)));
551 PM3_WRITE_REG(par, PM3Render2D,
552 PM3Render2D_XPositive |
553 PM3Render2D_YPositive |
554 PM3Render2D_Operation_SyncOnBitMask |
555 PM3Render2D_SpanOperation |
556 (PM3Render2D_Width(image->width)) |
557 (PM3Render2D_Height(image->height)));
558
559
560 while (height--) {
c79ba28c
KH		 561 int width = ((image->width + 7) >> 3)
562 + info->pixmap.scan_align - 1;
b0a318e2 563 width >>= 2;
e7f76df9
KH		 564
565 while (width >= PM3_FIFO_SIZE) {
566 int i = PM3_FIFO_SIZE - 1;
567
568 PM3_WAIT(par, PM3_FIFO_SIZE);
569 while (i--) {
570 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
571 src++;
572 }
573 width -= PM3_FIFO_SIZE - 1;
574 }
575
576 PM3_WAIT(par, width + 1);
577 while (width--) {
578 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
579 src++;
580 }
581 }
582}
a58d67ce
KH		 583/* end of acceleration functions */
584
1da177e4 585/* write the mode to registers */
f23a06f0 586static void pm3fb_write_mode(struct fb_info *info)
1da177e4 587{
f23a06f0 588 struct pm3_par *par = info->par;
1da177e4 589 char tempsync = 0x00, tempmisc = 0x00;
f23a06f0
KH		 590 const u32 hsstart = info->var.right_margin;
591 const u32 hsend = hsstart + info->var.hsync_len;
592 const u32 hbend = hsend + info->var.left_margin;
593 const u32 xres = (info->var.xres + 31) & ~31;
594 const u32 htotal = xres + hbend;
595 const u32 vsstart = info->var.lower_margin;
596 const u32 vsend = vsstart + info->var.vsync_len;
597 const u32 vbend = vsend + info->var.upper_margin;
598 const u32 vtotal = info->var.yres + vbend;
599 const u32 width = (info->var.xres_virtual + 7) & ~7;
2686ba89
KH		 600 const unsigned bpp = info->var.bits_per_pixel;
601
602 PM3_WAIT(par, 20);
603 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
604 PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
605 PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
606 PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
607
608 PM3_WRITE_REG(par, PM3HTotal,
609 pm3fb_shift_bpp(bpp, htotal - 1));
610 PM3_WRITE_REG(par, PM3HsEnd,
611 pm3fb_shift_bpp(bpp, hsend));
612 PM3_WRITE_REG(par, PM3HsStart,
613 pm3fb_shift_bpp(bpp, hsstart));
614 PM3_WRITE_REG(par, PM3HbEnd,
615 pm3fb_shift_bpp(bpp, hbend));
616 PM3_WRITE_REG(par, PM3HgEnd,
617 pm3fb_shift_bpp(bpp, hbend));
618 PM3_WRITE_REG(par, PM3ScreenStride,
619 pm3fb_shift_bpp(bpp, width));
620 PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
621 PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
622 PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
623 PM3_WRITE_REG(par, PM3VbEnd, vbend);
624
625 switch (bpp) {
1da177e4 626 case 8:
2686ba89 627 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4 628 PM3ByApertureMode_PIXELSIZE_8BIT);
2686ba89 629 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 630 PM3ByApertureMode_PIXELSIZE_8BIT);
631 break;
632
1da177e4
LT		 633 case 16:
634#ifndef __BIG_ENDIAN
2686ba89 635 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4 636 PM3ByApertureMode_PIXELSIZE_16BIT);
2686ba89 637 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 638 PM3ByApertureMode_PIXELSIZE_16BIT);
639#else
2686ba89 640 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4
LT		 641 PM3ByApertureMode_PIXELSIZE_16BIT |
642 PM3ByApertureMode_BYTESWAP_BADC);
2686ba89 643 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 644 PM3ByApertureMode_PIXELSIZE_16BIT |
645 PM3ByApertureMode_BYTESWAP_BADC);
646#endif /* ! __BIG_ENDIAN */
647 break;
648
649 case 32:
650#ifndef __BIG_ENDIAN
2686ba89 651 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4 652 PM3ByApertureMode_PIXELSIZE_32BIT);
2686ba89 653 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 654 PM3ByApertureMode_PIXELSIZE_32BIT);
655#else
2686ba89 656 PM3_WRITE_REG(par, PM3ByAperture1Mode,
1da177e4
LT		 657 PM3ByApertureMode_PIXELSIZE_32BIT |
658 PM3ByApertureMode_BYTESWAP_DCBA);
2686ba89 659 PM3_WRITE_REG(par, PM3ByAperture2Mode,
1da177e4
LT		 660 PM3ByApertureMode_PIXELSIZE_32BIT |
661 PM3ByApertureMode_BYTESWAP_DCBA);
662#endif /* ! __BIG_ENDIAN */
663 break;
664
665 default:
2686ba89 666 DPRINTK("Unsupported depth %d\n", bpp);
1da177e4
LT		 667 break;
668 }
669
670 /*
671 * Oxygen VX1 - it appears that setting PM3VideoControl and
672 * then PM3RD_SyncControl to the same SYNC settings undoes
673 * any net change - they seem to xor together. Only set the
674 * sync options in PM3RD_SyncControl. --rmk
675 */
676 {
f23a06f0 677 unsigned int video = par->video;
1da177e4
LT		 678
679 video &= ~(PM3VideoControl_HSYNC_MASK |
680 PM3VideoControl_VSYNC_MASK);
681 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
682 PM3VideoControl_VSYNC_ACTIVE_HIGH;
2686ba89 683 PM3_WRITE_REG(par, PM3VideoControl, video);
1da177e4 684 }
2686ba89 685 PM3_WRITE_REG(par, PM3VClkCtl,
f23a06f0 686 (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
2686ba89
KH		 687 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
688 PM3_WRITE_REG(par, PM3ChipConfig,
f23a06f0 689 (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
1da177e4 690
2686ba89 691 wmb();
1da177e4 692 {
f23a06f0
KH		 693 unsigned char uninitialized_var(m); /* ClkPreScale */
694 unsigned char uninitialized_var(n); /* ClkFeedBackScale */
695 unsigned char uninitialized_var(p); /* ClkPostScale */
696 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
697
698 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
699
700 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
701 pixclock, (int) m, (int) n, (int) p);
702
703 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
704 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
705 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
1da177e4
LT		 706 }
707 /*
f23a06f0 708 PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
1da177e4
LT		 709 */
710 /*
f23a06f0 711 PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
1da177e4 712 */
f23a06f0 713 if ((par->video & PM3VideoControl_HSYNC_MASK) ==
1da177e4
LT		 714 PM3VideoControl_HSYNC_ACTIVE_HIGH)
715 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
f23a06f0 716 if ((par->video & PM3VideoControl_VSYNC_MASK) ==
1da177e4
LT		 717 PM3VideoControl_VSYNC_ACTIVE_HIGH)
718 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
1da177e4 719
f23a06f0
KH		 720 PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
721 DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
722
723 PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
724
2686ba89 725 switch (pm3fb_depth(&info->var)) {
1da177e4 726 case 8:
f23a06f0 727 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 728 PM3RD_PixelSize_8_BIT_PIXELS);
f23a06f0 729 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 730 PM3RD_ColorFormat_CI8_COLOR |
731 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
732 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
733 break;
734 case 12:
f23a06f0 735 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 736 PM3RD_PixelSize_16_BIT_PIXELS);
f23a06f0 737 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 738 PM3RD_ColorFormat_4444_COLOR |
739 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
740 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
741 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
742 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
f23a06f0 743 break;
1da177e4 744 case 15:
f23a06f0 745 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 746 PM3RD_PixelSize_16_BIT_PIXELS);
f23a06f0 747 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 748 PM3RD_ColorFormat_5551_FRONT_COLOR |
749 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
750 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
751 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
752 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
f23a06f0 753 break;
1da177e4 754 case 16:
f23a06f0 755 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 756 PM3RD_PixelSize_16_BIT_PIXELS);
f23a06f0 757 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 758 PM3RD_ColorFormat_565_FRONT_COLOR |
759 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
760 PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
761 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
762 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
763 break;
764 case 32:
f23a06f0 765 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
1da177e4 766 PM3RD_PixelSize_32_BIT_PIXELS);
f23a06f0 767 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
1da177e4
LT		 768 PM3RD_ColorFormat_8888_COLOR |
769 PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
770 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
771 PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
772 break;
773 }
f23a06f0 774 PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
1da177e4
LT		 775}
776
f23a06f0
KH		 777/*
778 * hardware independent functions
779 */
f23a06f0
KH		 780static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
781{
782 u32 lpitch;
2686ba89
KH		 783 unsigned bpp = var->red.length + var->green.length
784 + var->blue.length + var->transp.length;
1da177e4 785
2686ba89
KH		 786 if ( bpp != var->bits_per_pixel ) {
787 /* set predefined mode for bits_per_pixel settings */
788
789 switch(var->bits_per_pixel) {
790 case 8:
791 var->red.length = var->green.length = var->blue.length = 8;
792 var->red.offset = var->green.offset = var->blue.offset = 0;
793 var->transp.offset = 0;
794 var->transp.length = 0;
795 break;
796 case 16:
797 var->red.length = var->blue.length = 5;
798 var->green.length = 6;
799 var->transp.length = 0;
800 break;
801 case 32:
802 var->red.length = var->green.length = var->blue.length = 8;
803 var->transp.length = 8;
804 break;
805 default:
806 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
807 return -EINVAL;
808 }
809 }
810 /* it is assumed BGRA order */
811 if (var->bits_per_pixel > 8 )
812 {
813 var->blue.offset = 0;
814 var->green.offset = var->blue.length;
815 var->red.offset = var->green.offset + var->green.length;
816 var->transp.offset = var->red.offset + var->red.length;
1da177e4 817 }
f23a06f0 818 var->height = var->width = -1;
1da177e4 819
f23a06f0
KH		 820 if (var->xres != var->xres_virtual) {
821 DPRINTK("virtual x resolution != physical x resolution not supported\n");
822 return -EINVAL;
823 }
1da177e4 824
f23a06f0
KH		 825 if (var->yres > var->yres_virtual) {
826 DPRINTK("virtual y resolution < physical y resolution not possible\n");
827 return -EINVAL;
1da177e4 828 }
1da177e4 829
f23a06f0
KH		 830 if (var->xoffset) {
831 DPRINTK("xoffset not supported\n");
832 return -EINVAL;
1da177e4
LT		 833 }
834
f23a06f0
KH		 835 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
836 DPRINTK("interlace not supported\n");
837 return -EINVAL;
1da177e4 838 }
1da177e4 839
f23a06f0
KH		 840 var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
841 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
1da177e4 842
f23a06f0
KH		 843 if (var->xres < 200 || var->xres > 2048) {
844 DPRINTK("width not supported: %u\n", var->xres);
845 return -EINVAL;
846 }
1da177e4 847
f23a06f0
KH		 848 if (var->yres < 200 || var->yres > 4095) {
849 DPRINTK("height not supported: %u\n", var->yres);
850 return -EINVAL;
851 }
1da177e4 852
f23a06f0
KH		 853 if (lpitch * var->yres_virtual > info->fix.smem_len) {
854 DPRINTK("no memory for screen (%ux%ux%u)\n",
855 var->xres, var->yres_virtual, var->bits_per_pixel);
856 return -EINVAL;
857 }
858
859 if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
860 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
861 return -EINVAL;
1da177e4
LT		 862 }
863
f23a06f0 864 var->accel_flags = 0; /* Can't mmap if this is on */
1da177e4 865
f23a06f0
KH		 866 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
867 var->xres, var->yres, var->bits_per_pixel);
868 return 0;
869}
1da177e4 870
f23a06f0
KH		 871static int pm3fb_set_par(struct fb_info *info)
872{
873 struct pm3_par *par = info->par;
874 const u32 xres = (info->var.xres + 31) & ~31;
2686ba89 875 const unsigned bpp = info->var.bits_per_pixel;
1da177e4 876
2686ba89 877 par->base = pm3fb_shift_bpp(bpp,(info->var.yoffset * xres)
f23a06f0
KH		 878 + info->var.xoffset);
879 par->video = 0;
1da177e4 880
f23a06f0
KH		 881 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
882 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
883 else
884 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
1da177e4 885
f23a06f0
KH		 886 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
887 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
888 else
889 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
1da177e4 890
f23a06f0
KH		 891 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
892 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
893 else
894 par->video |= PM3VideoControl_LINE_DOUBLE_OFF;
1da177e4 895
0bd327ef 896 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
f23a06f0
KH		 897 par->video |= PM3VideoControl_ENABLE;
898 else {
f259ebb6 899 par->video &= ~PM3VideoControl_ENABLE;
f23a06f0 900 DPRINTK("PM3Video disabled\n");
1da177e4 901 }
2686ba89 902 switch (bpp) {
f23a06f0
KH		 903 case 8:
904 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
905 break;
f23a06f0
KH		 906 case 16:
907 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
908 break;
909 case 32:
910 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
911 break;
912 default:
913 DPRINTK("Unsupported depth\n");
914 break;
1da177e4 915 }
1da177e4 916
f23a06f0 917 info->fix.visual =
2686ba89 918 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
f23a06f0 919 info->fix.line_length = ((info->var.xres_virtual + 7) & ~7)
2686ba89 920 * bpp / 8;
1da177e4 921
f23a06f0
KH		 922/* pm3fb_clear_memory(info, 0);*/
923 pm3fb_clear_colormap(par, 0, 0, 0);
f259ebb6 924 PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
a58d67ce 925 pm3fb_init_engine(info);
f23a06f0
KH		 926 pm3fb_write_mode(info);
927 return 0;
1da177e4
LT		 928}
929
f23a06f0
KH		 930static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
931 unsigned blue, unsigned transp,
932 struct fb_info *info)
1da177e4 933{
f23a06f0
KH		 934 struct pm3_par *par = info->par;
935
936 if (regno >= 256) /* no. of hw registers */
937 return -EINVAL;
938
939 /* grayscale works only partially under directcolor */
940 if (info->var.grayscale) {
941 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
942 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
943 }
944
945 /* Directcolor:
946 * var->{color}.offset contains start of bitfield
947 * var->{color}.length contains length of bitfield
948 * {hardwarespecific} contains width of DAC
949 * pseudo_palette[X] is programmed to (X << red.offset) |
2686ba89
KH		 950 * (X << green.offset) |
951 * (X << blue.offset)
f23a06f0
KH		 952 * RAMDAC[X] is programmed to (red, green, blue)
953 * color depth = SUM(var->{color}.length)
954 *
955 * Pseudocolor:
956 * var->{color}.offset is 0
957 * var->{color}.length contains width of DAC or the number of unique
958 * colors available (color depth)
959 * pseudo_palette is not used
960 * RAMDAC[X] is programmed to (red, green, blue)
961 * color depth = var->{color}.length
962 */
1da177e4 963
f23a06f0
KH		 964 /*
965 * This is the point where the color is converted to something that
966 * is acceptable by the hardware.
967 */
968#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
969 red = CNVT_TOHW(red, info->var.red.length);
970 green = CNVT_TOHW(green, info->var.green.length);
971 blue = CNVT_TOHW(blue, info->var.blue.length);
972 transp = CNVT_TOHW(transp, info->var.transp.length);
973#undef CNVT_TOHW
974
975 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
976 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
977 u32 v;
978
979 if (regno >= 16)
980 return -EINVAL;
981
982 v = (red << info->var.red.offset) |
983 (green << info->var.green.offset) |
984 (blue << info->var.blue.offset) |
985 (transp << info->var.transp.offset);
986
987 switch (info->var.bits_per_pixel) {
988 case 8:
989 break;
990 case 16:
f23a06f0
KH		 991 case 32:
992 ((u32*)(info->pseudo_palette))[regno] = v;
993 break;
994 }
995 return 0;
996 }
997 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
998 pm3fb_set_color(par, regno, red, green, blue);
1da177e4 999
f23a06f0 1000 return 0;
1da177e4
LT		 1001}
1002
f23a06f0
KH		 1003static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1004 struct fb_info *info)
1da177e4 1005{
f23a06f0
KH		 1006 struct pm3_par *par = info->par;
1007 const u32 xres = (var->xres + 31) & ~31;
1da177e4 1008
f23a06f0
KH		 1009 par->base = pm3fb_shift_bpp(var->bits_per_pixel,
1010 (var->yoffset * xres)
1011 + var->xoffset);
2686ba89
KH		 1012 PM3_WAIT(par, 1);
1013 PM3_WRITE_REG(par, PM3ScreenBase, par->base);
f23a06f0
KH		 1014 return 0;
1015}
1da177e4 1016
f23a06f0
KH		 1017static int pm3fb_blank(int blank_mode, struct fb_info *info)
1018{
1019 struct pm3_par *par = info->par;
1020 u32 video = par->video;
1da177e4 1021
f23a06f0
KH		 1022 /*
1023 * Oxygen VX1 - it appears that setting PM3VideoControl and
1024 * then PM3RD_SyncControl to the same SYNC settings undoes
1025 * any net change - they seem to xor together. Only set the
1026 * sync options in PM3RD_SyncControl. --rmk
1027 */
1028 video &= ~(PM3VideoControl_HSYNC_MASK |
1029 PM3VideoControl_VSYNC_MASK);
1030 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1031 PM3VideoControl_VSYNC_ACTIVE_HIGH;
1da177e4 1032
f23a06f0
KH		 1033 switch (blank_mode) {
1034 case FB_BLANK_UNBLANK:
2686ba89 1035 video |= PM3VideoControl_ENABLE;
f23a06f0 1036 break;
2686ba89
KH		 1037 case FB_BLANK_NORMAL:
1038 video &= ~(PM3VideoControl_ENABLE);
f23a06f0
KH		 1039 break;
1040 case FB_BLANK_HSYNC_SUSPEND:
2686ba89
KH		 1041 video &= ~(PM3VideoControl_HSYNC_MASK |
1042 PM3VideoControl_BLANK_ACTIVE_LOW);
f23a06f0
KH		 1043 break;
1044 case FB_BLANK_VSYNC_SUSPEND:
2686ba89
KH		 1045 video &= ~(PM3VideoControl_VSYNC_MASK |
1046 PM3VideoControl_BLANK_ACTIVE_LOW);
f23a06f0
KH		 1047 break;
1048 case FB_BLANK_POWERDOWN:
2686ba89
KH		 1049 video &= ~(PM3VideoControl_HSYNC_MASK |
1050 PM3VideoControl_VSYNC_MASK |
1051 PM3VideoControl_BLANK_ACTIVE_LOW);
f23a06f0
KH		 1052 break;
1053 default:
1054 DPRINTK("Unsupported blanking %d\n", blank_mode);
1055 return 1;
1da177e4
LT		 1056 }
1057
2686ba89
KH		 1058 PM3_WAIT(par, 1);
1059 PM3_WRITE_REG(par,PM3VideoControl, video);
f23a06f0 1060 return 0;
1da177e4
LT		 1061}
1062
f23a06f0
KH		 1063 /*
1064 * Frame buffer operations
1065 */
1da177e4 1066
f23a06f0
KH		 1067static struct fb_ops pm3fb_ops = {
1068 .owner = THIS_MODULE,
1069 .fb_check_var = pm3fb_check_var,
1070 .fb_set_par = pm3fb_set_par,
1071 .fb_setcolreg = pm3fb_setcolreg,
1072 .fb_pan_display = pm3fb_pan_display,
a58d67ce 1073 .fb_fillrect = pm3fb_fillrect,
e7f76df9
KH		 1074 .fb_copyarea = pm3fb_copyarea,
1075 .fb_imageblit = pm3fb_imageblit,
f23a06f0 1076 .fb_blank = pm3fb_blank,
a58d67ce 1077 .fb_sync = pm3fb_sync,
f23a06f0 1078};
1da177e4 1079
f23a06f0 1080/* ------------------------------------------------------------------------- */
1da177e4 1081
f23a06f0
KH		 1082 /*
1083 * Initialization
1084 */
1da177e4 1085
f23a06f0
KH		 1086/* mmio register are already mapped when this function is called */
1087/* the pm3fb_fix.smem_start is also set */
1088static unsigned long pm3fb_size_memory(struct pm3_par *par)
1da177e4 1089{
f23a06f0
KH		 1090 unsigned long memsize = 0, tempBypass, i, temp1, temp2;
1091 unsigned char __iomem *screen_mem;
1da177e4 1092
2686ba89 1093 pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
f23a06f0
KH		 1094 /* Linear frame buffer - request region and map it. */
1095 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1096 "pm3fb smem")) {
1097 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1098 return 0;
1da177e4 1099 }
f23a06f0
KH		 1100 screen_mem =
1101 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1102 if (!screen_mem) {
1103 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1104 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1105 return 0;
1da177e4
LT		 1106 }
1107
f23a06f0
KH		 1108 /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1109 /* For Appian Jeronimo 2000 board second head */
1da177e4 1110
f23a06f0 1111 tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1da177e4 1112
f23a06f0 1113 DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1da177e4 1114
2686ba89
KH		 1115 PM3_WAIT(par, 1);
1116 PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1da177e4 1117
f23a06f0
KH		 1118 /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */
1119 for (i = 0; i < 32; i++) {
1120 fb_writel(i * 0x00345678,
1121 (screen_mem + (i * 1048576)));
1122 mb();
1123 temp1 = fb_readl((screen_mem + (i * 1048576)));
1da177e4 1124
f23a06f0
KH		 1125 /* Let's check for wrapover, write will fail at 16MB boundary */
1126 if (temp1 == (i * 0x00345678))
1127 memsize = i;
1da177e4 1128 else
f23a06f0 1129 break;
1da177e4 1130 }
1da177e4 1131
f23a06f0 1132 DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1da177e4 1133
f23a06f0
KH		 1134 if (memsize + 1 == i) {
1135 for (i = 0; i < 32; i++) {
1136 /* Clear first 32MB ; 0 is 0, no need to byteswap */
2686ba89 1137 writel(0x0000000, (screen_mem + (i * 1048576)));
1da177e4 1138 }
2686ba89 1139 wmb();
1da177e4 1140
f23a06f0
KH		 1141 for (i = 32; i < 64; i++) {
1142 fb_writel(i * 0x00345678,
1143 (screen_mem + (i * 1048576)));
1144 mb();
1145 temp1 =
1146 fb_readl((screen_mem + (i * 1048576)));
1147 temp2 =
1148 fb_readl((screen_mem + ((i - 32) * 1048576)));
1149 /* different value, different RAM... */
1150 if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1151 memsize = i;
1152 else
1153 break;
1da177e4 1154 }
1da177e4 1155 }
f23a06f0 1156 DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1da177e4 1157
2686ba89
KH		 1158 PM3_WAIT(par, 1);
1159 PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1da177e4 1160
f23a06f0
KH		 1161 iounmap(screen_mem);
1162 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1163 memsize = 1048576 * (memsize + 1);
1da177e4 1164
f23a06f0 1165 DPRINTK("Returning 0x%08lx bytes\n", memsize);
1da177e4 1166
f23a06f0 1167 return memsize;
1da177e4
LT		 1168}
1169
f23a06f0
KH		 1170static int __devinit pm3fb_probe(struct pci_dev *dev,
1171 const struct pci_device_id *ent)
1da177e4 1172{
f23a06f0
KH		 1173 struct fb_info *info;
1174 struct pm3_par *par;
1175 struct device* device = &dev->dev; /* for pci drivers */
1176 int err, retval = -ENXIO;
1da177e4 1177
f23a06f0
KH		 1178 err = pci_enable_device(dev);
1179 if (err) {
1180 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1181 return err;
1da177e4 1182 }
f23a06f0
KH		 1183 /*
1184 * Dynamically allocate info and par
1185 */
1186 info = framebuffer_alloc(sizeof(struct pm3_par), device);
1da177e4 1187
f23a06f0
KH		 1188 if (!info)
1189 return -ENOMEM;
1190 par = info->par;
1da177e4 1191
f23a06f0
KH		 1192 /*
1193 * Here we set the screen_base to the virtual memory address
1194 * for the framebuffer.
1195 */
1196 pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1197 pm3fb_fix.mmio_len = PM3_REGS_SIZE;
c79ba28c
KH		 1198#if defined(__BIG_ENDIAN)
1199 pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1200 DPRINTK("Adjusting register base for big-endian.\n");
1201#endif
f23a06f0
KH		 1202
1203 /* Registers - request region and map it. */
1204 if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1205 "pm3fb regbase")) {
1206 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1207 goto err_exit_neither;
1208 }
1209 par->v_regs =
1210 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1211 if (!par->v_regs) {
1212 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1213 pm3fb_fix.id);
1214 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1215 goto err_exit_neither;
1216 }
1217
f23a06f0
KH		 1218 /* Linear frame buffer - request region and map it. */
1219 pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1220 pm3fb_fix.smem_len = pm3fb_size_memory(par);
1221 if (!pm3fb_fix.smem_len)
1222 {
1223 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1224 goto err_exit_mmio;
1da177e4 1225 }
f23a06f0
KH		 1226 if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1227 "pm3fb smem")) {
1228 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1229 goto err_exit_mmio;
1da177e4 1230 }
f23a06f0
KH		 1231 info->screen_base =
1232 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1233 if (!info->screen_base) {
1234 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1235 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1236 goto err_exit_mmio;
1da177e4 1237 }
f23a06f0 1238 info->screen_size = pm3fb_fix.smem_len;
1da177e4 1239
f23a06f0 1240 info->fbops = &pm3fb_ops;
1da177e4 1241
f23a06f0 1242 par->video = PM3_READ_REG(par, PM3VideoControl);
1da177e4 1243
f23a06f0
KH		 1244 info->fix = pm3fb_fix;
1245 info->pseudo_palette = par->palette;
a58d67ce 1246 info->flags = FBINFO_DEFAULT |
c79ba28c
KH		 1247 FBINFO_HWACCEL_XPAN |
1248 FBINFO_HWACCEL_YPAN |
e7f76df9
KH		 1249 FBINFO_HWACCEL_COPYAREA |
1250 FBINFO_HWACCEL_IMAGEBLIT |
1251 FBINFO_HWACCEL_FILLRECT;
1da177e4 1252
b0a318e2
KH		 1253 info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1254 if (!info->pixmap.addr) {
1255 retval = -ENOMEM;
1256 goto err_exit_pixmap;
1257 }
1258 info->pixmap.size = PM3_PIXMAP_SIZE;
1259 info->pixmap.buf_align = 4;
1260 info->pixmap.scan_align = 4;
1261 info->pixmap.access_align = 32;
1262 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1263
f23a06f0
KH		 1264 /*
1265 * This should give a reasonable default video mode. The following is
1266 * done when we can set a video mode.
1267 */
1268 if (!mode_option)
1269 mode_option = "640x480@60";
1da177e4 1270
f23a06f0 1271 retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1da177e4 1272
f23a06f0
KH		 1273 if (!retval || retval == 4) {
1274 retval = -EINVAL;
1275 goto err_exit_both;
1da177e4 1276 }
1da177e4 1277
f23a06f0
KH		 1278 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1279 retval = -ENOMEM;
1280 goto err_exit_both;
1da177e4 1281 }
1da177e4 1282
f23a06f0
KH		 1283 /*
1284 * For drivers that can...
1285 */
1286 pm3fb_check_var(&info->var, info);
1da177e4 1287
f23a06f0
KH		 1288 if (register_framebuffer(info) < 0) {
1289 retval = -EINVAL;
1290 goto err_exit_all;
1da177e4 1291 }
f23a06f0
KH		 1292 printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1293 info->fix.id);
2686ba89 1294 pci_set_drvdata(dev, info);
f23a06f0 1295 return 0;
1da177e4 1296
f23a06f0
KH		 1297 err_exit_all:
1298 fb_dealloc_cmap(&info->cmap);
1299 err_exit_both:
b0a318e2
KH		 1300 kfree(info->pixmap.addr);
1301 err_exit_pixmap:
f23a06f0
KH		 1302 iounmap(info->screen_base);
1303 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1304 err_exit_mmio:
1305 iounmap(par->v_regs);
1306 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1307 err_exit_neither:
1308 framebuffer_release(info);
1309 return retval;
1da177e4
LT		 1310}
1311
f23a06f0
KH		 1312 /*
1313 * Cleanup
1314 */
1315static void __devexit pm3fb_remove(struct pci_dev *dev)
1da177e4 1316{
f23a06f0 1317 struct fb_info *info = pci_get_drvdata(dev);
1da177e4 1318
f23a06f0
KH		 1319 if (info) {
1320 struct fb_fix_screeninfo *fix = &info->fix;
1321 struct pm3_par *par = info->par;
1da177e4 1322
f23a06f0
KH		 1323 unregister_framebuffer(info);
1324 fb_dealloc_cmap(&info->cmap);
1da177e4 1325
f23a06f0
KH		 1326 iounmap(info->screen_base);
1327 release_mem_region(fix->smem_start, fix->smem_len);
1328 iounmap(par->v_regs);
1329 release_mem_region(fix->mmio_start, fix->mmio_len);
1da177e4 1330
f23a06f0 1331 pci_set_drvdata(dev, NULL);
b0a318e2 1332 kfree(info->pixmap.addr);
f23a06f0 1333 framebuffer_release(info);
1da177e4 1334 }
1da177e4
LT		 1335}
1336
f23a06f0
KH		 1337static struct pci_device_id pm3fb_id_table[] = {
1338 { PCI_VENDOR_ID_3DLABS, 0x0a,
2686ba89 1339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
f23a06f0
KH		 1340 { 0, }
1341};
1da177e4 1342
f23a06f0
KH		 1343/* For PCI drivers */
1344static struct pci_driver pm3fb_driver = {
1345 .name = "pm3fb",
1346 .id_table = pm3fb_id_table,
1347 .probe = pm3fb_probe,
1348 .remove = __devexit_p(pm3fb_remove),
1349};
1da177e4 1350
f23a06f0 1351MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1da177e4 1352
b309c050 1353static int __init pm3fb_init(void)
2686ba89 1354{
f23a06f0 1355#ifndef MODULE
b309c050 1356 if (fb_get_options("pm3fb", NULL))
f23a06f0 1357 return -ENODEV;
1da177e4 1358#endif
f23a06f0 1359 return pci_register_driver(&pm3fb_driver);
1da177e4
LT		 1360}
1361
f23a06f0 1362static void __exit pm3fb_exit(void)
1da177e4 1363{
f23a06f0 1364 pci_unregister_driver(&pm3fb_driver);
1da177e4
LT		 1365}
1366
f23a06f0
KH		 1367module_init(pm3fb_init);
1368module_exit(pm3fb_exit);
1369
1370MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)