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pm2fb: 3dlabs Permedia 2V reference board added
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pm2fb.c
CommitLineData
1da177e4
LT		 1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/kernel.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
41
42#include <video/permedia2.h>
43#include <video/cvisionppc.h>
44
45#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46#error "The endianness of the target host has not been defined."
47#endif
48
49#if !defined(CONFIG_PCI)
50#error "Only generic PCI cards supported."
51#endif
52
53#undef PM2FB_MASTER_DEBUG
54#ifdef PM2FB_MASTER_DEBUG
55#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
56#else
57#define DPRINTK(a,b...)
58#endif
59
60/*
61 * Driver data
62 */
63static char *mode __devinitdata = NULL;
64
65/*
66 * The XFree GLINT driver will (I think to implement hardware cursor
67 * support on TVP4010 and similar where there is no RAMDAC - see
68 * comment in set_video) always request +ve sync regardless of what
69 * the mode requires. This screws me because I have a Sun
70 * fixed-frequency monitor which absolutely has to have -ve sync. So
71 * these flags allow the user to specify that requests for +ve sync
72 * should be silently turned in -ve sync.
73 */
c16c556e
DJ		 74static int lowhsync;
75static int lowvsync;
1da177e4
LT		 76
77/*
78 * The hardware state of the graphics card that isn't part of the
79 * screeninfo.
80 */
81struct pm2fb_par
82{
83 pm2type_t type; /* Board type */
84 u32 fb_size; /* framebuffer memory size */
85 unsigned char __iomem *v_fb; /* virtual address of frame buffer */
86 unsigned char __iomem *v_regs;/* virtual address of p_regs */
87 u32 memclock; /* memclock */
88 u32 video; /* video flags before blanking */
89 u32 mem_config; /* MemConfig reg at probe */
90 u32 mem_control; /* MemControl reg at probe */
91 u32 boot_address; /* BootAddress reg at probe */
6772a2ee 92 u32 palette[16];
1da177e4
LT		 93};
94
95/*
96 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
97 * if we don't use modedb.
98 */
99static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
100 .id = "",
101 .type = FB_TYPE_PACKED_PIXELS,
102 .visual = FB_VISUAL_PSEUDOCOLOR,
103 .xpanstep = 1,
104 .ypanstep = 1,
105 .ywrapstep = 0,
106 .accel = FB_ACCEL_NONE,
107};
108
109/*
110 * Default video mode. In case the modedb doesn't work.
111 */
112static struct fb_var_screeninfo pm2fb_var __devinitdata = {
113 /* "640x480, 8 bpp @ 60 Hz */
114 .xres = 640,
115 .yres = 480,
116 .xres_virtual = 640,
117 .yres_virtual = 480,
118 .bits_per_pixel =8,
119 .red = {0, 8, 0},
120 .blue = {0, 8, 0},
121 .green = {0, 8, 0},
122 .activate = FB_ACTIVATE_NOW,
123 .height = -1,
124 .width = -1,
125 .accel_flags = 0,
126 .pixclock = 39721,
127 .left_margin = 40,
128 .right_margin = 24,
129 .upper_margin = 32,
130 .lower_margin = 11,
131 .hsync_len = 96,
132 .vsync_len = 2,
133 .vmode = FB_VMODE_NONINTERLACED
134};
135
136/*
137 * Utility functions
138 */
139
77933d72 140static inline u32 RD32(unsigned char __iomem *base, s32 off)
1da177e4
LT		 141{
142 return fb_readl(base + off);
143}
144
77933d72 145static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
1da177e4
LT		 146{
147 fb_writel(v, base + off);
148}
149
77933d72 150static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
1da177e4
LT		 151{
152 return RD32(p->v_regs, off);
153}
154
77933d72 155static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
1da177e4
LT		 156{
157 WR32(p->v_regs, off, v);
158}
159
77933d72 160static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
1da177e4
LT		 161{
162 int index = PM2R_RD_INDEXED_DATA;
163 switch (p->type) {
164 case PM2_TYPE_PERMEDIA2:
165 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
166 break;
167 case PM2_TYPE_PERMEDIA2V:
168 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
169 index = PM2VR_RD_INDEXED_DATA;
170 break;
171 }
172 mb();
173 return pm2_RD(p, index);
174}
175
77933d72 176static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 177{
178 int index = PM2R_RD_INDEXED_DATA;
179 switch (p->type) {
180 case PM2_TYPE_PERMEDIA2:
181 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
182 break;
183 case PM2_TYPE_PERMEDIA2V:
184 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
185 index = PM2VR_RD_INDEXED_DATA;
186 break;
187 }
188 mb();
189 pm2_WR(p, index, v);
190}
191
77933d72 192static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 193{
194 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
195 mb();
196 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
197}
198
199#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
200#define WAIT_FIFO(p,a)
201#else
77933d72 202static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
1da177e4
LT		 203{
204 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
205 mb();
206}
207#endif
208
209/*
210 * partial products for the supported horizontal resolutions.
211 */
212#define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
213static const struct {
214 u16 width;
215 u16 pp;
216} pp_table[] = {
217 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
218 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
219 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
220 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
221 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
222 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
223 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
224 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
225 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
226 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
227 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
228 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
229 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
230 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
231 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
232 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
233 { 0, 0 } };
234
235static u32 partprod(u32 xres)
236{
237 int i;
238
239 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
240 ;
241 if ( pp_table[i].width == 0 )
242 DPRINTK("invalid width %u\n", xres);
243 return pp_table[i].pp;
244}
245
246static u32 to3264(u32 timing, int bpp, int is64)
247{
248 switch (bpp) {
249 case 8:
250 timing >>= 2 + is64;
251 break;
252 case 16:
253 timing >>= 1 + is64;
254 break;
255 case 24:
256 timing = (timing * 3) >> (2 + is64);
257 break;
258 case 32:
259 if (is64)
260 timing >>= 1;
261 break;
262 }
263 return timing;
264}
265
266static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
267 unsigned char* pp)
268{
269 unsigned char m;
270 unsigned char n;
271 unsigned char p;
272 u32 f;
273 s32 curr;
274 s32 delta = 100000;
275
276 *mm = *nn = *pp = 0;
277 for (n = 2; n < 15; n++) {
278 for (m = 2; m; m++) {
279 f = PM2_REFERENCE_CLOCK * m / n;
280 if (f >= 150000 && f <= 300000) {
281 for ( p = 0; p < 5; p++, f >>= 1) {
282 curr = ( clk > f ) ? clk - f : f - clk;
283 if ( curr < delta ) {
284 delta=curr;
285 *mm=m;
286 *nn=n;
287 *pp=p;
288 }
289 }
290 }
291 }
292 }
293}
294
295static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
296 unsigned char* pp)
297{
298 unsigned char m;
299 unsigned char n;
300 unsigned char p;
301 u32 f;
302 s32 delta = 1000;
303
304 *mm = *nn = *pp = 0;
305 for (n = 1; n; n++) {
306 for ( m = 1; m; m++) {
307 for ( p = 0; p < 2; p++) {
308 f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));
309 if ( clk > f - delta && clk < f + delta ) {
310 delta = ( clk > f ) ? clk - f : f - clk;
311 *mm=m;
312 *nn=n;
313 *pp=p;
314 }
315 }
316 }
317 }
318}
319
320static void clear_palette(struct pm2fb_par* p) {
321 int i=256;
322
323 WAIT_FIFO(p, 1);
324 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
325 wmb();
326 while (i--) {
327 WAIT_FIFO(p, 3);
328 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
329 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
330 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
331 }
332}
333
334static void reset_card(struct pm2fb_par* p)
335{
336 if (p->type == PM2_TYPE_PERMEDIA2V)
337 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
338 pm2_WR(p, PM2R_RESET_STATUS, 0);
339 mb();
340 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
341 ;
342 mb();
343#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
344 DPRINTK("FIFO disconnect enabled\n");
345 pm2_WR(p, PM2R_FIFO_DISCON, 1);
346 mb();
347#endif
348
349 /* Restore stashed memory config information from probe */
350 WAIT_FIFO(p, 3);
351 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
352 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
353 wmb();
354 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
355}
356
357static void reset_config(struct pm2fb_par* p)
358{
359 WAIT_FIFO(p, 52);
360 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
361 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
362 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
363 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
364 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
365 pm2_WR(p, PM2R_APERTURE_ONE, 0);
366 pm2_WR(p, PM2R_APERTURE_TWO, 0);
367 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
368 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
369 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
370 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
371 pm2_WR(p, PM2R_LB_READ_MODE, 0);
372 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
373 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
374 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
375 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
376 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
377 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
378 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
379 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
380 pm2_WR(p, PM2R_DITHER_MODE, 0);
381 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
382 pm2_WR(p, PM2R_DEPTH_MODE, 0);
383 pm2_WR(p, PM2R_STENCIL_MODE, 0);
384 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
385 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
386 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
387 pm2_WR(p, PM2R_YUV_MODE, 0);
388 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
389 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
390 pm2_WR(p, PM2R_FOG_MODE, 0);
391 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
392 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
393 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
394 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
395 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
396 switch (p->type) {
397 case PM2_TYPE_PERMEDIA2:
398 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
399 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
400 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
401 break;
402 case PM2_TYPE_PERMEDIA2V:
403 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
404 break;
405 }
406 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
407 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
408 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
409 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
410 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
411}
412
413static void set_aperture(struct pm2fb_par* p, u32 depth)
414{
415 /*
416 * The hardware is little-endian. When used in big-endian
417 * hosts, the on-chip aperture settings are used where
418 * possible to translate from host to card byte order.
419 */
420 WAIT_FIFO(p, 4);
421#ifdef __LITTLE_ENDIAN
422 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
423#else
424 switch (depth) {
425 case 24: /* RGB->BGR */
426 /*
427 * We can't use the aperture to translate host to
428 * card byte order here, so we switch to BGR mode
429 * in pm2fb_set_par().
430 */
431 case 8: /* B->B */
432 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
433 break;
434 case 16: /* HL->LH */
435 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
436 break;
437 case 32: /* RGBA->ABGR */
438 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
439 break;
440 }
441#endif
442
443 // We don't use aperture two, so this may be superflous
444 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
445}
446
447static void set_color(struct pm2fb_par* p, unsigned char regno,
448 unsigned char r, unsigned char g, unsigned char b)
449{
450 WAIT_FIFO(p, 4);
451 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
452 wmb();
453 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
454 wmb();
455 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
456 wmb();
457 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
458}
459
460static void set_memclock(struct pm2fb_par* par, u32 clk)
461{
462 int i;
463 unsigned char m, n, p;
464
465 pm2_mnp(clk, &m, &n, &p);
466 WAIT_FIFO(par, 10);
467 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
468 wmb();
469 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
470 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
471 wmb();
472 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
473 wmb();
474 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
475 rmb();
476 for (i = 256;
477 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
478 i--)
479 ;
480}
481
482static void set_pixclock(struct pm2fb_par* par, u32 clk)
483{
484 int i;
485 unsigned char m, n, p;
486
487 switch (par->type) {
488 case PM2_TYPE_PERMEDIA2:
489 pm2_mnp(clk, &m, &n, &p);
490 WAIT_FIFO(par, 8);
491 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
492 wmb();
493 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
494 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
495 wmb();
496 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
497 wmb();
498 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
499 rmb();
500 for (i = 256;
501 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
502 i--)
503 ;
504 break;
505 case PM2_TYPE_PERMEDIA2V:
506 pm2v_mnp(clk/2, &m, &n, &p);
507 WAIT_FIFO(par, 8);
508 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
509 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
510 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
511 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
512 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
513 break;
514 }
515}
516
517static void set_video(struct pm2fb_par* p, u32 video) {
518 u32 tmp;
519 u32 vsync;
520
521 vsync = video;
522
523 DPRINTK("video = 0x%x\n", video);
524
525 /*
526 * The hardware cursor needs +vsync to recognise vert retrace.
527 * We may not be using the hardware cursor, but the X Glint
528 * driver may well. So always set +hsync/+vsync and then set
529 * the RAMDAC to invert the sync if necessary.
530 */
531 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
532 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
533
534 WAIT_FIFO(p, 5);
535 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
536
537 switch (p->type) {
538 case PM2_TYPE_PERMEDIA2:
539 tmp = PM2F_RD_PALETTE_WIDTH_8;
540 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
541 tmp |= 4; /* invert hsync */
542 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
543 tmp |= 8; /* invert vsync */
544 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
545 break;
546 case PM2_TYPE_PERMEDIA2V:
547 tmp = 0;
548 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
549 tmp |= 1; /* invert hsync */
550 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
551 tmp |= 4; /* invert vsync */
552 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
553 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
554 break;
555 }
556}
557
558/*
559 *
560 */
561
562/**
563 * pm2fb_check_var - Optional function. Validates a var passed in.
564 * @var: frame buffer variable screen structure
565 * @info: frame buffer structure that represents a single frame buffer
566 *
567 * Checks to see if the hardware supports the state requested by
568 * var passed in.
569 *
570 * Returns negative errno on error, or zero on success.
571 */
572static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
573{
574 u32 lpitch;
575
576 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
577 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
578 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
579 return -EINVAL;
580 }
581
582 if (var->xres != var->xres_virtual) {
583 DPRINTK("virtual x resolution != physical x resolution not supported\n");
584 return -EINVAL;
585 }
586
587 if (var->yres > var->yres_virtual) {
588 DPRINTK("virtual y resolution < physical y resolution not possible\n");
589 return -EINVAL;
590 }
591
592 if (var->xoffset) {
593 DPRINTK("xoffset not supported\n");
594 return -EINVAL;
595 }
596
597 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
598 DPRINTK("interlace not supported\n");
599 return -EINVAL;
600 }
601
602 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
603 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
604
605 if (var->xres < 320 || var->xres > 1600) {
606 DPRINTK("width not supported: %u\n", var->xres);
607 return -EINVAL;
608 }
609
610 if (var->yres < 200 || var->yres > 1200) {
611 DPRINTK("height not supported: %u\n", var->yres);
612 return -EINVAL;
613 }
614
615 if (lpitch * var->yres_virtual > info->fix.smem_len) {
616 DPRINTK("no memory for screen (%ux%ux%u)\n",
617 var->xres, var->yres_virtual, var->bits_per_pixel);
618 return -EINVAL;
619 }
620
621 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
622 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
623 return -EINVAL;
624 }
625
626 switch(var->bits_per_pixel) {
627 case 8:
628 var->red.length = var->green.length = var->blue.length = 8;
629 break;
630 case 16:
631 var->red.offset = 11;
632 var->red.length = 5;
633 var->green.offset = 5;
634 var->green.length = 6;
635 var->blue.offset = 0;
636 var->blue.length = 5;
637 break;
638 case 32:
639 var->transp.offset = 24;
640 var->transp.length = 8;
641 var->red.offset = 16;
642 var->green.offset = 8;
643 var->blue.offset = 0;
644 var->red.length = var->green.length = var->blue.length = 8;
645 break;
646 case 24:
647#ifdef __BIG_ENDIAN
648 var->red.offset = 0;
649 var->blue.offset = 16;
650#else
651 var->red.offset = 16;
652 var->blue.offset = 0;
653#endif
654 var->green.offset = 8;
655 var->red.length = var->green.length = var->blue.length = 8;
656 break;
657 }
658 var->height = var->width = -1;
659
660 var->accel_flags = 0; /* Can't mmap if this is on */
661
662 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
663 var->xres, var->yres, var->bits_per_pixel);
664 return 0;
665}
666
667/**
668 * pm2fb_set_par - Alters the hardware state.
669 * @info: frame buffer structure that represents a single frame buffer
670 *
671 * Using the fb_var_screeninfo in fb_info we set the resolution of the
672 * this particular framebuffer.
673 */
674static int pm2fb_set_par(struct fb_info *info)
675{
6772a2ee 676 struct pm2fb_par *par = info->par;
1da177e4
LT		 677 u32 pixclock;
678 u32 width, height, depth;
679 u32 hsstart, hsend, hbend, htotal;
680 u32 vsstart, vsend, vbend, vtotal;
681 u32 stride;
682 u32 base;
683 u32 video = 0;
684 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
685 u32 txtmap = 0;
686 u32 pixsize = 0;
687 u32 clrformat = 0;
688 u32 xres;
689 int data64;
690
691 reset_card(par);
692 reset_config(par);
693 clear_palette(par);
694 if ( par->memclock )
695 set_memclock(par, par->memclock);
696
697 width = (info->var.xres_virtual + 7) & ~7;
698 height = info->var.yres_virtual;
699 depth = (info->var.bits_per_pixel + 7) & ~7;
700 depth = (depth > 32) ? 32 : depth;
701 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
702
703 xres = (info->var.xres + 31) & ~31;
704 pixclock = PICOS2KHZ(info->var.pixclock);
705 if (pixclock > PM2_MAX_PIXCLOCK) {
706 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
707 return -EINVAL;
708 }
709
710 hsstart = to3264(info->var.right_margin, depth, data64);
711 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
712 hbend = hsend + to3264(info->var.left_margin, depth, data64);
713 htotal = to3264(xres, depth, data64) + hbend - 1;
714 vsstart = (info->var.lower_margin)
715 ? info->var.lower_margin - 1
716 : 0; /* FIXME! */
717 vsend = info->var.lower_margin + info->var.vsync_len - 1;
718 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
719 vtotal = info->var.yres + vbend - 1;
720 stride = to3264(width, depth, 1);
721 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
722 if (data64)
723 video |= PM2F_DATA_64_ENABLE;
724
725 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
726 if (lowhsync) {
727 DPRINTK("ignoring +hsync, using -hsync.\n");
728 video |= PM2F_HSYNC_ACT_LOW;
729 } else
730 video |= PM2F_HSYNC_ACT_HIGH;
731 }
732 else
733 video |= PM2F_HSYNC_ACT_LOW;
734 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
735 if (lowvsync) {
736 DPRINTK("ignoring +vsync, using -vsync.\n");
737 video |= PM2F_VSYNC_ACT_LOW;
738 } else
739 video |= PM2F_VSYNC_ACT_HIGH;
740 }
741 else
742 video |= PM2F_VSYNC_ACT_LOW;
743 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
744 DPRINTK("interlaced not supported\n");
745 return -EINVAL;
746 }
747 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
748 video |= PM2F_LINE_DOUBLE;
749 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
750 video |= PM2F_VIDEO_ENABLE;
751 par->video = video;
752
753 info->fix.visual =
754 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
755 info->fix.line_length = info->var.xres * depth / 8;
756 info->cmap.len = 256;
757
758 /*
759 * Settings calculated. Now write them out.
760 */
761 if (par->type == PM2_TYPE_PERMEDIA2V) {
762 WAIT_FIFO(par, 1);
763 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
764 }
765
766 set_aperture(par, depth);
767
768 mb();
769 WAIT_FIFO(par, 19);
770 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
771 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
772 switch (depth) {
773 case 8:
774 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
775 clrformat = 0x0e;
776 break;
777 case 16:
778 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
779 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
780 txtmap = PM2F_TEXTEL_SIZE_16;
781 pixsize = 1;
782 clrformat = 0x70;
783 break;
784 case 32:
785 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
786 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
787 txtmap = PM2F_TEXTEL_SIZE_32;
788 pixsize = 2;
789 clrformat = 0x20;
790 break;
791 case 24:
792 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
793 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
794 txtmap = PM2F_TEXTEL_SIZE_24;
795 pixsize = 4;
796 clrformat = 0x20;
797 break;
798 }
799 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
800 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
801 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
802 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
803 pm2_WR(par, PM2R_H_TOTAL, htotal);
804 pm2_WR(par, PM2R_HS_START, hsstart);
805 pm2_WR(par, PM2R_HS_END, hsend);
806 pm2_WR(par, PM2R_HG_END, hbend);
807 pm2_WR(par, PM2R_HB_END, hbend);
808 pm2_WR(par, PM2R_V_TOTAL, vtotal);
809 pm2_WR(par, PM2R_VS_START, vsstart);
810 pm2_WR(par, PM2R_VS_END, vsend);
811 pm2_WR(par, PM2R_VB_END, vbend);
812 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
813 wmb();
814 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
815 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
816 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
817 wmb();
818 pm2_WR(par, PM2R_SCREEN_BASE, base);
819 wmb();
820 set_video(par, video);
821 WAIT_FIFO(par, 4);
822 switch (par->type) {
823 case PM2_TYPE_PERMEDIA2:
824 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
825 break;
826 case PM2_TYPE_PERMEDIA2V:
827 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
828 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
829 break;
830 }
831 set_pixclock(par, pixclock);
832 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
833 info->var.xres, info->var.yres, info->var.bits_per_pixel);
834 return 0;
835}
836
837/**
838 * pm2fb_setcolreg - Sets a color register.
839 * @regno: boolean, 0 copy local, 1 get_user() function
840 * @red: frame buffer colormap structure
841 * @green: The green value which can be up to 16 bits wide
842 * @blue: The blue value which can be up to 16 bits wide.
843 * @transp: If supported the alpha value which can be up to 16 bits wide.
844 * @info: frame buffer info structure
845 *
846 * Set a single color register. The values supplied have a 16 bit
847 * magnitude which needs to be scaled in this function for the hardware.
848 * Pretty much a direct lift from tdfxfb.c.
849 *
850 * Returns negative errno on error, or zero on success.
851 */
852static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
853 unsigned blue, unsigned transp,
854 struct fb_info *info)
855{
6772a2ee 856 struct pm2fb_par *par = info->par;
1da177e4
LT		 857
858 if (regno >= info->cmap.len) /* no. of hw registers */
859 return 1;
860 /*
861 * Program hardware... do anything you want with transp
862 */
863
864 /* grayscale works only partially under directcolor */
865 if (info->var.grayscale) {
866 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
867 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
868 }
869
870 /* Directcolor:
871 * var->{color}.offset contains start of bitfield
872 * var->{color}.length contains length of bitfield
873 * {hardwarespecific} contains width of DAC
874 * cmap[X] is programmed to
875 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
876 * RAMDAC[X] is programmed to (red, green, blue)
877 *
878 * Pseudocolor:
879 * uses offset = 0 && length = DAC register width.
880 * var->{color}.offset is 0
881 * var->{color}.length contains widht of DAC
882 * cmap is not used
883 * DAC[X] is programmed to (red, green, blue)
884 * Truecolor:
885 * does not use RAMDAC (usually has 3 of them).
886 * var->{color}.offset contains start of bitfield
887 * var->{color}.length contains length of bitfield
888 * cmap is programmed to
889 * (red << red.offset) | (green << green.offset) |
890 * (blue << blue.offset) | (transp << transp.offset)
891 * RAMDAC does not exist
892 */
893#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
894 switch (info->fix.visual) {
895 case FB_VISUAL_TRUECOLOR:
896 case FB_VISUAL_PSEUDOCOLOR:
897 red = CNVT_TOHW(red, info->var.red.length);
898 green = CNVT_TOHW(green, info->var.green.length);
899 blue = CNVT_TOHW(blue, info->var.blue.length);
900 transp = CNVT_TOHW(transp, info->var.transp.length);
901 break;
902 case FB_VISUAL_DIRECTCOLOR:
903 /* example here assumes 8 bit DAC. Might be different
904 * for your hardware */
905 red = CNVT_TOHW(red, 8);
906 green = CNVT_TOHW(green, 8);
907 blue = CNVT_TOHW(blue, 8);
908 /* hey, there is bug in transp handling... */
909 transp = CNVT_TOHW(transp, 8);
910 break;
911 }
912#undef CNVT_TOHW
913 /* Truecolor has hardware independent palette */
914 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
915 u32 v;
916
917 if (regno >= 16)
918 return 1;
919
920 v = (red << info->var.red.offset) |
921 (green << info->var.green.offset) |
922 (blue << info->var.blue.offset) |
923 (transp << info->var.transp.offset);
924
925 switch (info->var.bits_per_pixel) {
926 case 8:
927 break;
928 case 16:
929 case 24:
930 case 32:
6772a2ee 931 par->palette[regno] = v;
1da177e4
LT		 932 break;
933 }
934 return 0;
935 }
936 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
937 set_color(par, regno, red, green, blue);
938
939 return 0;
940}
941
942/**
943 * pm2fb_pan_display - Pans the display.
944 * @var: frame buffer variable screen structure
945 * @info: frame buffer structure that represents a single frame buffer
946 *
947 * Pan (or wrap, depending on the `vmode' field) the display using the
948 * `xoffset' and `yoffset' fields of the `var' structure.
949 * If the values don't fit, return -EINVAL.
950 *
951 * Returns negative errno on error, or zero on success.
952 *
953 */
954static int pm2fb_pan_display(struct fb_var_screeninfo *var,
955 struct fb_info *info)
956{
6772a2ee 957 struct pm2fb_par *p = info->par;
1da177e4
LT		 958 u32 base;
959 u32 depth;
960 u32 xres;
961
962 xres = (var->xres + 31) & ~31;
963 depth = (var->bits_per_pixel + 7) & ~7;
964 depth = (depth > 32) ? 32 : depth;
965 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
966 WAIT_FIFO(p, 1);
967 pm2_WR(p, PM2R_SCREEN_BASE, base);
968 return 0;
969}
970
971/**
972 * pm2fb_blank - Blanks the display.
973 * @blank_mode: the blank mode we want.
974 * @info: frame buffer structure that represents a single frame buffer
975 *
976 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
977 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
978 * video mode which doesn't support it. Implements VESA suspend
979 * and powerdown modes on hardware that supports disabling hsync/vsync:
980 * blank_mode == 2: suspend vsync
981 * blank_mode == 3: suspend hsync
982 * blank_mode == 4: powerdown
983 *
984 * Returns negative errno on error, or zero on success.
985 *
986 */
987static int pm2fb_blank(int blank_mode, struct fb_info *info)
988{
6772a2ee 989 struct pm2fb_par *par = info->par;
1da177e4
LT		 990 u32 video = par->video;
991
992 DPRINTK("blank_mode %d\n", blank_mode);
993
994 switch (blank_mode) {
995 case FB_BLANK_UNBLANK:
996 /* Screen: On */
997 video |= PM2F_VIDEO_ENABLE;
998 break;
999 case FB_BLANK_NORMAL:
1000 /* Screen: Off */
1001 video &= ~PM2F_VIDEO_ENABLE;
1002 break;
1003 case FB_BLANK_VSYNC_SUSPEND:
1004 /* VSync: Off */
1005 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1006 break;
1007 case FB_BLANK_HSYNC_SUSPEND:
1008 /* HSync: Off */
1009 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1010 break;
1011 case FB_BLANK_POWERDOWN:
1012 /* HSync: Off, VSync: Off */
1013 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1014 break;
1015 }
1016 set_video(par, video);
1017 return 0;
1018}
1019
1020/* ------------ Hardware Independent Functions ------------ */
1021
1022/*
1023 * Frame buffer operations
1024 */
1025
1026static struct fb_ops pm2fb_ops = {
1027 .owner = THIS_MODULE,
1028 .fb_check_var = pm2fb_check_var,
1029 .fb_set_par = pm2fb_set_par,
1030 .fb_setcolreg = pm2fb_setcolreg,
1031 .fb_blank = pm2fb_blank,
1032 .fb_pan_display = pm2fb_pan_display,
1033 .fb_fillrect = cfb_fillrect,
1034 .fb_copyarea = cfb_copyarea,
1035 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 1036};
1037
1038/*
1039 * PCI stuff
1040 */
1041
1042
1043/**
1044 * Device initialisation
1045 *
1046 * Initialise and allocate resource for PCI device.
1047 *
1048 * @param pdev PCI device.
1049 * @param id PCI device ID.
1050 */
1051static int __devinit pm2fb_probe(struct pci_dev *pdev,
1052 const struct pci_device_id *id)
1053{
1054 struct pm2fb_par *default_par;
1055 struct fb_info *info;
6772a2ee 1056 int err, err_retval = -ENXIO;
1da177e4
LT		 1057
1058 err = pci_enable_device(pdev);
1059 if ( err ) {
1060 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1061 return err;
1062 }
1063
6772a2ee 1064 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1da177e4
LT		 1065 if ( !info )
1066 return -ENOMEM;
6772a2ee 1067 default_par = info->par;
1da177e4
LT		 1068
1069 switch (pdev->device) {
1070 case PCI_DEVICE_ID_TI_TVP4020:
1071 strcpy(pm2fb_fix.id, "TVP4020");
1072 default_par->type = PM2_TYPE_PERMEDIA2;
1073 break;
1074 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1075 strcpy(pm2fb_fix.id, "Permedia2");
1076 default_par->type = PM2_TYPE_PERMEDIA2;
1077 break;
1078 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1079 strcpy(pm2fb_fix.id, "Permedia2v");
1080 default_par->type = PM2_TYPE_PERMEDIA2V;
1081 break;
1082 }
1083
1084 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1085 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1086
1087#if defined(__BIG_ENDIAN)
1088 /*
1089 * PM2 has a 64k register file, mapped twice in 128k. Lower
1090 * map is little-endian, upper map is big-endian.
1091 */
1092 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1093 DPRINTK("Adjusting register base for big-endian.\n");
1094#endif
1095 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1096
1097 /* Registers - request region and map it. */
1098 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1099 "pm2fb regbase") ) {
1100 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1101 goto err_exit_neither;
1102 }
1103 default_par->v_regs =
1104 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1105 if ( !default_par->v_regs ) {
1106 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1107 pm2fb_fix.id);
1108 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1109 goto err_exit_neither;
1110 }
1111
1112 /* Stash away memory register info for use when we reset the board */
1113 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1114 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1115 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1116 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1117 default_par->mem_control, default_par->boot_address,
1118 default_par->mem_config);
1119
f1c15f93 1120 default_par->memclock = CVPPC_MEMCLOCK;
9127fa28
PDS		 1121 if(default_par->mem_control == 0 &&
1122 default_par->boot_address == 0x31 &&
f1c15f93 1123 default_par->mem_config == 0x259fffff) {
9127fa28
PDS		 1124 default_par->mem_control=0;
1125 default_par->boot_address=0x20;
1126 default_par->mem_config=0xe6002021;
f1c15f93
KH		 1127 if (pdev->subsystem_vendor == 0x1048 &&
1128 pdev->subsystem_device == 0x0a31) {
1129 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1130 pdev->subsystem_vendor, pdev->subsystem_device);
1131 DPRINTK("We have not been initialized by VGA BIOS "
1132 "and are running on an Elsa Winner 2000 Office\n");
1133 DPRINTK("Initializing card timings manually...\n");
1134 default_par->memclock=70000;
1135 }
1136 if (pdev->subsystem_vendor == 0x3d3d &&
1137 pdev->subsystem_device == 0x0100) {
1138 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1139 pdev->subsystem_vendor, pdev->subsystem_device);
1140 DPRINTK("We have not been initialized by VGA BIOS "
1141 "and are running on an 3dlabs reference board\n");
1142 DPRINTK("Initializing card timings manually...\n");
1143 default_par->memclock=70000;
1144 }
9127fa28
PDS		 1145 }
1146
1da177e4
LT		 1147 /* Now work out how big lfb is going to be. */
1148 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1149 case PM2F_MEM_BANKS_1:
1150 default_par->fb_size=0x200000;
1151 break;
1152 case PM2F_MEM_BANKS_2:
1153 default_par->fb_size=0x400000;
1154 break;
1155 case PM2F_MEM_BANKS_3:
1156 default_par->fb_size=0x600000;
1157 break;
1158 case PM2F_MEM_BANKS_4:
1159 default_par->fb_size=0x800000;
1160 break;
1161 }
1da177e4
LT		 1162 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1163 pm2fb_fix.smem_len = default_par->fb_size;
1164
1165 /* Linear frame buffer - request region and map it. */
1166 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1167 "pm2fb smem") ) {
1168 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1169 goto err_exit_mmio;
1170 }
1171 info->screen_base = default_par->v_fb =
1172 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1173 if ( !default_par->v_fb ) {
1174 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1175 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1176 goto err_exit_mmio;
1177 }
1178
1179 info->fbops = &pm2fb_ops;
1180 info->fix = pm2fb_fix;
6772a2ee 1181 info->pseudo_palette = default_par->palette;
1da177e4
LT		 1182 info->flags = FBINFO_DEFAULT |
1183 FBINFO_HWACCEL_YPAN;
1184
1185 if (!mode)
1186 mode = "640x480@60";
1187
1188 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1189 if (!err || err == 4)
1190 info->var = pm2fb_var;
1191
1192 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1193 goto err_exit_all;
1194
1195 if (register_framebuffer(info) < 0)
1196 goto err_exit_both;
1197
1198 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1199 info->node, info->fix.id, default_par->fb_size / 1024);
1200
1201 /*
1202 * Our driver data
1203 */
1204 pci_set_drvdata(pdev, info);
1205
1206 return 0;
1207
1208 err_exit_all:
1209 fb_dealloc_cmap(&info->cmap);
1210 err_exit_both:
1211 iounmap(info->screen_base);
1212 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1213 err_exit_mmio:
1214 iounmap(default_par->v_regs);
1215 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1216 err_exit_neither:
1217 framebuffer_release(info);
1218 return err_retval;
1219}
1220
1221/**
1222 * Device removal.
1223 *
1224 * Release all device resources.
1225 *
1226 * @param pdev PCI device to clean up.
1227 */
1228static void __devexit pm2fb_remove(struct pci_dev *pdev)
1229{
1230 struct fb_info* info = pci_get_drvdata(pdev);
1231 struct fb_fix_screeninfo* fix = &info->fix;
1232 struct pm2fb_par *par = info->par;
1233
1234 unregister_framebuffer(info);
1235
1236 iounmap(info->screen_base);
1237 release_mem_region(fix->smem_start, fix->smem_len);
1238 iounmap(par->v_regs);
1239 release_mem_region(fix->mmio_start, fix->mmio_len);
1240
1241 pci_set_drvdata(pdev, NULL);
1242 kfree(info);
1243}
1244
1245static struct pci_device_id pm2fb_id_table[] = {
1246 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1247 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1248 0xff0000, 0 },
1249 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1250 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1251 0xff0000, 0 },
1252 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1253 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1254 0xff0000, 0 },
f1c15f93
KH		 1255 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1256 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1257 0xff00, 0 },
1da177e4
LT		 1258 { 0, }
1259};
1260
1261static struct pci_driver pm2fb_driver = {
1262 .name = "pm2fb",
1263 .id_table = pm2fb_id_table,
1264 .probe = pm2fb_probe,
1265 .remove = __devexit_p(pm2fb_remove),
1266};
1267
1268MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1269
1270
1271#ifndef MODULE
1272/**
1273 * Parse user speficied options.
1274 *
1275 * This is, comma-separated options following `video=pm2fb:'.
1276 */
1277static int __init pm2fb_setup(char *options)
1278{
1279 char* this_opt;
1280
1281 if (!options || !*options)
1282 return 0;
1283
1284 while ((this_opt = strsep(&options, ",")) != NULL) {
1285 if (!*this_opt)
1286 continue;
1287 if(!strcmp(this_opt, "lowhsync")) {
1288 lowhsync = 1;
1289 } else if(!strcmp(this_opt, "lowvsync")) {
1290 lowvsync = 1;
1291 } else {
1292 mode = this_opt;
1293 }
1294 }
1295 return 0;
1296}
1297#endif
1298
1299
1300static int __init pm2fb_init(void)
1301{
1302#ifndef MODULE
1303 char *option = NULL;
1304
1305 if (fb_get_options("pm2fb", &option))
1306 return -ENODEV;
1307 pm2fb_setup(option);
1308#endif
1309
1310 return pci_register_driver(&pm2fb_driver);
1311}
1312
1313module_init(pm2fb_init);
1314
1315#ifdef MODULE
1316/*
1317 * Cleanup
1318 */
1319
1320static void __exit pm2fb_exit(void)
1321{
1322 pci_unregister_driver(&pm2fb_driver);
1323}
1324#endif
1325
1326#ifdef MODULE
1327module_exit(pm2fb_exit);
1328
1329module_param(mode, charp, 0);
1330MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1331module_param(lowhsync, bool, 0);
1332MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1333module_param(lowvsync, bool, 0);
1334MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1335
1336MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1337MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1338MODULE_LICENSE("GPL");
1339#endif
kernel source for telekom puls (alcatel/mediatek)