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pm3fb: mtrr support and noaccel option
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pm2fb.c
CommitLineData
1da177e4
LT		 1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
2f7bb99f 27 *
1da177e4
LT		 28 */
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/kernel.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
d5383fcc
KH		 41#ifdef CONFIG_MTRR
42#include <asm/mtrr.h>
43#endif
1da177e4
LT		 44
45#include <video/permedia2.h>
46#include <video/cvisionppc.h>
47
48#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
49#error "The endianness of the target host has not been defined."
50#endif
51
52#if !defined(CONFIG_PCI)
53#error "Only generic PCI cards supported."
54#endif
55
56#undef PM2FB_MASTER_DEBUG
57#ifdef PM2FB_MASTER_DEBUG
58#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
59#else
60#define DPRINTK(a,b...)
61#endif
62
63/*
2f7bb99f 64 * Driver data
1da177e4
LT		 65 */
66static char *mode __devinitdata = NULL;
67
68/*
69 * The XFree GLINT driver will (I think to implement hardware cursor
70 * support on TVP4010 and similar where there is no RAMDAC - see
71 * comment in set_video) always request +ve sync regardless of what
72 * the mode requires. This screws me because I have a Sun
73 * fixed-frequency monitor which absolutely has to have -ve sync. So
74 * these flags allow the user to specify that requests for +ve sync
75 * should be silently turned in -ve sync.
76 */
c16c556e
DJ		 77static int lowhsync;
78static int lowvsync;
d5383fcc
KH		 79static int noaccel __devinitdata;
80/* mtrr option */
81#ifdef CONFIG_MTRR
82static int nomtrr __devinitdata;
83#endif
1da177e4
LT		 84
85/*
86 * The hardware state of the graphics card that isn't part of the
87 * screeninfo.
88 */
89struct pm2fb_par
90{
91 pm2type_t type; /* Board type */
1da177e4 92 unsigned char __iomem *v_regs;/* virtual address of p_regs */
2f7bb99f 93 u32 memclock; /* memclock */
1da177e4
LT		 94 u32 video; /* video flags before blanking */
95 u32 mem_config; /* MemConfig reg at probe */
96 u32 mem_control; /* MemControl reg at probe */
97 u32 boot_address; /* BootAddress reg at probe */
2f7bb99f 98 u32 palette[16];
d5383fcc 99 int mtrr_handle;
1da177e4
LT		 100};
101
102/*
103 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
104 * if we don't use modedb.
105 */
106static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
2f7bb99f 107 .id = "",
1da177e4
LT		 108 .type = FB_TYPE_PACKED_PIXELS,
109 .visual = FB_VISUAL_PSEUDOCOLOR,
110 .xpanstep = 1,
111 .ypanstep = 1,
2f7bb99f 112 .ywrapstep = 0,
87a7cc68 113 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
1da177e4
LT		 114};
115
116/*
117 * Default video mode. In case the modedb doesn't work.
118 */
119static struct fb_var_screeninfo pm2fb_var __devinitdata = {
120 /* "640x480, 8 bpp @ 60 Hz */
2f7bb99f
KH		 121 .xres = 640,
122 .yres = 480,
123 .xres_virtual = 640,
124 .yres_virtual = 480,
125 .bits_per_pixel = 8,
126 .red = {0, 8, 0},
127 .blue = {0, 8, 0},
128 .green = {0, 8, 0},
129 .activate = FB_ACTIVATE_NOW,
130 .height = -1,
131 .width = -1,
132 .accel_flags = 0,
133 .pixclock = 39721,
134 .left_margin = 40,
135 .right_margin = 24,
136 .upper_margin = 32,
137 .lower_margin = 11,
138 .hsync_len = 96,
139 .vsync_len = 2,
140 .vmode = FB_VMODE_NONINTERLACED
1da177e4
LT		 141};
142
143/*
144 * Utility functions
145 */
146
77933d72 147static inline u32 RD32(unsigned char __iomem *base, s32 off)
1da177e4
LT		 148{
149 return fb_readl(base + off);
150}
151
77933d72 152static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
1da177e4
LT		 153{
154 fb_writel(v, base + off);
155}
156
77933d72 157static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
1da177e4
LT		 158{
159 return RD32(p->v_regs, off);
160}
161
77933d72 162static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
1da177e4
LT		 163{
164 WR32(p->v_regs, off, v);
165}
166
77933d72 167static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
1da177e4
LT		 168{
169 int index = PM2R_RD_INDEXED_DATA;
170 switch (p->type) {
171 case PM2_TYPE_PERMEDIA2:
172 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
173 break;
174 case PM2_TYPE_PERMEDIA2V:
175 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
176 index = PM2VR_RD_INDEXED_DATA;
177 break;
2f7bb99f 178 }
1da177e4
LT		 179 mb();
180 return pm2_RD(p, index);
181}
182
77933d72 183static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 184{
185 int index = PM2R_RD_INDEXED_DATA;
186 switch (p->type) {
187 case PM2_TYPE_PERMEDIA2:
188 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
189 break;
190 case PM2_TYPE_PERMEDIA2V:
191 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
192 index = PM2VR_RD_INDEXED_DATA;
193 break;
2f7bb99f 194 }
11d1a62c 195 wmb();
1da177e4 196 pm2_WR(p, index, v);
11d1a62c 197 wmb();
1da177e4
LT		 198}
199
77933d72 200static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 201{
202 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
11d1a62c 203 wmb();
1da177e4 204 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
11d1a62c 205 wmb();
1da177e4
LT		 206}
207
208#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
2f7bb99f 209#define WAIT_FIFO(p, a)
1da177e4 210#else
77933d72 211static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
1da177e4
LT		 212{
213 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
214 mb();
215}
216#endif
217
218/*
219 * partial products for the supported horizontal resolutions.
220 */
2f7bb99f 221#define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
1da177e4
LT		 222static const struct {
223 u16 width;
224 u16 pp;
225} pp_table[] = {
226 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
227 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
228 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
229 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
230 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
231 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
232 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
233 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
234 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
235 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
236 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
237 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
238 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
239 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
240 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
241 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
242 { 0, 0 } };
243
244static u32 partprod(u32 xres)
245{
246 int i;
247
248 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
249 ;
250 if ( pp_table[i].width == 0 )
251 DPRINTK("invalid width %u\n", xres);
252 return pp_table[i].pp;
253}
254
255static u32 to3264(u32 timing, int bpp, int is64)
256{
257 switch (bpp) {
258 case 8:
259 timing >>= 2 + is64;
260 break;
261 case 16:
262 timing >>= 1 + is64;
263 break;
264 case 24:
265 timing = (timing * 3) >> (2 + is64);
266 break;
267 case 32:
268 if (is64)
269 timing >>= 1;
270 break;
271 }
272 return timing;
273}
274
275static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
276 unsigned char* pp)
277{
278 unsigned char m;
279 unsigned char n;
280 unsigned char p;
281 u32 f;
282 s32 curr;
283 s32 delta = 100000;
284
285 *mm = *nn = *pp = 0;
286 for (n = 2; n < 15; n++) {
287 for (m = 2; m; m++) {
288 f = PM2_REFERENCE_CLOCK * m / n;
289 if (f >= 150000 && f <= 300000) {
290 for ( p = 0; p < 5; p++, f >>= 1) {
291 curr = ( clk > f ) ? clk - f : f - clk;
292 if ( curr < delta ) {
293 delta=curr;
294 *mm=m;
295 *nn=n;
296 *pp=p;
297 }
298 }
299 }
300 }
301 }
302}
303
304static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
305 unsigned char* pp)
306{
307 unsigned char m;
308 unsigned char n;
309 unsigned char p;
310 u32 f;
311 s32 delta = 1000;
312
313 *mm = *nn = *pp = 0;
d4a96b53
KH		 314 for ( m = 1; m < 128; m++) {
315 for (n = 2 * m + 1; n; n++) {
1da177e4 316 for ( p = 0; p < 2; p++) {
d4a96b53 317 f = ( PM2_REFERENCE_CLOCK >> ( p + 1 )) * n / m;
1da177e4
LT		 318 if ( clk > f - delta && clk < f + delta ) {
319 delta = ( clk > f ) ? clk - f : f - clk;
320 *mm=m;
321 *nn=n;
322 *pp=p;
323 }
324 }
325 }
326 }
327}
328
329static void clear_palette(struct pm2fb_par* p) {
330 int i=256;
331
332 WAIT_FIFO(p, 1);
333 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
334 wmb();
335 while (i--) {
336 WAIT_FIFO(p, 3);
337 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
338 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
339 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
340 }
341}
342
343static void reset_card(struct pm2fb_par* p)
344{
345 if (p->type == PM2_TYPE_PERMEDIA2V)
346 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
347 pm2_WR(p, PM2R_RESET_STATUS, 0);
348 mb();
349 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
350 ;
351 mb();
352#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
353 DPRINTK("FIFO disconnect enabled\n");
354 pm2_WR(p, PM2R_FIFO_DISCON, 1);
355 mb();
356#endif
357
358 /* Restore stashed memory config information from probe */
359 WAIT_FIFO(p, 3);
360 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
361 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
362 wmb();
363 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
364}
365
366static void reset_config(struct pm2fb_par* p)
367{
368 WAIT_FIFO(p, 52);
2f7bb99f 369 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
1da177e4
LT		 370 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
371 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
372 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
373 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
374 pm2_WR(p, PM2R_APERTURE_ONE, 0);
375 pm2_WR(p, PM2R_APERTURE_TWO, 0);
376 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
377 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
378 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
2f7bb99f 379 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
1da177e4
LT		 380 pm2_WR(p, PM2R_LB_READ_MODE, 0);
381 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
382 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
383 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
384 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
385 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
386 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
387 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
388 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
389 pm2_WR(p, PM2R_DITHER_MODE, 0);
390 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
391 pm2_WR(p, PM2R_DEPTH_MODE, 0);
392 pm2_WR(p, PM2R_STENCIL_MODE, 0);
393 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
394 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
395 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
396 pm2_WR(p, PM2R_YUV_MODE, 0);
397 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
398 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
399 pm2_WR(p, PM2R_FOG_MODE, 0);
400 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
401 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
402 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
403 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
404 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
405 switch (p->type) {
406 case PM2_TYPE_PERMEDIA2:
407 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
408 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
409 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
410 break;
411 case PM2_TYPE_PERMEDIA2V:
412 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
413 break;
414 }
415 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
416 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
417 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
418 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
419 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
420}
421
422static void set_aperture(struct pm2fb_par* p, u32 depth)
423{
424 /*
425 * The hardware is little-endian. When used in big-endian
426 * hosts, the on-chip aperture settings are used where
427 * possible to translate from host to card byte order.
428 */
429 WAIT_FIFO(p, 4);
430#ifdef __LITTLE_ENDIAN
431 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
432#else
433 switch (depth) {
434 case 24: /* RGB->BGR */
435 /*
436 * We can't use the aperture to translate host to
437 * card byte order here, so we switch to BGR mode
438 * in pm2fb_set_par().
439 */
440 case 8: /* B->B */
441 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
442 break;
443 case 16: /* HL->LH */
444 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
445 break;
446 case 32: /* RGBA->ABGR */
447 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
448 break;
449 }
450#endif
451
452 // We don't use aperture two, so this may be superflous
453 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
454}
455
456static void set_color(struct pm2fb_par* p, unsigned char regno,
457 unsigned char r, unsigned char g, unsigned char b)
458{
459 WAIT_FIFO(p, 4);
460 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
461 wmb();
462 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
463 wmb();
464 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
465 wmb();
466 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
467}
468
469static void set_memclock(struct pm2fb_par* par, u32 clk)
470{
471 int i;
472 unsigned char m, n, p;
473
e5d809d7
KH		 474 switch (par->type) {
475 case PM2_TYPE_PERMEDIA2V:
476 pm2v_mnp(clk/2, &m, &n, &p);
477 WAIT_FIFO(par, 8);
478 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
479 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
e5d809d7
KH		 480 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
481 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
482 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
e5d809d7
KH		 483 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
484 rmb();
485 for (i = 256;
486 i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2);
487 i--)
488 ;
489 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
490 break;
491 case PM2_TYPE_PERMEDIA2:
492 pm2_mnp(clk, &m, &n, &p);
493 WAIT_FIFO(par, 10);
494 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
e5d809d7
KH		 495 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
496 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
e5d809d7 497 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
e5d809d7
KH		 498 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
499 rmb();
500 for (i = 256;
501 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
502 i--)
503 ;
504 break;
505 }
1da177e4
LT		 506}
507
508static void set_pixclock(struct pm2fb_par* par, u32 clk)
509{
510 int i;
511 unsigned char m, n, p;
512
513 switch (par->type) {
514 case PM2_TYPE_PERMEDIA2:
515 pm2_mnp(clk, &m, &n, &p);
516 WAIT_FIFO(par, 8);
517 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
1da177e4
LT		 518 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
519 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
1da177e4 520 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
1da177e4
LT		 521 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
522 rmb();
523 for (i = 256;
524 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
525 i--)
526 ;
527 break;
528 case PM2_TYPE_PERMEDIA2V:
529 pm2v_mnp(clk/2, &m, &n, &p);
530 WAIT_FIFO(par, 8);
531 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
532 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
533 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
534 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
535 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
536 break;
537 }
538}
539
540static void set_video(struct pm2fb_par* p, u32 video) {
541 u32 tmp;
542 u32 vsync;
543
544 vsync = video;
545
546 DPRINTK("video = 0x%x\n", video);
2f7bb99f 547
1da177e4
LT		 548 /*
549 * The hardware cursor needs +vsync to recognise vert retrace.
550 * We may not be using the hardware cursor, but the X Glint
551 * driver may well. So always set +hsync/+vsync and then set
552 * the RAMDAC to invert the sync if necessary.
553 */
554 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
555 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
556
557 WAIT_FIFO(p, 5);
558 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
559
560 switch (p->type) {
561 case PM2_TYPE_PERMEDIA2:
562 tmp = PM2F_RD_PALETTE_WIDTH_8;
563 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
564 tmp |= 4; /* invert hsync */
565 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
566 tmp |= 8; /* invert vsync */
567 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
568 break;
569 case PM2_TYPE_PERMEDIA2V:
570 tmp = 0;
571 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
572 tmp |= 1; /* invert hsync */
573 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
574 tmp |= 4; /* invert vsync */
575 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
576 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
577 break;
578 }
579}
580
581/*
582 *
583 */
584
585/**
2f7bb99f
KH		 586 * pm2fb_check_var - Optional function. Validates a var passed in.
587 * @var: frame buffer variable screen structure
588 * @info: frame buffer structure that represents a single frame buffer
1da177e4
LT		 589 *
590 * Checks to see if the hardware supports the state requested by
591 * var passed in.
592 *
593 * Returns negative errno on error, or zero on success.
594 */
595static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
596{
597 u32 lpitch;
598
599 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
600 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
601 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
602 return -EINVAL;
603 }
604
605 if (var->xres != var->xres_virtual) {
606 DPRINTK("virtual x resolution != physical x resolution not supported\n");
607 return -EINVAL;
608 }
609
610 if (var->yres > var->yres_virtual) {
611 DPRINTK("virtual y resolution < physical y resolution not possible\n");
612 return -EINVAL;
613 }
614
615 if (var->xoffset) {
616 DPRINTK("xoffset not supported\n");
617 return -EINVAL;
618 }
619
620 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
621 DPRINTK("interlace not supported\n");
622 return -EINVAL;
623 }
624
625 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
626 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
2f7bb99f 627
1da177e4
LT		 628 if (var->xres < 320 || var->xres > 1600) {
629 DPRINTK("width not supported: %u\n", var->xres);
630 return -EINVAL;
631 }
2f7bb99f 632
1da177e4
LT		 633 if (var->yres < 200 || var->yres > 1200) {
634 DPRINTK("height not supported: %u\n", var->yres);
635 return -EINVAL;
636 }
2f7bb99f 637
1da177e4
LT		 638 if (lpitch * var->yres_virtual > info->fix.smem_len) {
639 DPRINTK("no memory for screen (%ux%ux%u)\n",
640 var->xres, var->yres_virtual, var->bits_per_pixel);
641 return -EINVAL;
642 }
2f7bb99f 643
1da177e4
LT		 644 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
645 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
646 return -EINVAL;
647 }
648
76c7d3ff 649 var->transp.offset = 0;
650 var->transp.length = 0;
1da177e4
LT		 651 switch(var->bits_per_pixel) {
652 case 8:
653 var->red.length = var->green.length = var->blue.length = 8;
654 break;
655 case 16:
656 var->red.offset = 11;
657 var->red.length = 5;
658 var->green.offset = 5;
659 var->green.length = 6;
660 var->blue.offset = 0;
661 var->blue.length = 5;
662 break;
663 case 32:
664 var->transp.offset = 24;
665 var->transp.length = 8;
666 var->red.offset = 16;
667 var->green.offset = 8;
668 var->blue.offset = 0;
669 var->red.length = var->green.length = var->blue.length = 8;
670 break;
671 case 24:
672#ifdef __BIG_ENDIAN
673 var->red.offset = 0;
674 var->blue.offset = 16;
675#else
676 var->red.offset = 16;
677 var->blue.offset = 0;
678#endif
679 var->green.offset = 8;
680 var->red.length = var->green.length = var->blue.length = 8;
681 break;
682 }
683 var->height = var->width = -1;
2f7bb99f 684
1da177e4 685 var->accel_flags = 0; /* Can't mmap if this is on */
2f7bb99f 686
1da177e4
LT		 687 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
688 var->xres, var->yres, var->bits_per_pixel);
689 return 0;
690}
691
692/**
2f7bb99f
KH		 693 * pm2fb_set_par - Alters the hardware state.
694 * @info: frame buffer structure that represents a single frame buffer
1da177e4
LT		 695 *
696 * Using the fb_var_screeninfo in fb_info we set the resolution of the
697 * this particular framebuffer.
698 */
699static int pm2fb_set_par(struct fb_info *info)
700{
6772a2ee 701 struct pm2fb_par *par = info->par;
1da177e4
LT		 702 u32 pixclock;
703 u32 width, height, depth;
704 u32 hsstart, hsend, hbend, htotal;
705 u32 vsstart, vsend, vbend, vtotal;
706 u32 stride;
707 u32 base;
708 u32 video = 0;
709 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
710 u32 txtmap = 0;
711 u32 pixsize = 0;
712 u32 clrformat = 0;
713 u32 xres;
714 int data64;
715
716 reset_card(par);
717 reset_config(par);
718 clear_palette(par);
719 if ( par->memclock )
720 set_memclock(par, par->memclock);
2f7bb99f 721
1da177e4
LT		 722 width = (info->var.xres_virtual + 7) & ~7;
723 height = info->var.yres_virtual;
724 depth = (info->var.bits_per_pixel + 7) & ~7;
725 depth = (depth > 32) ? 32 : depth;
726 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
727
728 xres = (info->var.xres + 31) & ~31;
729 pixclock = PICOS2KHZ(info->var.pixclock);
730 if (pixclock > PM2_MAX_PIXCLOCK) {
731 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
732 return -EINVAL;
733 }
2f7bb99f 734
1da177e4
LT		 735 hsstart = to3264(info->var.right_margin, depth, data64);
736 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
737 hbend = hsend + to3264(info->var.left_margin, depth, data64);
738 htotal = to3264(xres, depth, data64) + hbend - 1;
739 vsstart = (info->var.lower_margin)
740 ? info->var.lower_margin - 1
741 : 0; /* FIXME! */
742 vsend = info->var.lower_margin + info->var.vsync_len - 1;
743 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
744 vtotal = info->var.yres + vbend - 1;
745 stride = to3264(width, depth, 1);
746 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
747 if (data64)
748 video |= PM2F_DATA_64_ENABLE;
2f7bb99f 749
1da177e4
LT		 750 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
751 if (lowhsync) {
752 DPRINTK("ignoring +hsync, using -hsync.\n");
753 video |= PM2F_HSYNC_ACT_LOW;
754 } else
755 video |= PM2F_HSYNC_ACT_HIGH;
756 }
757 else
758 video |= PM2F_HSYNC_ACT_LOW;
759 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
760 if (lowvsync) {
761 DPRINTK("ignoring +vsync, using -vsync.\n");
762 video |= PM2F_VSYNC_ACT_LOW;
763 } else
764 video |= PM2F_VSYNC_ACT_HIGH;
765 }
766 else
767 video |= PM2F_VSYNC_ACT_LOW;
768 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
769 DPRINTK("interlaced not supported\n");
770 return -EINVAL;
771 }
772 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
773 video |= PM2F_LINE_DOUBLE;
774 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
775 video |= PM2F_VIDEO_ENABLE;
776 par->video = video;
777
778 info->fix.visual =
779 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
780 info->fix.line_length = info->var.xres * depth / 8;
781 info->cmap.len = 256;
782
783 /*
784 * Settings calculated. Now write them out.
785 */
786 if (par->type == PM2_TYPE_PERMEDIA2V) {
787 WAIT_FIFO(par, 1);
788 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
789 }
2f7bb99f 790
1da177e4 791 set_aperture(par, depth);
2f7bb99f 792
1da177e4
LT		 793 mb();
794 WAIT_FIFO(par, 19);
795 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
796 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
797 switch (depth) {
798 case 8:
799 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
800 clrformat = 0x0e;
801 break;
802 case 16:
803 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
804 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
805 txtmap = PM2F_TEXTEL_SIZE_16;
806 pixsize = 1;
807 clrformat = 0x70;
808 break;
809 case 32:
810 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
811 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
812 txtmap = PM2F_TEXTEL_SIZE_32;
813 pixsize = 2;
814 clrformat = 0x20;
815 break;
816 case 24:
817 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
818 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
819 txtmap = PM2F_TEXTEL_SIZE_24;
820 pixsize = 4;
821 clrformat = 0x20;
822 break;
823 }
824 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
825 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
826 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
827 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
828 pm2_WR(par, PM2R_H_TOTAL, htotal);
829 pm2_WR(par, PM2R_HS_START, hsstart);
830 pm2_WR(par, PM2R_HS_END, hsend);
831 pm2_WR(par, PM2R_HG_END, hbend);
832 pm2_WR(par, PM2R_HB_END, hbend);
833 pm2_WR(par, PM2R_V_TOTAL, vtotal);
834 pm2_WR(par, PM2R_VS_START, vsstart);
835 pm2_WR(par, PM2R_VS_END, vsend);
836 pm2_WR(par, PM2R_VB_END, vbend);
837 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
838 wmb();
839 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
840 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
841 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
842 wmb();
843 pm2_WR(par, PM2R_SCREEN_BASE, base);
844 wmb();
845 set_video(par, video);
846 WAIT_FIFO(par, 4);
847 switch (par->type) {
848 case PM2_TYPE_PERMEDIA2:
849 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
850 break;
851 case PM2_TYPE_PERMEDIA2V:
852 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
853 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
854 break;
855 }
856 set_pixclock(par, pixclock);
857 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
858 info->var.xres, info->var.yres, info->var.bits_per_pixel);
2f7bb99f 859 return 0;
1da177e4
LT		 860}
861
862/**
2f7bb99f
KH		 863 * pm2fb_setcolreg - Sets a color register.
864 * @regno: boolean, 0 copy local, 1 get_user() function
865 * @red: frame buffer colormap structure
866 * @green: The green value which can be up to 16 bits wide
1da177e4 867 * @blue: The blue value which can be up to 16 bits wide.
2f7bb99f
KH		 868 * @transp: If supported the alpha value which can be up to 16 bits wide.
869 * @info: frame buffer info structure
870 *
871 * Set a single color register. The values supplied have a 16 bit
872 * magnitude which needs to be scaled in this function for the hardware.
1da177e4 873 * Pretty much a direct lift from tdfxfb.c.
2f7bb99f 874 *
1da177e4
LT		 875 * Returns negative errno on error, or zero on success.
876 */
877static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
878 unsigned blue, unsigned transp,
879 struct fb_info *info)
880{
6772a2ee 881 struct pm2fb_par *par = info->par;
1da177e4
LT		 882
883 if (regno >= info->cmap.len) /* no. of hw registers */
884 return 1;
885 /*
886 * Program hardware... do anything you want with transp
887 */
888
889 /* grayscale works only partially under directcolor */
890 if (info->var.grayscale) {
891 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
892 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
893 }
894
895 /* Directcolor:
896 * var->{color}.offset contains start of bitfield
897 * var->{color}.length contains length of bitfield
898 * {hardwarespecific} contains width of DAC
899 * cmap[X] is programmed to
900 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
901 * RAMDAC[X] is programmed to (red, green, blue)
902 *
903 * Pseudocolor:
904 * uses offset = 0 && length = DAC register width.
905 * var->{color}.offset is 0
906 * var->{color}.length contains widht of DAC
907 * cmap is not used
908 * DAC[X] is programmed to (red, green, blue)
909 * Truecolor:
910 * does not use RAMDAC (usually has 3 of them).
911 * var->{color}.offset contains start of bitfield
912 * var->{color}.length contains length of bitfield
913 * cmap is programmed to
914 * (red << red.offset) | (green << green.offset) |
915 * (blue << blue.offset) | (transp << transp.offset)
916 * RAMDAC does not exist
917 */
2f7bb99f 918#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
1da177e4
LT		 919 switch (info->fix.visual) {
920 case FB_VISUAL_TRUECOLOR:
921 case FB_VISUAL_PSEUDOCOLOR:
922 red = CNVT_TOHW(red, info->var.red.length);
923 green = CNVT_TOHW(green, info->var.green.length);
924 blue = CNVT_TOHW(blue, info->var.blue.length);
925 transp = CNVT_TOHW(transp, info->var.transp.length);
926 break;
927 case FB_VISUAL_DIRECTCOLOR:
2f7bb99f
KH		 928 /* example here assumes 8 bit DAC. Might be different
929 * for your hardware */
930 red = CNVT_TOHW(red, 8);
1da177e4
LT		 931 green = CNVT_TOHW(green, 8);
932 blue = CNVT_TOHW(blue, 8);
933 /* hey, there is bug in transp handling... */
934 transp = CNVT_TOHW(transp, 8);
935 break;
936 }
937#undef CNVT_TOHW
938 /* Truecolor has hardware independent palette */
939 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
940 u32 v;
941
942 if (regno >= 16)
943 return 1;
944
945 v = (red << info->var.red.offset) |
946 (green << info->var.green.offset) |
947 (blue << info->var.blue.offset) |
948 (transp << info->var.transp.offset);
949
950 switch (info->var.bits_per_pixel) {
951 case 8:
2f7bb99f
KH		 952 break;
953 case 16:
1da177e4 954 case 24:
2f7bb99f
KH		 955 case 32:
956 par->palette[regno] = v;
1da177e4
LT		 957 break;
958 }
959 return 0;
960 }
961 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
962 set_color(par, regno, red, green, blue);
963
964 return 0;
965}
966
967/**
2f7bb99f
KH		 968 * pm2fb_pan_display - Pans the display.
969 * @var: frame buffer variable screen structure
970 * @info: frame buffer structure that represents a single frame buffer
1da177e4
LT		 971 *
972 * Pan (or wrap, depending on the `vmode' field) the display using the
2f7bb99f
KH		 973 * `xoffset' and `yoffset' fields of the `var' structure.
974 * If the values don't fit, return -EINVAL.
1da177e4 975 *
2f7bb99f 976 * Returns negative errno on error, or zero on success.
1da177e4
LT		 977 *
978 */
979static int pm2fb_pan_display(struct fb_var_screeninfo *var,
980 struct fb_info *info)
981{
6772a2ee 982 struct pm2fb_par *p = info->par;
1da177e4
LT		 983 u32 base;
984 u32 depth;
985 u32 xres;
986
987 xres = (var->xres + 31) & ~31;
988 depth = (var->bits_per_pixel + 7) & ~7;
989 depth = (depth > 32) ? 32 : depth;
990 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
991 WAIT_FIFO(p, 1);
2f7bb99f 992 pm2_WR(p, PM2R_SCREEN_BASE, base);
1da177e4
LT		 993 return 0;
994}
995
996/**
2f7bb99f
KH		 997 * pm2fb_blank - Blanks the display.
998 * @blank_mode: the blank mode we want.
999 * @info: frame buffer structure that represents a single frame buffer
1da177e4 1000 *
2f7bb99f
KH		 1001 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
1002 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1003 * video mode which doesn't support it. Implements VESA suspend
1004 * and powerdown modes on hardware that supports disabling hsync/vsync:
1005 * blank_mode == 2: suspend vsync
1006 * blank_mode == 3: suspend hsync
1007 * blank_mode == 4: powerdown
1da177e4 1008 *
2f7bb99f 1009 * Returns negative errno on error, or zero on success.
1da177e4
LT		 1010 *
1011 */
1012static int pm2fb_blank(int blank_mode, struct fb_info *info)
1013{
6772a2ee 1014 struct pm2fb_par *par = info->par;
1da177e4
LT		 1015 u32 video = par->video;
1016
1017 DPRINTK("blank_mode %d\n", blank_mode);
1018
1019 switch (blank_mode) {
1020 case FB_BLANK_UNBLANK:
1021 /* Screen: On */
1022 video |= PM2F_VIDEO_ENABLE;
1023 break;
1024 case FB_BLANK_NORMAL:
1025 /* Screen: Off */
1026 video &= ~PM2F_VIDEO_ENABLE;
1027 break;
1028 case FB_BLANK_VSYNC_SUSPEND:
1029 /* VSync: Off */
1030 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1031 break;
1032 case FB_BLANK_HSYNC_SUSPEND:
1033 /* HSync: Off */
1034 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1035 break;
1036 case FB_BLANK_POWERDOWN:
1037 /* HSync: Off, VSync: Off */
1038 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1039 break;
1040 }
1041 set_video(par, video);
1042 return 0;
1043}
1044
03b9ae4b
AD		 1045static int pm2fb_sync(struct fb_info *info)
1046{
1047 struct pm2fb_par *par = info->par;
1048
1049 WAIT_FIFO(par, 1);
1050 pm2_WR(par, PM2R_SYNC, 0);
1051 mb();
1052 do {
1053 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1054 udelay(10);
1055 rmb();
1056 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1057
1058 return 0;
1059}
1060
87a7cc68
KH		 1061/*
1062 * block operation. copy=0: rectangle fill, copy=1: rectangle copy.
1063 */
03b9ae4b 1064static void pm2fb_block_op(struct fb_info* info, int copy,
87a7cc68
KH		 1065 s32 xsrc, s32 ysrc,
1066 s32 x, s32 y, s32 w, s32 h,
1067 u32 color) {
03b9ae4b 1068 struct pm2fb_par *par = info->par;
87a7cc68
KH		 1069
1070 if (!w || !h)
1071 return;
11d1a62c 1072 WAIT_FIFO(par, 5);
87a7cc68
KH		 1073 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1074 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
87a7cc68
KH		 1075 if (copy)
1076 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1077 ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff));
1078 else
1079 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1080 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (y << 16) | x);
1081 pm2_WR(par, PM2R_RECTANGLE_SIZE, (h << 16) | w);
1082 wmb();
2f7bb99f 1083 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
87a7cc68
KH		 1084 (x<xsrc ? PM2F_INCREASE_X : 0) |
1085 (y<ysrc ? PM2F_INCREASE_Y : 0) |
1086 (copy ? 0 : PM2F_RENDER_FASTFILL));
87a7cc68
KH		 1087}
1088
1089static void pm2fb_fillrect (struct fb_info *info,
1090 const struct fb_fillrect *region)
1091{
87a7cc68
KH		 1092 struct fb_fillrect modded;
1093 int vxres, vyres;
1094 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1095 ((u32*)info->pseudo_palette)[region->color] : region->color;
1096
1097 if (info->state != FBINFO_STATE_RUNNING)
1098 return;
1099 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1100 region->rop != ROP_COPY ) {
1101 cfb_fillrect(info, region);
1102 return;
1103 }
1104
1105 vxres = info->var.xres_virtual;
1106 vyres = info->var.yres_virtual;
1107
1108 memcpy(&modded, region, sizeof(struct fb_fillrect));
1109
1110 if(!modded.width || !modded.height ||
1111 modded.dx >= vxres || modded.dy >= vyres)
1112 return;
1113
1114 if(modded.dx + modded.width > vxres)
1115 modded.width = vxres - modded.dx;
1116 if(modded.dy + modded.height > vyres)
1117 modded.height = vyres - modded.dy;
1118
1119 if(info->var.bits_per_pixel == 8)
1120 color |= color << 8;
1121 if(info->var.bits_per_pixel <= 16)
1122 color |= color << 16;
1123
1124 if(info->var.bits_per_pixel != 24)
03b9ae4b 1125 pm2fb_block_op(info, 0, 0, 0,
87a7cc68
KH		 1126 modded.dx, modded.dy,
1127 modded.width, modded.height, color);
1128 else
1129 cfb_fillrect(info, region);
1130}
1131
1132static void pm2fb_copyarea(struct fb_info *info,
1133 const struct fb_copyarea *area)
1134{
87a7cc68
KH		 1135 struct fb_copyarea modded;
1136 u32 vxres, vyres;
1137
1138 if (info->state != FBINFO_STATE_RUNNING)
1139 return;
1140 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1141 cfb_copyarea(info, area);
1142 return;
1143 }
1144
1145 memcpy(&modded, area, sizeof(struct fb_copyarea));
1146
1147 vxres = info->var.xres_virtual;
1148 vyres = info->var.yres_virtual;
1149
1150 if(!modded.width || !modded.height ||
1151 modded.sx >= vxres || modded.sy >= vyres ||
1152 modded.dx >= vxres || modded.dy >= vyres)
1153 return;
1154
1155 if(modded.sx + modded.width > vxres)
1156 modded.width = vxres - modded.sx;
1157 if(modded.dx + modded.width > vxres)
1158 modded.width = vxres - modded.dx;
1159 if(modded.sy + modded.height > vyres)
1160 modded.height = vyres - modded.sy;
1161 if(modded.dy + modded.height > vyres)
1162 modded.height = vyres - modded.dy;
1163
03b9ae4b 1164 pm2fb_block_op(info, 1, modded.sx, modded.sy,
87a7cc68
KH		 1165 modded.dx, modded.dy,
1166 modded.width, modded.height, 0);
1167}
1168
1da177e4
LT		 1169/* ------------ Hardware Independent Functions ------------ */
1170
1171/*
1172 * Frame buffer operations
1173 */
1174
1175static struct fb_ops pm2fb_ops = {
1176 .owner = THIS_MODULE,
1177 .fb_check_var = pm2fb_check_var,
1178 .fb_set_par = pm2fb_set_par,
1179 .fb_setcolreg = pm2fb_setcolreg,
1180 .fb_blank = pm2fb_blank,
1181 .fb_pan_display = pm2fb_pan_display,
87a7cc68
KH		 1182 .fb_fillrect = pm2fb_fillrect,
1183 .fb_copyarea = pm2fb_copyarea,
1da177e4 1184 .fb_imageblit = cfb_imageblit,
03b9ae4b 1185 .fb_sync = pm2fb_sync,
1da177e4
LT		 1186};
1187
1188/*
1189 * PCI stuff
1190 */
1191
1192
1193/**
1194 * Device initialisation
1195 *
1196 * Initialise and allocate resource for PCI device.
1197 *
1198 * @param pdev PCI device.
1199 * @param id PCI device ID.
1200 */
1201static int __devinit pm2fb_probe(struct pci_dev *pdev,
1202 const struct pci_device_id *id)
1203{
1204 struct pm2fb_par *default_par;
1205 struct fb_info *info;
6772a2ee 1206 int err, err_retval = -ENXIO;
1da177e4
LT		 1207
1208 err = pci_enable_device(pdev);
1209 if ( err ) {
1210 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1211 return err;
1212 }
1213
6772a2ee 1214 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1da177e4
LT		 1215 if ( !info )
1216 return -ENOMEM;
6772a2ee 1217 default_par = info->par;
1da177e4
LT		 1218
1219 switch (pdev->device) {
1220 case PCI_DEVICE_ID_TI_TVP4020:
1221 strcpy(pm2fb_fix.id, "TVP4020");
1222 default_par->type = PM2_TYPE_PERMEDIA2;
1223 break;
1224 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1225 strcpy(pm2fb_fix.id, "Permedia2");
1226 default_par->type = PM2_TYPE_PERMEDIA2;
1227 break;
1228 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1229 strcpy(pm2fb_fix.id, "Permedia2v");
1230 default_par->type = PM2_TYPE_PERMEDIA2V;
1231 break;
1232 }
1233
1234 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1235 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1236
1237#if defined(__BIG_ENDIAN)
1238 /*
1239 * PM2 has a 64k register file, mapped twice in 128k. Lower
1240 * map is little-endian, upper map is big-endian.
1241 */
1242 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1243 DPRINTK("Adjusting register base for big-endian.\n");
1244#endif
1245 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
2f7bb99f 1246
1da177e4
LT		 1247 /* Registers - request region and map it. */
1248 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1249 "pm2fb regbase") ) {
1250 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1251 goto err_exit_neither;
1252 }
1253 default_par->v_regs =
1254 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1255 if ( !default_par->v_regs ) {
1256 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1257 pm2fb_fix.id);
1258 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1259 goto err_exit_neither;
1260 }
1261
1262 /* Stash away memory register info for use when we reset the board */
1263 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1264 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1265 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1266 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1267 default_par->mem_control, default_par->boot_address,
1268 default_par->mem_config);
1269
9127fa28
PDS		 1270 if(default_par->mem_control == 0 &&
1271 default_par->boot_address == 0x31 &&
f1c15f93 1272 default_par->mem_config == 0x259fffff) {
9a31f0f7 1273 default_par->memclock = CVPPC_MEMCLOCK;
9127fa28
PDS		 1274 default_par->mem_control=0;
1275 default_par->boot_address=0x20;
1276 default_par->mem_config=0xe6002021;
f1c15f93
KH		 1277 if (pdev->subsystem_vendor == 0x1048 &&
1278 pdev->subsystem_device == 0x0a31) {
1279 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1280 pdev->subsystem_vendor, pdev->subsystem_device);
1281 DPRINTK("We have not been initialized by VGA BIOS "
1282 "and are running on an Elsa Winner 2000 Office\n");
1283 DPRINTK("Initializing card timings manually...\n");
1284 default_par->memclock=70000;
1285 }
1286 if (pdev->subsystem_vendor == 0x3d3d &&
1287 pdev->subsystem_device == 0x0100) {
1288 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1289 pdev->subsystem_vendor, pdev->subsystem_device);
1290 DPRINTK("We have not been initialized by VGA BIOS "
1291 "and are running on an 3dlabs reference board\n");
1292 DPRINTK("Initializing card timings manually...\n");
9a31f0f7 1293 default_par->memclock=74894;
f1c15f93 1294 }
9127fa28
PDS		 1295 }
1296
1da177e4
LT		 1297 /* Now work out how big lfb is going to be. */
1298 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1299 case PM2F_MEM_BANKS_1:
4560daaf 1300 pm2fb_fix.smem_len=0x200000;
1da177e4
LT		 1301 break;
1302 case PM2F_MEM_BANKS_2:
4560daaf 1303 pm2fb_fix.smem_len=0x400000;
1da177e4
LT		 1304 break;
1305 case PM2F_MEM_BANKS_3:
4560daaf 1306 pm2fb_fix.smem_len=0x600000;
1da177e4
LT		 1307 break;
1308 case PM2F_MEM_BANKS_4:
4560daaf 1309 pm2fb_fix.smem_len=0x800000;
1da177e4
LT		 1310 break;
1311 }
1da177e4 1312 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1da177e4
LT		 1313
1314 /* Linear frame buffer - request region and map it. */
1315 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1316 "pm2fb smem") ) {
1317 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1318 goto err_exit_mmio;
1319 }
4560daaf 1320 info->screen_base =
1da177e4 1321 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
4560daaf 1322 if ( !info->screen_base ) {
1da177e4
LT		 1323 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1324 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1325 goto err_exit_mmio;
1326 }
1327
d5383fcc
KH		 1328#ifdef CONFIG_MTRR
1329 default_par->mtrr_handle = -1;
1330 if (!nomtrr)
1331 default_par->mtrr_handle =
1332 mtrr_add(pm2fb_fix.smem_start,
1333 pm2fb_fix.smem_len,
1334 MTRR_TYPE_WRCOMB, 1);
1335#endif
1336
1da177e4 1337 info->fbops = &pm2fb_ops;
2f7bb99f 1338 info->fix = pm2fb_fix;
6772a2ee 1339 info->pseudo_palette = default_par->palette;
1da177e4 1340 info->flags = FBINFO_DEFAULT |
2f7bb99f
KH		 1341 FBINFO_HWACCEL_YPAN |
1342 FBINFO_HWACCEL_COPYAREA |
1343 FBINFO_HWACCEL_FILLRECT;
1da177e4 1344
d5383fcc
KH		 1345 if (noaccel) {
1346 printk(KERN_DEBUG "disabling acceleration\n");
1347 info->flags |= FBINFO_HWACCEL_DISABLED;
1348 }
1349
1da177e4
LT		 1350 if (!mode)
1351 mode = "640x480@60";
2f7bb99f
KH		 1352
1353 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1da177e4
LT		 1354 if (!err || err == 4)
1355 info->var = pm2fb_var;
1356
1357 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
435d56fc 1358 goto err_exit_both;
1da177e4
LT		 1359
1360 if (register_framebuffer(info) < 0)
435d56fc 1361 goto err_exit_all;
1da177e4
LT		 1362
1363 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
4560daaf 1364 info->node, info->fix.id, pm2fb_fix.smem_len / 1024);
1da177e4
LT		 1365
1366 /*
1367 * Our driver data
1368 */
1369 pci_set_drvdata(pdev, info);
1370
1371 return 0;
1372
1373 err_exit_all:
2f7bb99f
KH		 1374 fb_dealloc_cmap(&info->cmap);
1375 err_exit_both:
1da177e4
LT		 1376 iounmap(info->screen_base);
1377 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1378 err_exit_mmio:
1379 iounmap(default_par->v_regs);
1380 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1381 err_exit_neither:
1382 framebuffer_release(info);
1383 return err_retval;
1384}
1385
1386/**
1387 * Device removal.
1388 *
1389 * Release all device resources.
1390 *
1391 * @param pdev PCI device to clean up.
1392 */
1393static void __devexit pm2fb_remove(struct pci_dev *pdev)
1394{
1395 struct fb_info* info = pci_get_drvdata(pdev);
1396 struct fb_fix_screeninfo* fix = &info->fix;
1397 struct pm2fb_par *par = info->par;
1398
1399 unregister_framebuffer(info);
2f7bb99f 1400
d5383fcc
KH		 1401#ifdef CONFIG_MTRR
1402 if (par->mtrr_handle >= 0)
1403 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1404 info->fix.smem_len);
1405#endif /* CONFIG_MTRR */
1da177e4
LT		 1406 iounmap(info->screen_base);
1407 release_mem_region(fix->smem_start, fix->smem_len);
1408 iounmap(par->v_regs);
1409 release_mem_region(fix->mmio_start, fix->mmio_len);
1410
1411 pci_set_drvdata(pdev, NULL);
1412 kfree(info);
1413}
1414
1415static struct pci_device_id pm2fb_id_table[] = {
1416 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1417 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1418 0xff0000, 0 },
1419 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1420 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1421 0xff0000, 0 },
1422 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1423 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1424 0xff0000, 0 },
f1c15f93
KH		 1425 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1426 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1427 0xff00, 0 },
1da177e4
LT		 1428 { 0, }
1429};
1430
1431static struct pci_driver pm2fb_driver = {
1432 .name = "pm2fb",
2f7bb99f
KH		 1433 .id_table = pm2fb_id_table,
1434 .probe = pm2fb_probe,
1435 .remove = __devexit_p(pm2fb_remove),
1da177e4
LT		 1436};
1437
1438MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1439
1440
1441#ifndef MODULE
1442/**
1443 * Parse user speficied options.
1444 *
1445 * This is, comma-separated options following `video=pm2fb:'.
1446 */
1447static int __init pm2fb_setup(char *options)
1448{
1449 char* this_opt;
1450
1451 if (!options || !*options)
1452 return 0;
1453
2f7bb99f 1454 while ((this_opt = strsep(&options, ",")) != NULL) {
1da177e4
LT		 1455 if (!*this_opt)
1456 continue;
1457 if(!strcmp(this_opt, "lowhsync")) {
1458 lowhsync = 1;
1459 } else if(!strcmp(this_opt, "lowvsync")) {
1460 lowvsync = 1;
d5383fcc
KH		 1461#ifdef CONFIG_MTRR
1462 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1463 nomtrr = 1;
1464#endif
1465 } else if (!strncmp(this_opt, "noaccel", 7)) {
1466 noaccel = 1;
1da177e4
LT		 1467 } else {
1468 mode = this_opt;
1469 }
1470 }
1471 return 0;
1472}
1473#endif
1474
1475
1476static int __init pm2fb_init(void)
1477{
1478#ifndef MODULE
1479 char *option = NULL;
1480
1481 if (fb_get_options("pm2fb", &option))
1482 return -ENODEV;
1483 pm2fb_setup(option);
1484#endif
1485
1486 return pci_register_driver(&pm2fb_driver);
1487}
1488
1489module_init(pm2fb_init);
1490
1491#ifdef MODULE
1492/*
1493 * Cleanup
1494 */
1495
1496static void __exit pm2fb_exit(void)
1497{
1498 pci_unregister_driver(&pm2fb_driver);
1499}
1500#endif
1501
1502#ifdef MODULE
1503module_exit(pm2fb_exit);
1504
1505module_param(mode, charp, 0);
1506MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1507module_param(lowhsync, bool, 0);
1508MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1509module_param(lowvsync, bool, 0);
1510MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
d5383fcc
KH		 1511module_param(noaccel, bool, 0);
1512MODULE_PARM_DESC(noaccel, "Disable acceleration");
1513#ifdef CONFIG_MTRR
1514module_param(nomtrr, bool, 0);
1515MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1516#endif
1da177e4
LT		 1517
1518MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1519MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1520MODULE_LICENSE("GPL");
1521#endif
kernel source for telekom puls (alcatel/mediatek)