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fbcon: check console-fb mapping in fbcon_get_requirement
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / pm2fb.c
CommitLineData
1da177e4
LT		 1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/kernel.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/slab.h>
37#include <linux/delay.h>
38#include <linux/fb.h>
39#include <linux/init.h>
40#include <linux/pci.h>
41
42#include <video/permedia2.h>
43#include <video/cvisionppc.h>
44
45#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46#error "The endianness of the target host has not been defined."
47#endif
48
49#if !defined(CONFIG_PCI)
50#error "Only generic PCI cards supported."
51#endif
52
53#undef PM2FB_MASTER_DEBUG
54#ifdef PM2FB_MASTER_DEBUG
55#define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
56#else
57#define DPRINTK(a,b...)
58#endif
59
60/*
61 * Driver data
62 */
63static char *mode __devinitdata = NULL;
64
65/*
66 * The XFree GLINT driver will (I think to implement hardware cursor
67 * support on TVP4010 and similar where there is no RAMDAC - see
68 * comment in set_video) always request +ve sync regardless of what
69 * the mode requires. This screws me because I have a Sun
70 * fixed-frequency monitor which absolutely has to have -ve sync. So
71 * these flags allow the user to specify that requests for +ve sync
72 * should be silently turned in -ve sync.
73 */
c16c556e
DJ		 74static int lowhsync;
75static int lowvsync;
1da177e4
LT		 76
77/*
78 * The hardware state of the graphics card that isn't part of the
79 * screeninfo.
80 */
81struct pm2fb_par
82{
83 pm2type_t type; /* Board type */
84 u32 fb_size; /* framebuffer memory size */
85 unsigned char __iomem *v_fb; /* virtual address of frame buffer */
86 unsigned char __iomem *v_regs;/* virtual address of p_regs */
87 u32 memclock; /* memclock */
88 u32 video; /* video flags before blanking */
89 u32 mem_config; /* MemConfig reg at probe */
90 u32 mem_control; /* MemControl reg at probe */
91 u32 boot_address; /* BootAddress reg at probe */
6772a2ee 92 u32 palette[16];
1da177e4
LT		 93};
94
95/*
96 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
97 * if we don't use modedb.
98 */
99static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
100 .id = "",
101 .type = FB_TYPE_PACKED_PIXELS,
102 .visual = FB_VISUAL_PSEUDOCOLOR,
103 .xpanstep = 1,
104 .ypanstep = 1,
105 .ywrapstep = 0,
106 .accel = FB_ACCEL_NONE,
107};
108
109/*
110 * Default video mode. In case the modedb doesn't work.
111 */
112static struct fb_var_screeninfo pm2fb_var __devinitdata = {
113 /* "640x480, 8 bpp @ 60 Hz */
114 .xres = 640,
115 .yres = 480,
116 .xres_virtual = 640,
117 .yres_virtual = 480,
118 .bits_per_pixel =8,
119 .red = {0, 8, 0},
120 .blue = {0, 8, 0},
121 .green = {0, 8, 0},
122 .activate = FB_ACTIVATE_NOW,
123 .height = -1,
124 .width = -1,
125 .accel_flags = 0,
126 .pixclock = 39721,
127 .left_margin = 40,
128 .right_margin = 24,
129 .upper_margin = 32,
130 .lower_margin = 11,
131 .hsync_len = 96,
132 .vsync_len = 2,
133 .vmode = FB_VMODE_NONINTERLACED
134};
135
136/*
137 * Utility functions
138 */
139
77933d72 140static inline u32 RD32(unsigned char __iomem *base, s32 off)
1da177e4
LT		 141{
142 return fb_readl(base + off);
143}
144
77933d72 145static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
1da177e4
LT		 146{
147 fb_writel(v, base + off);
148}
149
77933d72 150static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
1da177e4
LT		 151{
152 return RD32(p->v_regs, off);
153}
154
77933d72 155static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
1da177e4
LT		 156{
157 WR32(p->v_regs, off, v);
158}
159
77933d72 160static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
1da177e4
LT		 161{
162 int index = PM2R_RD_INDEXED_DATA;
163 switch (p->type) {
164 case PM2_TYPE_PERMEDIA2:
165 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
166 break;
167 case PM2_TYPE_PERMEDIA2V:
168 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
169 index = PM2VR_RD_INDEXED_DATA;
170 break;
171 }
172 mb();
173 return pm2_RD(p, index);
174}
175
77933d72 176static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 177{
178 int index = PM2R_RD_INDEXED_DATA;
179 switch (p->type) {
180 case PM2_TYPE_PERMEDIA2:
181 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
182 break;
183 case PM2_TYPE_PERMEDIA2V:
184 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
185 index = PM2VR_RD_INDEXED_DATA;
186 break;
187 }
188 mb();
189 pm2_WR(p, index, v);
190}
191
77933d72 192static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
1da177e4
LT		 193{
194 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
195 mb();
196 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
197}
198
199#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
200#define WAIT_FIFO(p,a)
201#else
77933d72 202static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
1da177e4
LT		 203{
204 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
205 mb();
206}
207#endif
208
209/*
210 * partial products for the supported horizontal resolutions.
211 */
212#define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
213static const struct {
214 u16 width;
215 u16 pp;
216} pp_table[] = {
217 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
218 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
219 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
220 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
221 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
222 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
223 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
224 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
225 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
226 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
227 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
228 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
229 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
230 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
231 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
232 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
233 { 0, 0 } };
234
235static u32 partprod(u32 xres)
236{
237 int i;
238
239 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
240 ;
241 if ( pp_table[i].width == 0 )
242 DPRINTK("invalid width %u\n", xres);
243 return pp_table[i].pp;
244}
245
246static u32 to3264(u32 timing, int bpp, int is64)
247{
248 switch (bpp) {
249 case 8:
250 timing >>= 2 + is64;
251 break;
252 case 16:
253 timing >>= 1 + is64;
254 break;
255 case 24:
256 timing = (timing * 3) >> (2 + is64);
257 break;
258 case 32:
259 if (is64)
260 timing >>= 1;
261 break;
262 }
263 return timing;
264}
265
266static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
267 unsigned char* pp)
268{
269 unsigned char m;
270 unsigned char n;
271 unsigned char p;
272 u32 f;
273 s32 curr;
274 s32 delta = 100000;
275
276 *mm = *nn = *pp = 0;
277 for (n = 2; n < 15; n++) {
278 for (m = 2; m; m++) {
279 f = PM2_REFERENCE_CLOCK * m / n;
280 if (f >= 150000 && f <= 300000) {
281 for ( p = 0; p < 5; p++, f >>= 1) {
282 curr = ( clk > f ) ? clk - f : f - clk;
283 if ( curr < delta ) {
284 delta=curr;
285 *mm=m;
286 *nn=n;
287 *pp=p;
288 }
289 }
290 }
291 }
292 }
293}
294
295static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
296 unsigned char* pp)
297{
298 unsigned char m;
299 unsigned char n;
300 unsigned char p;
301 u32 f;
302 s32 delta = 1000;
303
304 *mm = *nn = *pp = 0;
d4a96b53
KH		 305 for ( m = 1; m < 128; m++) {
306 for (n = 2 * m + 1; n; n++) {
1da177e4 307 for ( p = 0; p < 2; p++) {
d4a96b53 308 f = ( PM2_REFERENCE_CLOCK >> ( p + 1 )) * n / m;
1da177e4
LT		 309 if ( clk > f - delta && clk < f + delta ) {
310 delta = ( clk > f ) ? clk - f : f - clk;
311 *mm=m;
312 *nn=n;
313 *pp=p;
314 }
315 }
316 }
317 }
318}
319
320static void clear_palette(struct pm2fb_par* p) {
321 int i=256;
322
323 WAIT_FIFO(p, 1);
324 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
325 wmb();
326 while (i--) {
327 WAIT_FIFO(p, 3);
328 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
329 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
330 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
331 }
332}
333
334static void reset_card(struct pm2fb_par* p)
335{
336 if (p->type == PM2_TYPE_PERMEDIA2V)
337 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
338 pm2_WR(p, PM2R_RESET_STATUS, 0);
339 mb();
340 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
341 ;
342 mb();
343#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
344 DPRINTK("FIFO disconnect enabled\n");
345 pm2_WR(p, PM2R_FIFO_DISCON, 1);
346 mb();
347#endif
348
349 /* Restore stashed memory config information from probe */
350 WAIT_FIFO(p, 3);
351 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
352 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
353 wmb();
354 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
355}
356
357static void reset_config(struct pm2fb_par* p)
358{
359 WAIT_FIFO(p, 52);
360 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
361 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
362 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
363 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
364 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
365 pm2_WR(p, PM2R_APERTURE_ONE, 0);
366 pm2_WR(p, PM2R_APERTURE_TWO, 0);
367 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
368 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
369 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
370 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
371 pm2_WR(p, PM2R_LB_READ_MODE, 0);
372 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
373 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
374 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
375 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
376 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
377 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
378 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
379 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
380 pm2_WR(p, PM2R_DITHER_MODE, 0);
381 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
382 pm2_WR(p, PM2R_DEPTH_MODE, 0);
383 pm2_WR(p, PM2R_STENCIL_MODE, 0);
384 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
385 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
386 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
387 pm2_WR(p, PM2R_YUV_MODE, 0);
388 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
389 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
390 pm2_WR(p, PM2R_FOG_MODE, 0);
391 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
392 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
393 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
394 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
395 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
396 switch (p->type) {
397 case PM2_TYPE_PERMEDIA2:
398 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
399 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
400 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
401 break;
402 case PM2_TYPE_PERMEDIA2V:
403 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
404 break;
405 }
406 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
407 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
408 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
409 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
410 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
411}
412
413static void set_aperture(struct pm2fb_par* p, u32 depth)
414{
415 /*
416 * The hardware is little-endian. When used in big-endian
417 * hosts, the on-chip aperture settings are used where
418 * possible to translate from host to card byte order.
419 */
420 WAIT_FIFO(p, 4);
421#ifdef __LITTLE_ENDIAN
422 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
423#else
424 switch (depth) {
425 case 24: /* RGB->BGR */
426 /*
427 * We can't use the aperture to translate host to
428 * card byte order here, so we switch to BGR mode
429 * in pm2fb_set_par().
430 */
431 case 8: /* B->B */
432 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
433 break;
434 case 16: /* HL->LH */
435 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
436 break;
437 case 32: /* RGBA->ABGR */
438 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
439 break;
440 }
441#endif
442
443 // We don't use aperture two, so this may be superflous
444 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
445}
446
447static void set_color(struct pm2fb_par* p, unsigned char regno,
448 unsigned char r, unsigned char g, unsigned char b)
449{
450 WAIT_FIFO(p, 4);
451 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
452 wmb();
453 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
454 wmb();
455 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
456 wmb();
457 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
458}
459
460static void set_memclock(struct pm2fb_par* par, u32 clk)
461{
462 int i;
463 unsigned char m, n, p;
464
e5d809d7
KH		 465 switch (par->type) {
466 case PM2_TYPE_PERMEDIA2V:
467 pm2v_mnp(clk/2, &m, &n, &p);
468 WAIT_FIFO(par, 8);
469 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
470 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
471 wmb();
472 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
473 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
474 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
475 wmb();
476 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
477 rmb();
478 for (i = 256;
479 i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2);
480 i--)
481 ;
482 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
483 break;
484 case PM2_TYPE_PERMEDIA2:
485 pm2_mnp(clk, &m, &n, &p);
486 WAIT_FIFO(par, 10);
487 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
488 wmb();
489 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
490 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
491 wmb();
492 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
493 wmb();
494 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
495 rmb();
496 for (i = 256;
497 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
498 i--)
499 ;
500 break;
501 }
1da177e4
LT		 502}
503
504static void set_pixclock(struct pm2fb_par* par, u32 clk)
505{
506 int i;
507 unsigned char m, n, p;
508
509 switch (par->type) {
510 case PM2_TYPE_PERMEDIA2:
511 pm2_mnp(clk, &m, &n, &p);
512 WAIT_FIFO(par, 8);
513 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
514 wmb();
515 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
516 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
517 wmb();
518 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
519 wmb();
520 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
521 rmb();
522 for (i = 256;
523 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
524 i--)
525 ;
526 break;
527 case PM2_TYPE_PERMEDIA2V:
528 pm2v_mnp(clk/2, &m, &n, &p);
529 WAIT_FIFO(par, 8);
530 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
531 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
532 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
533 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
534 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
535 break;
536 }
537}
538
539static void set_video(struct pm2fb_par* p, u32 video) {
540 u32 tmp;
541 u32 vsync;
542
543 vsync = video;
544
545 DPRINTK("video = 0x%x\n", video);
546
547 /*
548 * The hardware cursor needs +vsync to recognise vert retrace.
549 * We may not be using the hardware cursor, but the X Glint
550 * driver may well. So always set +hsync/+vsync and then set
551 * the RAMDAC to invert the sync if necessary.
552 */
553 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
554 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
555
556 WAIT_FIFO(p, 5);
557 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
558
559 switch (p->type) {
560 case PM2_TYPE_PERMEDIA2:
561 tmp = PM2F_RD_PALETTE_WIDTH_8;
562 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
563 tmp |= 4; /* invert hsync */
564 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
565 tmp |= 8; /* invert vsync */
566 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
567 break;
568 case PM2_TYPE_PERMEDIA2V:
569 tmp = 0;
570 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
571 tmp |= 1; /* invert hsync */
572 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
573 tmp |= 4; /* invert vsync */
574 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
575 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
576 break;
577 }
578}
579
580/*
581 *
582 */
583
584/**
585 * pm2fb_check_var - Optional function. Validates a var passed in.
586 * @var: frame buffer variable screen structure
587 * @info: frame buffer structure that represents a single frame buffer
588 *
589 * Checks to see if the hardware supports the state requested by
590 * var passed in.
591 *
592 * Returns negative errno on error, or zero on success.
593 */
594static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
595{
596 u32 lpitch;
597
598 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
599 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
600 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
601 return -EINVAL;
602 }
603
604 if (var->xres != var->xres_virtual) {
605 DPRINTK("virtual x resolution != physical x resolution not supported\n");
606 return -EINVAL;
607 }
608
609 if (var->yres > var->yres_virtual) {
610 DPRINTK("virtual y resolution < physical y resolution not possible\n");
611 return -EINVAL;
612 }
613
614 if (var->xoffset) {
615 DPRINTK("xoffset not supported\n");
616 return -EINVAL;
617 }
618
619 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
620 DPRINTK("interlace not supported\n");
621 return -EINVAL;
622 }
623
624 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
625 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
626
627 if (var->xres < 320 || var->xres > 1600) {
628 DPRINTK("width not supported: %u\n", var->xres);
629 return -EINVAL;
630 }
631
632 if (var->yres < 200 || var->yres > 1200) {
633 DPRINTK("height not supported: %u\n", var->yres);
634 return -EINVAL;
635 }
636
637 if (lpitch * var->yres_virtual > info->fix.smem_len) {
638 DPRINTK("no memory for screen (%ux%ux%u)\n",
639 var->xres, var->yres_virtual, var->bits_per_pixel);
640 return -EINVAL;
641 }
642
643 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
644 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
645 return -EINVAL;
646 }
647
648 switch(var->bits_per_pixel) {
649 case 8:
650 var->red.length = var->green.length = var->blue.length = 8;
651 break;
652 case 16:
653 var->red.offset = 11;
654 var->red.length = 5;
655 var->green.offset = 5;
656 var->green.length = 6;
657 var->blue.offset = 0;
658 var->blue.length = 5;
659 break;
660 case 32:
661 var->transp.offset = 24;
662 var->transp.length = 8;
663 var->red.offset = 16;
664 var->green.offset = 8;
665 var->blue.offset = 0;
666 var->red.length = var->green.length = var->blue.length = 8;
667 break;
668 case 24:
669#ifdef __BIG_ENDIAN
670 var->red.offset = 0;
671 var->blue.offset = 16;
672#else
673 var->red.offset = 16;
674 var->blue.offset = 0;
675#endif
676 var->green.offset = 8;
677 var->red.length = var->green.length = var->blue.length = 8;
678 break;
679 }
680 var->height = var->width = -1;
681
682 var->accel_flags = 0; /* Can't mmap if this is on */
683
684 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
685 var->xres, var->yres, var->bits_per_pixel);
686 return 0;
687}
688
689/**
690 * pm2fb_set_par - Alters the hardware state.
691 * @info: frame buffer structure that represents a single frame buffer
692 *
693 * Using the fb_var_screeninfo in fb_info we set the resolution of the
694 * this particular framebuffer.
695 */
696static int pm2fb_set_par(struct fb_info *info)
697{
6772a2ee 698 struct pm2fb_par *par = info->par;
1da177e4
LT		 699 u32 pixclock;
700 u32 width, height, depth;
701 u32 hsstart, hsend, hbend, htotal;
702 u32 vsstart, vsend, vbend, vtotal;
703 u32 stride;
704 u32 base;
705 u32 video = 0;
706 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
707 u32 txtmap = 0;
708 u32 pixsize = 0;
709 u32 clrformat = 0;
710 u32 xres;
711 int data64;
712
713 reset_card(par);
714 reset_config(par);
715 clear_palette(par);
716 if ( par->memclock )
717 set_memclock(par, par->memclock);
718
719 width = (info->var.xres_virtual + 7) & ~7;
720 height = info->var.yres_virtual;
721 depth = (info->var.bits_per_pixel + 7) & ~7;
722 depth = (depth > 32) ? 32 : depth;
723 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
724
725 xres = (info->var.xres + 31) & ~31;
726 pixclock = PICOS2KHZ(info->var.pixclock);
727 if (pixclock > PM2_MAX_PIXCLOCK) {
728 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
729 return -EINVAL;
730 }
731
732 hsstart = to3264(info->var.right_margin, depth, data64);
733 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
734 hbend = hsend + to3264(info->var.left_margin, depth, data64);
735 htotal = to3264(xres, depth, data64) + hbend - 1;
736 vsstart = (info->var.lower_margin)
737 ? info->var.lower_margin - 1
738 : 0; /* FIXME! */
739 vsend = info->var.lower_margin + info->var.vsync_len - 1;
740 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
741 vtotal = info->var.yres + vbend - 1;
742 stride = to3264(width, depth, 1);
743 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
744 if (data64)
745 video |= PM2F_DATA_64_ENABLE;
746
747 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
748 if (lowhsync) {
749 DPRINTK("ignoring +hsync, using -hsync.\n");
750 video |= PM2F_HSYNC_ACT_LOW;
751 } else
752 video |= PM2F_HSYNC_ACT_HIGH;
753 }
754 else
755 video |= PM2F_HSYNC_ACT_LOW;
756 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
757 if (lowvsync) {
758 DPRINTK("ignoring +vsync, using -vsync.\n");
759 video |= PM2F_VSYNC_ACT_LOW;
760 } else
761 video |= PM2F_VSYNC_ACT_HIGH;
762 }
763 else
764 video |= PM2F_VSYNC_ACT_LOW;
765 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
766 DPRINTK("interlaced not supported\n");
767 return -EINVAL;
768 }
769 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
770 video |= PM2F_LINE_DOUBLE;
771 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
772 video |= PM2F_VIDEO_ENABLE;
773 par->video = video;
774
775 info->fix.visual =
776 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
777 info->fix.line_length = info->var.xres * depth / 8;
778 info->cmap.len = 256;
779
780 /*
781 * Settings calculated. Now write them out.
782 */
783 if (par->type == PM2_TYPE_PERMEDIA2V) {
784 WAIT_FIFO(par, 1);
785 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
786 }
787
788 set_aperture(par, depth);
789
790 mb();
791 WAIT_FIFO(par, 19);
792 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
793 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
794 switch (depth) {
795 case 8:
796 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
797 clrformat = 0x0e;
798 break;
799 case 16:
800 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
801 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
802 txtmap = PM2F_TEXTEL_SIZE_16;
803 pixsize = 1;
804 clrformat = 0x70;
805 break;
806 case 32:
807 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
808 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
809 txtmap = PM2F_TEXTEL_SIZE_32;
810 pixsize = 2;
811 clrformat = 0x20;
812 break;
813 case 24:
814 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
815 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
816 txtmap = PM2F_TEXTEL_SIZE_24;
817 pixsize = 4;
818 clrformat = 0x20;
819 break;
820 }
821 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
822 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
823 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
824 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
825 pm2_WR(par, PM2R_H_TOTAL, htotal);
826 pm2_WR(par, PM2R_HS_START, hsstart);
827 pm2_WR(par, PM2R_HS_END, hsend);
828 pm2_WR(par, PM2R_HG_END, hbend);
829 pm2_WR(par, PM2R_HB_END, hbend);
830 pm2_WR(par, PM2R_V_TOTAL, vtotal);
831 pm2_WR(par, PM2R_VS_START, vsstart);
832 pm2_WR(par, PM2R_VS_END, vsend);
833 pm2_WR(par, PM2R_VB_END, vbend);
834 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
835 wmb();
836 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
837 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
838 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
839 wmb();
840 pm2_WR(par, PM2R_SCREEN_BASE, base);
841 wmb();
842 set_video(par, video);
843 WAIT_FIFO(par, 4);
844 switch (par->type) {
845 case PM2_TYPE_PERMEDIA2:
846 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
847 break;
848 case PM2_TYPE_PERMEDIA2V:
849 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
850 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
851 break;
852 }
853 set_pixclock(par, pixclock);
854 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
855 info->var.xres, info->var.yres, info->var.bits_per_pixel);
856 return 0;
857}
858
859/**
860 * pm2fb_setcolreg - Sets a color register.
861 * @regno: boolean, 0 copy local, 1 get_user() function
862 * @red: frame buffer colormap structure
863 * @green: The green value which can be up to 16 bits wide
864 * @blue: The blue value which can be up to 16 bits wide.
865 * @transp: If supported the alpha value which can be up to 16 bits wide.
866 * @info: frame buffer info structure
867 *
868 * Set a single color register. The values supplied have a 16 bit
869 * magnitude which needs to be scaled in this function for the hardware.
870 * Pretty much a direct lift from tdfxfb.c.
871 *
872 * Returns negative errno on error, or zero on success.
873 */
874static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
875 unsigned blue, unsigned transp,
876 struct fb_info *info)
877{
6772a2ee 878 struct pm2fb_par *par = info->par;
1da177e4
LT		 879
880 if (regno >= info->cmap.len) /* no. of hw registers */
881 return 1;
882 /*
883 * Program hardware... do anything you want with transp
884 */
885
886 /* grayscale works only partially under directcolor */
887 if (info->var.grayscale) {
888 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
889 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
890 }
891
892 /* Directcolor:
893 * var->{color}.offset contains start of bitfield
894 * var->{color}.length contains length of bitfield
895 * {hardwarespecific} contains width of DAC
896 * cmap[X] is programmed to
897 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
898 * RAMDAC[X] is programmed to (red, green, blue)
899 *
900 * Pseudocolor:
901 * uses offset = 0 && length = DAC register width.
902 * var->{color}.offset is 0
903 * var->{color}.length contains widht of DAC
904 * cmap is not used
905 * DAC[X] is programmed to (red, green, blue)
906 * Truecolor:
907 * does not use RAMDAC (usually has 3 of them).
908 * var->{color}.offset contains start of bitfield
909 * var->{color}.length contains length of bitfield
910 * cmap is programmed to
911 * (red << red.offset) | (green << green.offset) |
912 * (blue << blue.offset) | (transp << transp.offset)
913 * RAMDAC does not exist
914 */
915#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
916 switch (info->fix.visual) {
917 case FB_VISUAL_TRUECOLOR:
918 case FB_VISUAL_PSEUDOCOLOR:
919 red = CNVT_TOHW(red, info->var.red.length);
920 green = CNVT_TOHW(green, info->var.green.length);
921 blue = CNVT_TOHW(blue, info->var.blue.length);
922 transp = CNVT_TOHW(transp, info->var.transp.length);
923 break;
924 case FB_VISUAL_DIRECTCOLOR:
925 /* example here assumes 8 bit DAC. Might be different
926 * for your hardware */
927 red = CNVT_TOHW(red, 8);
928 green = CNVT_TOHW(green, 8);
929 blue = CNVT_TOHW(blue, 8);
930 /* hey, there is bug in transp handling... */
931 transp = CNVT_TOHW(transp, 8);
932 break;
933 }
934#undef CNVT_TOHW
935 /* Truecolor has hardware independent palette */
936 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
937 u32 v;
938
939 if (regno >= 16)
940 return 1;
941
942 v = (red << info->var.red.offset) |
943 (green << info->var.green.offset) |
944 (blue << info->var.blue.offset) |
945 (transp << info->var.transp.offset);
946
947 switch (info->var.bits_per_pixel) {
948 case 8:
949 break;
950 case 16:
951 case 24:
952 case 32:
6772a2ee 953 par->palette[regno] = v;
1da177e4
LT		 954 break;
955 }
956 return 0;
957 }
958 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
959 set_color(par, regno, red, green, blue);
960
961 return 0;
962}
963
964/**
965 * pm2fb_pan_display - Pans the display.
966 * @var: frame buffer variable screen structure
967 * @info: frame buffer structure that represents a single frame buffer
968 *
969 * Pan (or wrap, depending on the `vmode' field) the display using the
970 * `xoffset' and `yoffset' fields of the `var' structure.
971 * If the values don't fit, return -EINVAL.
972 *
973 * Returns negative errno on error, or zero on success.
974 *
975 */
976static int pm2fb_pan_display(struct fb_var_screeninfo *var,
977 struct fb_info *info)
978{
6772a2ee 979 struct pm2fb_par *p = info->par;
1da177e4
LT		 980 u32 base;
981 u32 depth;
982 u32 xres;
983
984 xres = (var->xres + 31) & ~31;
985 depth = (var->bits_per_pixel + 7) & ~7;
986 depth = (depth > 32) ? 32 : depth;
987 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
988 WAIT_FIFO(p, 1);
989 pm2_WR(p, PM2R_SCREEN_BASE, base);
990 return 0;
991}
992
993/**
994 * pm2fb_blank - Blanks the display.
995 * @blank_mode: the blank mode we want.
996 * @info: frame buffer structure that represents a single frame buffer
997 *
998 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
999 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1000 * video mode which doesn't support it. Implements VESA suspend
1001 * and powerdown modes on hardware that supports disabling hsync/vsync:
1002 * blank_mode == 2: suspend vsync
1003 * blank_mode == 3: suspend hsync
1004 * blank_mode == 4: powerdown
1005 *
1006 * Returns negative errno on error, or zero on success.
1007 *
1008 */
1009static int pm2fb_blank(int blank_mode, struct fb_info *info)
1010{
6772a2ee 1011 struct pm2fb_par *par = info->par;
1da177e4
LT		 1012 u32 video = par->video;
1013
1014 DPRINTK("blank_mode %d\n", blank_mode);
1015
1016 switch (blank_mode) {
1017 case FB_BLANK_UNBLANK:
1018 /* Screen: On */
1019 video |= PM2F_VIDEO_ENABLE;
1020 break;
1021 case FB_BLANK_NORMAL:
1022 /* Screen: Off */
1023 video &= ~PM2F_VIDEO_ENABLE;
1024 break;
1025 case FB_BLANK_VSYNC_SUSPEND:
1026 /* VSync: Off */
1027 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1028 break;
1029 case FB_BLANK_HSYNC_SUSPEND:
1030 /* HSync: Off */
1031 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1032 break;
1033 case FB_BLANK_POWERDOWN:
1034 /* HSync: Off, VSync: Off */
1035 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1036 break;
1037 }
1038 set_video(par, video);
1039 return 0;
1040}
1041
1042/* ------------ Hardware Independent Functions ------------ */
1043
1044/*
1045 * Frame buffer operations
1046 */
1047
1048static struct fb_ops pm2fb_ops = {
1049 .owner = THIS_MODULE,
1050 .fb_check_var = pm2fb_check_var,
1051 .fb_set_par = pm2fb_set_par,
1052 .fb_setcolreg = pm2fb_setcolreg,
1053 .fb_blank = pm2fb_blank,
1054 .fb_pan_display = pm2fb_pan_display,
1055 .fb_fillrect = cfb_fillrect,
1056 .fb_copyarea = cfb_copyarea,
1057 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 1058};
1059
1060/*
1061 * PCI stuff
1062 */
1063
1064
1065/**
1066 * Device initialisation
1067 *
1068 * Initialise and allocate resource for PCI device.
1069 *
1070 * @param pdev PCI device.
1071 * @param id PCI device ID.
1072 */
1073static int __devinit pm2fb_probe(struct pci_dev *pdev,
1074 const struct pci_device_id *id)
1075{
1076 struct pm2fb_par *default_par;
1077 struct fb_info *info;
6772a2ee 1078 int err, err_retval = -ENXIO;
1da177e4
LT		 1079
1080 err = pci_enable_device(pdev);
1081 if ( err ) {
1082 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1083 return err;
1084 }
1085
6772a2ee 1086 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1da177e4
LT		 1087 if ( !info )
1088 return -ENOMEM;
6772a2ee 1089 default_par = info->par;
1da177e4
LT		 1090
1091 switch (pdev->device) {
1092 case PCI_DEVICE_ID_TI_TVP4020:
1093 strcpy(pm2fb_fix.id, "TVP4020");
1094 default_par->type = PM2_TYPE_PERMEDIA2;
1095 break;
1096 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1097 strcpy(pm2fb_fix.id, "Permedia2");
1098 default_par->type = PM2_TYPE_PERMEDIA2;
1099 break;
1100 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1101 strcpy(pm2fb_fix.id, "Permedia2v");
1102 default_par->type = PM2_TYPE_PERMEDIA2V;
1103 break;
1104 }
1105
1106 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1107 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1108
1109#if defined(__BIG_ENDIAN)
1110 /*
1111 * PM2 has a 64k register file, mapped twice in 128k. Lower
1112 * map is little-endian, upper map is big-endian.
1113 */
1114 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1115 DPRINTK("Adjusting register base for big-endian.\n");
1116#endif
1117 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1118
1119 /* Registers - request region and map it. */
1120 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1121 "pm2fb regbase") ) {
1122 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1123 goto err_exit_neither;
1124 }
1125 default_par->v_regs =
1126 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1127 if ( !default_par->v_regs ) {
1128 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1129 pm2fb_fix.id);
1130 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1131 goto err_exit_neither;
1132 }
1133
1134 /* Stash away memory register info for use when we reset the board */
1135 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1136 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1137 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1138 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1139 default_par->mem_control, default_par->boot_address,
1140 default_par->mem_config);
1141
f1c15f93 1142 default_par->memclock = CVPPC_MEMCLOCK;
9127fa28
PDS		 1143 if(default_par->mem_control == 0 &&
1144 default_par->boot_address == 0x31 &&
f1c15f93 1145 default_par->mem_config == 0x259fffff) {
9127fa28
PDS		 1146 default_par->mem_control=0;
1147 default_par->boot_address=0x20;
1148 default_par->mem_config=0xe6002021;
f1c15f93
KH		 1149 if (pdev->subsystem_vendor == 0x1048 &&
1150 pdev->subsystem_device == 0x0a31) {
1151 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1152 pdev->subsystem_vendor, pdev->subsystem_device);
1153 DPRINTK("We have not been initialized by VGA BIOS "
1154 "and are running on an Elsa Winner 2000 Office\n");
1155 DPRINTK("Initializing card timings manually...\n");
1156 default_par->memclock=70000;
1157 }
1158 if (pdev->subsystem_vendor == 0x3d3d &&
1159 pdev->subsystem_device == 0x0100) {
1160 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1161 pdev->subsystem_vendor, pdev->subsystem_device);
1162 DPRINTK("We have not been initialized by VGA BIOS "
1163 "and are running on an 3dlabs reference board\n");
1164 DPRINTK("Initializing card timings manually...\n");
1165 default_par->memclock=70000;
1166 }
9127fa28
PDS		 1167 }
1168
1da177e4
LT		 1169 /* Now work out how big lfb is going to be. */
1170 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1171 case PM2F_MEM_BANKS_1:
1172 default_par->fb_size=0x200000;
1173 break;
1174 case PM2F_MEM_BANKS_2:
1175 default_par->fb_size=0x400000;
1176 break;
1177 case PM2F_MEM_BANKS_3:
1178 default_par->fb_size=0x600000;
1179 break;
1180 case PM2F_MEM_BANKS_4:
1181 default_par->fb_size=0x800000;
1182 break;
1183 }
1da177e4
LT		 1184 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1185 pm2fb_fix.smem_len = default_par->fb_size;
1186
1187 /* Linear frame buffer - request region and map it. */
1188 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1189 "pm2fb smem") ) {
1190 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1191 goto err_exit_mmio;
1192 }
1193 info->screen_base = default_par->v_fb =
1194 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1195 if ( !default_par->v_fb ) {
1196 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1197 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1198 goto err_exit_mmio;
1199 }
1200
1201 info->fbops = &pm2fb_ops;
1202 info->fix = pm2fb_fix;
6772a2ee 1203 info->pseudo_palette = default_par->palette;
1da177e4
LT		 1204 info->flags = FBINFO_DEFAULT |
1205 FBINFO_HWACCEL_YPAN;
1206
1207 if (!mode)
1208 mode = "640x480@60";
1209
1210 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1211 if (!err || err == 4)
1212 info->var = pm2fb_var;
1213
1214 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1215 goto err_exit_all;
1216
1217 if (register_framebuffer(info) < 0)
1218 goto err_exit_both;
1219
1220 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1221 info->node, info->fix.id, default_par->fb_size / 1024);
1222
1223 /*
1224 * Our driver data
1225 */
1226 pci_set_drvdata(pdev, info);
1227
1228 return 0;
1229
1230 err_exit_all:
1231 fb_dealloc_cmap(&info->cmap);
1232 err_exit_both:
1233 iounmap(info->screen_base);
1234 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1235 err_exit_mmio:
1236 iounmap(default_par->v_regs);
1237 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1238 err_exit_neither:
1239 framebuffer_release(info);
1240 return err_retval;
1241}
1242
1243/**
1244 * Device removal.
1245 *
1246 * Release all device resources.
1247 *
1248 * @param pdev PCI device to clean up.
1249 */
1250static void __devexit pm2fb_remove(struct pci_dev *pdev)
1251{
1252 struct fb_info* info = pci_get_drvdata(pdev);
1253 struct fb_fix_screeninfo* fix = &info->fix;
1254 struct pm2fb_par *par = info->par;
1255
1256 unregister_framebuffer(info);
1257
1258 iounmap(info->screen_base);
1259 release_mem_region(fix->smem_start, fix->smem_len);
1260 iounmap(par->v_regs);
1261 release_mem_region(fix->mmio_start, fix->mmio_len);
1262
1263 pci_set_drvdata(pdev, NULL);
1264 kfree(info);
1265}
1266
1267static struct pci_device_id pm2fb_id_table[] = {
1268 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1269 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1270 0xff0000, 0 },
1271 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1272 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1273 0xff0000, 0 },
1274 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1275 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1276 0xff0000, 0 },
f1c15f93
KH		 1277 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1278 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1279 0xff00, 0 },
1da177e4
LT		 1280 { 0, }
1281};
1282
1283static struct pci_driver pm2fb_driver = {
1284 .name = "pm2fb",
1285 .id_table = pm2fb_id_table,
1286 .probe = pm2fb_probe,
1287 .remove = __devexit_p(pm2fb_remove),
1288};
1289
1290MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1291
1292
1293#ifndef MODULE
1294/**
1295 * Parse user speficied options.
1296 *
1297 * This is, comma-separated options following `video=pm2fb:'.
1298 */
1299static int __init pm2fb_setup(char *options)
1300{
1301 char* this_opt;
1302
1303 if (!options || !*options)
1304 return 0;
1305
1306 while ((this_opt = strsep(&options, ",")) != NULL) {
1307 if (!*this_opt)
1308 continue;
1309 if(!strcmp(this_opt, "lowhsync")) {
1310 lowhsync = 1;
1311 } else if(!strcmp(this_opt, "lowvsync")) {
1312 lowvsync = 1;
1313 } else {
1314 mode = this_opt;
1315 }
1316 }
1317 return 0;
1318}
1319#endif
1320
1321
1322static int __init pm2fb_init(void)
1323{
1324#ifndef MODULE
1325 char *option = NULL;
1326
1327 if (fb_get_options("pm2fb", &option))
1328 return -ENODEV;
1329 pm2fb_setup(option);
1330#endif
1331
1332 return pci_register_driver(&pm2fb_driver);
1333}
1334
1335module_init(pm2fb_init);
1336
1337#ifdef MODULE
1338/*
1339 * Cleanup
1340 */
1341
1342static void __exit pm2fb_exit(void)
1343{
1344 pci_unregister_driver(&pm2fb_driver);
1345}
1346#endif
1347
1348#ifdef MODULE
1349module_exit(pm2fb_exit);
1350
1351module_param(mode, charp, 0);
1352MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1353module_param(lowhsync, bool, 0);
1354MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1355module_param(lowvsync, bool, 0);
1356MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1357
1358MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1359MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1360MODULE_LICENSE("GPL");
1361#endif
kernel source for telekom puls (alcatel/mediatek)