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OMAPFB: Adding a check for timings in set_def_mode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
80c39712
TV		 35
36#include <plat/sram.h>
37#include <plat/clock.h>
38
39#include <plat/display.h>
40
41#include "dss.h"
a0acb557 42#include "dss_features.h"
80c39712
TV		 43
44/* DISPC */
8613b000 45#define DISPC_SZ_REGS SZ_4K
80c39712
TV		 46
47struct dispc_reg { u16 idx; };
48
49#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
50
8613b000
SS		 51/*
52 * DISPC common registers and
53 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
54 * DIGIT, and ch = 2 for LCD2
55 */
80c39712
TV		 56#define DISPC_REVISION DISPC_REG(0x0000)
57#define DISPC_SYSCONFIG DISPC_REG(0x0010)
58#define DISPC_SYSSTATUS DISPC_REG(0x0014)
59#define DISPC_IRQSTATUS DISPC_REG(0x0018)
60#define DISPC_IRQENABLE DISPC_REG(0x001C)
61#define DISPC_CONTROL DISPC_REG(0x0040)
8613b000 62#define DISPC_CONTROL2 DISPC_REG(0x0238)
80c39712 63#define DISPC_CONFIG DISPC_REG(0x0044)
8613b000 64#define DISPC_CONFIG2 DISPC_REG(0x0620)
80c39712 65#define DISPC_CAPABLE DISPC_REG(0x0048)
8613b000
SS		 66#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
67 (ch == 1 ? 0x0050 : 0x03AC))
68#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
69 (ch == 1 ? 0x0058 : 0x03B0))
80c39712
TV		 70#define DISPC_LINE_STATUS DISPC_REG(0x005C)
71#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
8613b000
SS		 72#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
73#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
74#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
75#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
80c39712
TV		 76#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
77#define DISPC_SIZE_DIG DISPC_REG(0x0078)
8613b000 78#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
80c39712
TV		 79
80/* DISPC GFX plane */
81#define DISPC_GFX_BA0 DISPC_REG(0x0080)
82#define DISPC_GFX_BA1 DISPC_REG(0x0084)
83#define DISPC_GFX_POSITION DISPC_REG(0x0088)
84#define DISPC_GFX_SIZE DISPC_REG(0x008C)
85#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
86#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
87#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
88#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
89#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
90#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
91#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
92
8613b000
SS		 93#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
94#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
95#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
96#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
97#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
98#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
80c39712
TV		 99
100#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
101
102/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
103#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
104
105#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
106#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
107#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
108#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
109#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
110#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
111#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
112#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
113#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
114#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
115#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
116#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
117#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
118
119/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
120#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
121/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
123/* coef index i = {0, 1, 2, 3, 4} */
124#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
125/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
126#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
127
128#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
129
130
131#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
132 DISPC_IRQ_OCP_ERR | \
133 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
134 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
135 DISPC_IRQ_SYNC_LOST | \
136 DISPC_IRQ_SYNC_LOST_DIGIT)
137
138#define DISPC_MAX_NR_ISRS 8
139
140struct omap_dispc_isr_data {
141 omap_dispc_isr_t isr;
142 void *arg;
143 u32 mask;
144};
145
66be8f6c
GI		 146struct dispc_h_coef {
147 s8 hc4;
148 s8 hc3;
149 u8 hc2;
150 s8 hc1;
151 s8 hc0;
152};
153
154struct dispc_v_coef {
155 s8 vc22;
156 s8 vc2;
157 u8 vc1;
158 s8 vc0;
159 s8 vc00;
160};
161
80c39712
TV		 162#define REG_GET(idx, start, end) \
163 FLD_GET(dispc_read_reg(idx), start, end)
164
165#define REG_FLD_MOD(idx, val, start, end) \
166 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
167
168static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
169 DISPC_VID_ATTRIBUTES(0),
170 DISPC_VID_ATTRIBUTES(1) };
171
dfc0fd8d
TV		 172struct dispc_irq_stats {
173 unsigned long last_reset;
174 unsigned irq_count;
175 unsigned irqs[32];
176};
177
80c39712 178static struct {
060b6d9c 179 struct platform_device *pdev;
80c39712
TV		 180 void __iomem *base;
181
182 u32 fifo_size[3];
183
184 spinlock_t irq_lock;
185 u32 irq_error_mask;
186 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
187 u32 error_irqs;
188 struct work_struct error_work;
189
190 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 191
192#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
193 spinlock_t irq_stats_lock;
194 struct dispc_irq_stats irq_stats;
195#endif
80c39712
TV		 196} dispc;
197
198static void _omap_dispc_set_irqs(void);
199
200static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
201{
202 __raw_writel(val, dispc.base + idx.idx);
203}
204
205static inline u32 dispc_read_reg(const struct dispc_reg idx)
206{
207 return __raw_readl(dispc.base + idx.idx);
208}
209
210#define SR(reg) \
211 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
212#define RR(reg) \
213 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
214
215void dispc_save_context(void)
216{
217 if (cpu_is_omap24xx())
218 return;
219
220 SR(SYSCONFIG);
221 SR(IRQENABLE);
222 SR(CONTROL);
223 SR(CONFIG);
8613b000
SS		 224 SR(DEFAULT_COLOR(0));
225 SR(DEFAULT_COLOR(1));
226 SR(TRANS_COLOR(0));
227 SR(TRANS_COLOR(1));
80c39712 228 SR(LINE_NUMBER);
8613b000
SS		 229 SR(TIMING_H(0));
230 SR(TIMING_V(0));
231 SR(POL_FREQ(0));
232 SR(DIVISOR(0));
80c39712
TV		 233 SR(GLOBAL_ALPHA);
234 SR(SIZE_DIG);
8613b000 235 SR(SIZE_LCD(0));
2a205f34
SS		 236 if (dss_has_feature(FEAT_MGR_LCD2)) {
237 SR(CONTROL2);
238 SR(DEFAULT_COLOR(2));
239 SR(TRANS_COLOR(2));
240 SR(SIZE_LCD(2));
241 SR(TIMING_H(2));
242 SR(TIMING_V(2));
243 SR(POL_FREQ(2));
244 SR(DIVISOR(2));
245 SR(CONFIG2);
246 }
80c39712
TV		 247
248 SR(GFX_BA0);
249 SR(GFX_BA1);
250 SR(GFX_POSITION);
251 SR(GFX_SIZE);
252 SR(GFX_ATTRIBUTES);
253 SR(GFX_FIFO_THRESHOLD);
254 SR(GFX_ROW_INC);
255 SR(GFX_PIXEL_INC);
256 SR(GFX_WINDOW_SKIP);
257 SR(GFX_TABLE_BA);
258
8613b000
SS		 259 SR(DATA_CYCLE1(0));
260 SR(DATA_CYCLE2(0));
261 SR(DATA_CYCLE3(0));
80c39712 262
8613b000
SS		 263 SR(CPR_COEF_R(0));
264 SR(CPR_COEF_G(0));
265 SR(CPR_COEF_B(0));
2a205f34
SS		 266 if (dss_has_feature(FEAT_MGR_LCD2)) {
267 SR(CPR_COEF_B(2));
268 SR(CPR_COEF_G(2));
269 SR(CPR_COEF_R(2));
270
271 SR(DATA_CYCLE1(2));
272 SR(DATA_CYCLE2(2));
273 SR(DATA_CYCLE3(2));
274 }
80c39712
TV		 275
276 SR(GFX_PRELOAD);
277
278 /* VID1 */
279 SR(VID_BA0(0));
280 SR(VID_BA1(0));
281 SR(VID_POSITION(0));
282 SR(VID_SIZE(0));
283 SR(VID_ATTRIBUTES(0));
284 SR(VID_FIFO_THRESHOLD(0));
285 SR(VID_ROW_INC(0));
286 SR(VID_PIXEL_INC(0));
287 SR(VID_FIR(0));
288 SR(VID_PICTURE_SIZE(0));
289 SR(VID_ACCU0(0));
290 SR(VID_ACCU1(0));
291
292 SR(VID_FIR_COEF_H(0, 0));
293 SR(VID_FIR_COEF_H(0, 1));
294 SR(VID_FIR_COEF_H(0, 2));
295 SR(VID_FIR_COEF_H(0, 3));
296 SR(VID_FIR_COEF_H(0, 4));
297 SR(VID_FIR_COEF_H(0, 5));
298 SR(VID_FIR_COEF_H(0, 6));
299 SR(VID_FIR_COEF_H(0, 7));
300
301 SR(VID_FIR_COEF_HV(0, 0));
302 SR(VID_FIR_COEF_HV(0, 1));
303 SR(VID_FIR_COEF_HV(0, 2));
304 SR(VID_FIR_COEF_HV(0, 3));
305 SR(VID_FIR_COEF_HV(0, 4));
306 SR(VID_FIR_COEF_HV(0, 5));
307 SR(VID_FIR_COEF_HV(0, 6));
308 SR(VID_FIR_COEF_HV(0, 7));
309
310 SR(VID_CONV_COEF(0, 0));
311 SR(VID_CONV_COEF(0, 1));
312 SR(VID_CONV_COEF(0, 2));
313 SR(VID_CONV_COEF(0, 3));
314 SR(VID_CONV_COEF(0, 4));
315
316 SR(VID_FIR_COEF_V(0, 0));
317 SR(VID_FIR_COEF_V(0, 1));
318 SR(VID_FIR_COEF_V(0, 2));
319 SR(VID_FIR_COEF_V(0, 3));
320 SR(VID_FIR_COEF_V(0, 4));
321 SR(VID_FIR_COEF_V(0, 5));
322 SR(VID_FIR_COEF_V(0, 6));
323 SR(VID_FIR_COEF_V(0, 7));
324
325 SR(VID_PRELOAD(0));
326
327 /* VID2 */
328 SR(VID_BA0(1));
329 SR(VID_BA1(1));
330 SR(VID_POSITION(1));
331 SR(VID_SIZE(1));
332 SR(VID_ATTRIBUTES(1));
333 SR(VID_FIFO_THRESHOLD(1));
334 SR(VID_ROW_INC(1));
335 SR(VID_PIXEL_INC(1));
336 SR(VID_FIR(1));
337 SR(VID_PICTURE_SIZE(1));
338 SR(VID_ACCU0(1));
339 SR(VID_ACCU1(1));
340
341 SR(VID_FIR_COEF_H(1, 0));
342 SR(VID_FIR_COEF_H(1, 1));
343 SR(VID_FIR_COEF_H(1, 2));
344 SR(VID_FIR_COEF_H(1, 3));
345 SR(VID_FIR_COEF_H(1, 4));
346 SR(VID_FIR_COEF_H(1, 5));
347 SR(VID_FIR_COEF_H(1, 6));
348 SR(VID_FIR_COEF_H(1, 7));
349
350 SR(VID_FIR_COEF_HV(1, 0));
351 SR(VID_FIR_COEF_HV(1, 1));
352 SR(VID_FIR_COEF_HV(1, 2));
353 SR(VID_FIR_COEF_HV(1, 3));
354 SR(VID_FIR_COEF_HV(1, 4));
355 SR(VID_FIR_COEF_HV(1, 5));
356 SR(VID_FIR_COEF_HV(1, 6));
357 SR(VID_FIR_COEF_HV(1, 7));
358
359 SR(VID_CONV_COEF(1, 0));
360 SR(VID_CONV_COEF(1, 1));
361 SR(VID_CONV_COEF(1, 2));
362 SR(VID_CONV_COEF(1, 3));
363 SR(VID_CONV_COEF(1, 4));
364
365 SR(VID_FIR_COEF_V(1, 0));
366 SR(VID_FIR_COEF_V(1, 1));
367 SR(VID_FIR_COEF_V(1, 2));
368 SR(VID_FIR_COEF_V(1, 3));
369 SR(VID_FIR_COEF_V(1, 4));
370 SR(VID_FIR_COEF_V(1, 5));
371 SR(VID_FIR_COEF_V(1, 6));
372 SR(VID_FIR_COEF_V(1, 7));
373
374 SR(VID_PRELOAD(1));
375}
376
377void dispc_restore_context(void)
378{
379 RR(SYSCONFIG);
75c7d59d 380 /*RR(IRQENABLE);*/
80c39712
TV		 381 /*RR(CONTROL);*/
382 RR(CONFIG);
8613b000
SS		 383 RR(DEFAULT_COLOR(0));
384 RR(DEFAULT_COLOR(1));
385 RR(TRANS_COLOR(0));
386 RR(TRANS_COLOR(1));
80c39712 387 RR(LINE_NUMBER);
8613b000
SS		 388 RR(TIMING_H(0));
389 RR(TIMING_V(0));
390 RR(POL_FREQ(0));
391 RR(DIVISOR(0));
80c39712
TV		 392 RR(GLOBAL_ALPHA);
393 RR(SIZE_DIG);
8613b000 394 RR(SIZE_LCD(0));
2a205f34
SS		 395 if (dss_has_feature(FEAT_MGR_LCD2)) {
396 RR(DEFAULT_COLOR(2));
397 RR(TRANS_COLOR(2));
398 RR(SIZE_LCD(2));
399 RR(TIMING_H(2));
400 RR(TIMING_V(2));
401 RR(POL_FREQ(2));
402 RR(DIVISOR(2));
403 RR(CONFIG2);
404 }
80c39712
TV		 405
406 RR(GFX_BA0);
407 RR(GFX_BA1);
408 RR(GFX_POSITION);
409 RR(GFX_SIZE);
410 RR(GFX_ATTRIBUTES);
411 RR(GFX_FIFO_THRESHOLD);
412 RR(GFX_ROW_INC);
413 RR(GFX_PIXEL_INC);
414 RR(GFX_WINDOW_SKIP);
415 RR(GFX_TABLE_BA);
416
8613b000
SS		 417 RR(DATA_CYCLE1(0));
418 RR(DATA_CYCLE2(0));
419 RR(DATA_CYCLE3(0));
80c39712 420
8613b000
SS		 421 RR(CPR_COEF_R(0));
422 RR(CPR_COEF_G(0));
423 RR(CPR_COEF_B(0));
2a205f34
SS		 424 if (dss_has_feature(FEAT_MGR_LCD2)) {
425 RR(DATA_CYCLE1(2));
426 RR(DATA_CYCLE2(2));
427 RR(DATA_CYCLE3(2));
428
429 RR(CPR_COEF_B(2));
430 RR(CPR_COEF_G(2));
431 RR(CPR_COEF_R(2));
432 }
80c39712
TV		 433
434 RR(GFX_PRELOAD);
435
436 /* VID1 */
437 RR(VID_BA0(0));
438 RR(VID_BA1(0));
439 RR(VID_POSITION(0));
440 RR(VID_SIZE(0));
441 RR(VID_ATTRIBUTES(0));
442 RR(VID_FIFO_THRESHOLD(0));
443 RR(VID_ROW_INC(0));
444 RR(VID_PIXEL_INC(0));
445 RR(VID_FIR(0));
446 RR(VID_PICTURE_SIZE(0));
447 RR(VID_ACCU0(0));
448 RR(VID_ACCU1(0));
449
450 RR(VID_FIR_COEF_H(0, 0));
451 RR(VID_FIR_COEF_H(0, 1));
452 RR(VID_FIR_COEF_H(0, 2));
453 RR(VID_FIR_COEF_H(0, 3));
454 RR(VID_FIR_COEF_H(0, 4));
455 RR(VID_FIR_COEF_H(0, 5));
456 RR(VID_FIR_COEF_H(0, 6));
457 RR(VID_FIR_COEF_H(0, 7));
458
459 RR(VID_FIR_COEF_HV(0, 0));
460 RR(VID_FIR_COEF_HV(0, 1));
461 RR(VID_FIR_COEF_HV(0, 2));
462 RR(VID_FIR_COEF_HV(0, 3));
463 RR(VID_FIR_COEF_HV(0, 4));
464 RR(VID_FIR_COEF_HV(0, 5));
465 RR(VID_FIR_COEF_HV(0, 6));
466 RR(VID_FIR_COEF_HV(0, 7));
467
468 RR(VID_CONV_COEF(0, 0));
469 RR(VID_CONV_COEF(0, 1));
470 RR(VID_CONV_COEF(0, 2));
471 RR(VID_CONV_COEF(0, 3));
472 RR(VID_CONV_COEF(0, 4));
473
474 RR(VID_FIR_COEF_V(0, 0));
475 RR(VID_FIR_COEF_V(0, 1));
476 RR(VID_FIR_COEF_V(0, 2));
477 RR(VID_FIR_COEF_V(0, 3));
478 RR(VID_FIR_COEF_V(0, 4));
479 RR(VID_FIR_COEF_V(0, 5));
480 RR(VID_FIR_COEF_V(0, 6));
481 RR(VID_FIR_COEF_V(0, 7));
482
483 RR(VID_PRELOAD(0));
484
485 /* VID2 */
486 RR(VID_BA0(1));
487 RR(VID_BA1(1));
488 RR(VID_POSITION(1));
489 RR(VID_SIZE(1));
490 RR(VID_ATTRIBUTES(1));
491 RR(VID_FIFO_THRESHOLD(1));
492 RR(VID_ROW_INC(1));
493 RR(VID_PIXEL_INC(1));
494 RR(VID_FIR(1));
495 RR(VID_PICTURE_SIZE(1));
496 RR(VID_ACCU0(1));
497 RR(VID_ACCU1(1));
498
499 RR(VID_FIR_COEF_H(1, 0));
500 RR(VID_FIR_COEF_H(1, 1));
501 RR(VID_FIR_COEF_H(1, 2));
502 RR(VID_FIR_COEF_H(1, 3));
503 RR(VID_FIR_COEF_H(1, 4));
504 RR(VID_FIR_COEF_H(1, 5));
505 RR(VID_FIR_COEF_H(1, 6));
506 RR(VID_FIR_COEF_H(1, 7));
507
508 RR(VID_FIR_COEF_HV(1, 0));
509 RR(VID_FIR_COEF_HV(1, 1));
510 RR(VID_FIR_COEF_HV(1, 2));
511 RR(VID_FIR_COEF_HV(1, 3));
512 RR(VID_FIR_COEF_HV(1, 4));
513 RR(VID_FIR_COEF_HV(1, 5));
514 RR(VID_FIR_COEF_HV(1, 6));
515 RR(VID_FIR_COEF_HV(1, 7));
516
517 RR(VID_CONV_COEF(1, 0));
518 RR(VID_CONV_COEF(1, 1));
519 RR(VID_CONV_COEF(1, 2));
520 RR(VID_CONV_COEF(1, 3));
521 RR(VID_CONV_COEF(1, 4));
522
523 RR(VID_FIR_COEF_V(1, 0));
524 RR(VID_FIR_COEF_V(1, 1));
525 RR(VID_FIR_COEF_V(1, 2));
526 RR(VID_FIR_COEF_V(1, 3));
527 RR(VID_FIR_COEF_V(1, 4));
528 RR(VID_FIR_COEF_V(1, 5));
529 RR(VID_FIR_COEF_V(1, 6));
530 RR(VID_FIR_COEF_V(1, 7));
531
532 RR(VID_PRELOAD(1));
533
534 /* enable last, because LCD & DIGIT enable are here */
535 RR(CONTROL);
2a205f34
SS		 536 if (dss_has_feature(FEAT_MGR_LCD2))
537 RR(CONTROL2);
75c7d59d
VS		 538 /* clear spurious SYNC_LOST_DIGIT interrupts */
539 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
540
541 /*
542 * enable last so IRQs won't trigger before
543 * the context is fully restored
544 */
545 RR(IRQENABLE);
80c39712
TV		 546}
547
548#undef SR
549#undef RR
550
551static inline void enable_clocks(bool enable)
552{
553 if (enable)
6af9cd14 554 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712 555 else
6af9cd14 556 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 557}
558
559bool dispc_go_busy(enum omap_channel channel)
560{
561 int bit;
562
2a205f34
SS		 563 if (channel == OMAP_DSS_CHANNEL_LCD ||
564 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 565 bit = 5; /* GOLCD */
566 else
567 bit = 6; /* GODIGIT */
568
2a205f34
SS		 569 if (channel == OMAP_DSS_CHANNEL_LCD2)
570 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
571 else
572 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 573}
574
575void dispc_go(enum omap_channel channel)
576{
577 int bit;
2a205f34 578 bool enable_bit, go_bit;
80c39712
TV		 579
580 enable_clocks(1);
581
2a205f34
SS		 582 if (channel == OMAP_DSS_CHANNEL_LCD ||
583 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 584 bit = 0; /* LCDENABLE */
585 else
586 bit = 1; /* DIGITALENABLE */
587
588 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 589 if (channel == OMAP_DSS_CHANNEL_LCD2)
590 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
591 else
592 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
593
594 if (!enable_bit)
80c39712
TV		 595 goto end;
596
2a205f34
SS		 597 if (channel == OMAP_DSS_CHANNEL_LCD ||
598 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 599 bit = 5; /* GOLCD */
600 else
601 bit = 6; /* GODIGIT */
602
2a205f34
SS		 603 if (channel == OMAP_DSS_CHANNEL_LCD2)
604 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
605 else
606 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
607
608 if (go_bit) {
80c39712
TV		 609 DSSERR("GO bit not down for channel %d\n", channel);
610 goto end;
611 }
612
2a205f34
SS		 613 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
614 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 615
2a205f34
SS		 616 if (channel == OMAP_DSS_CHANNEL_LCD2)
617 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
618 else
619 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 620end:
621 enable_clocks(0);
622}
623
624static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
625{
626 BUG_ON(plane == OMAP_DSS_GFX);
627
628 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
629}
630
631static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
632{
633 BUG_ON(plane == OMAP_DSS_GFX);
634
635 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
636}
637
638static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
639{
640 BUG_ON(plane == OMAP_DSS_GFX);
641
642 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
643}
644
645static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
646 int vscaleup, int five_taps)
647{
648 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 649 static const struct dispc_h_coef coef_hup[8] = {
650 { 0, 0, 128, 0, 0 },
651 { -1, 13, 124, -8, 0 },
652 { -2, 30, 112, -11, -1 },
653 { -5, 51, 95, -11, -2 },
654 { 0, -9, 73, 73, -9 },
655 { -2, -11, 95, 51, -5 },
656 { -1, -11, 112, 30, -2 },
657 { 0, -8, 124, 13, -1 },
80c39712
TV		 658 };
659
66be8f6c
GI		 660 /* Coefficients for vertical up-sampling */
661 static const struct dispc_v_coef coef_vup_3tap[8] = {
662 { 0, 0, 128, 0, 0 },
663 { 0, 3, 123, 2, 0 },
664 { 0, 12, 111, 5, 0 },
665 { 0, 32, 89, 7, 0 },
666 { 0, 0, 64, 64, 0 },
667 { 0, 7, 89, 32, 0 },
668 { 0, 5, 111, 12, 0 },
669 { 0, 2, 123, 3, 0 },
80c39712
TV		 670 };
671
66be8f6c
GI		 672 static const struct dispc_v_coef coef_vup_5tap[8] = {
673 { 0, 0, 128, 0, 0 },
674 { -1, 13, 124, -8, 0 },
675 { -2, 30, 112, -11, -1 },
676 { -5, 51, 95, -11, -2 },
677 { 0, -9, 73, 73, -9 },
678 { -2, -11, 95, 51, -5 },
679 { -1, -11, 112, 30, -2 },
680 { 0, -8, 124, 13, -1 },
80c39712
TV		 681 };
682
66be8f6c
GI		 683 /* Coefficients for horizontal down-sampling */
684 static const struct dispc_h_coef coef_hdown[8] = {
685 { 0, 36, 56, 36, 0 },
686 { 4, 40, 55, 31, -2 },
687 { 8, 44, 54, 27, -5 },
688 { 12, 48, 53, 22, -7 },
689 { -9, 17, 52, 51, 17 },
690 { -7, 22, 53, 48, 12 },
691 { -5, 27, 54, 44, 8 },
692 { -2, 31, 55, 40, 4 },
80c39712
TV		 693 };
694
66be8f6c
GI		 695 /* Coefficients for vertical down-sampling */
696 static const struct dispc_v_coef coef_vdown_3tap[8] = {
697 { 0, 36, 56, 36, 0 },
698 { 0, 40, 57, 31, 0 },
699 { 0, 45, 56, 27, 0 },
700 { 0, 50, 55, 23, 0 },
701 { 0, 18, 55, 55, 0 },
702 { 0, 23, 55, 50, 0 },
703 { 0, 27, 56, 45, 0 },
704 { 0, 31, 57, 40, 0 },
80c39712
TV		 705 };
706
66be8f6c
GI		 707 static const struct dispc_v_coef coef_vdown_5tap[8] = {
708 { 0, 36, 56, 36, 0 },
709 { 4, 40, 55, 31, -2 },
710 { 8, 44, 54, 27, -5 },
711 { 12, 48, 53, 22, -7 },
712 { -9, 17, 52, 51, 17 },
713 { -7, 22, 53, 48, 12 },
714 { -5, 27, 54, 44, 8 },
715 { -2, 31, 55, 40, 4 },
80c39712
TV		 716 };
717
66be8f6c
GI		 718 const struct dispc_h_coef *h_coef;
719 const struct dispc_v_coef *v_coef;
80c39712
TV		 720 int i;
721
722 if (hscaleup)
723 h_coef = coef_hup;
724 else
725 h_coef = coef_hdown;
726
66be8f6c
GI		 727 if (vscaleup)
728 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
729 else
730 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 731
732 for (i = 0; i < 8; i++) {
733 u32 h, hv;
734
66be8f6c
GI		 735 h = FLD_VAL(h_coef[i].hc0, 7, 0)
736 | FLD_VAL(h_coef[i].hc1, 15, 8)
737 | FLD_VAL(h_coef[i].hc2, 23, 16)
738 | FLD_VAL(h_coef[i].hc3, 31, 24);
739 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
740 | FLD_VAL(v_coef[i].vc0, 15, 8)
741 | FLD_VAL(v_coef[i].vc1, 23, 16)
742 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712
TV		 743
744 _dispc_write_firh_reg(plane, i, h);
745 _dispc_write_firhv_reg(plane, i, hv);
746 }
747
66be8f6c
GI		 748 if (five_taps) {
749 for (i = 0; i < 8; i++) {
750 u32 v;
751 v = FLD_VAL(v_coef[i].vc00, 7, 0)
752 | FLD_VAL(v_coef[i].vc22, 15, 8);
753 _dispc_write_firv_reg(plane, i, v);
754 }
80c39712
TV		 755 }
756}
757
758static void _dispc_setup_color_conv_coef(void)
759{
760 const struct color_conv_coef {
761 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
762 int full_range;
763 } ctbl_bt601_5 = {
764 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
765 };
766
767 const struct color_conv_coef *ct;
768
769#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
770
771 ct = &ctbl_bt601_5;
772
773 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
774 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
775 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
776 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
777 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
778
779 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
780 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
781 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
782 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
783 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
784
785#undef CVAL
786
787 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
788 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
789}
790
791
792static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
793{
794 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
795 DISPC_VID_BA0(0),
796 DISPC_VID_BA0(1) };
797
798 dispc_write_reg(ba0_reg[plane], paddr);
799}
800
801static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
802{
803 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
804 DISPC_VID_BA1(0),
805 DISPC_VID_BA1(1) };
806
807 dispc_write_reg(ba1_reg[plane], paddr);
808}
809
810static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
811{
812 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
813 DISPC_VID_POSITION(0),
814 DISPC_VID_POSITION(1) };
815
816 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
817 dispc_write_reg(pos_reg[plane], val);
818}
819
820static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
821{
822 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
823 DISPC_VID_PICTURE_SIZE(0),
824 DISPC_VID_PICTURE_SIZE(1) };
825 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
826 dispc_write_reg(siz_reg[plane], val);
827}
828
829static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
830{
831 u32 val;
832 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
833 DISPC_VID_SIZE(1) };
834
835 BUG_ON(plane == OMAP_DSS_GFX);
836
837 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
838 dispc_write_reg(vsi_reg[plane-1], val);
839}
840
fd28a390
R		 841static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
842{
843 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
844 return;
845
846 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
847 plane == OMAP_DSS_VIDEO1)
848 return;
849
850 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
851}
852
80c39712
TV		 853static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
854{
a0acb557 855 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 856 return;
857
fd28a390
R		 858 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
859 plane == OMAP_DSS_VIDEO1)
860 return;
a0acb557 861
80c39712
TV		 862 if (plane == OMAP_DSS_GFX)
863 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
864 else if (plane == OMAP_DSS_VIDEO2)
865 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
866}
867
868static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
869{
870 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
871 DISPC_VID_PIXEL_INC(0),
872 DISPC_VID_PIXEL_INC(1) };
873
874 dispc_write_reg(ri_reg[plane], inc);
875}
876
877static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
878{
879 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
880 DISPC_VID_ROW_INC(0),
881 DISPC_VID_ROW_INC(1) };
882
883 dispc_write_reg(ri_reg[plane], inc);
884}
885
886static void _dispc_set_color_mode(enum omap_plane plane,
887 enum omap_color_mode color_mode)
888{
889 u32 m = 0;
890
891 switch (color_mode) {
892 case OMAP_DSS_COLOR_CLUT1:
893 m = 0x0; break;
894 case OMAP_DSS_COLOR_CLUT2:
895 m = 0x1; break;
896 case OMAP_DSS_COLOR_CLUT4:
897 m = 0x2; break;
898 case OMAP_DSS_COLOR_CLUT8:
899 m = 0x3; break;
900 case OMAP_DSS_COLOR_RGB12U:
901 m = 0x4; break;
902 case OMAP_DSS_COLOR_ARGB16:
903 m = 0x5; break;
904 case OMAP_DSS_COLOR_RGB16:
905 m = 0x6; break;
906 case OMAP_DSS_COLOR_RGB24U:
907 m = 0x8; break;
908 case OMAP_DSS_COLOR_RGB24P:
909 m = 0x9; break;
910 case OMAP_DSS_COLOR_YUV2:
911 m = 0xa; break;
912 case OMAP_DSS_COLOR_UYVY:
913 m = 0xb; break;
914 case OMAP_DSS_COLOR_ARGB32:
915 m = 0xc; break;
916 case OMAP_DSS_COLOR_RGBA32:
917 m = 0xd; break;
918 case OMAP_DSS_COLOR_RGBX32:
919 m = 0xe; break;
920 default:
921 BUG(); break;
922 }
923
924 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
925}
926
927static void _dispc_set_channel_out(enum omap_plane plane,
928 enum omap_channel channel)
929{
930 int shift;
931 u32 val;
2a205f34 932 int chan = 0, chan2 = 0;
80c39712
TV		 933
934 switch (plane) {
935 case OMAP_DSS_GFX:
936 shift = 8;
937 break;
938 case OMAP_DSS_VIDEO1:
939 case OMAP_DSS_VIDEO2:
940 shift = 16;
941 break;
942 default:
943 BUG();
944 return;
945 }
946
947 val = dispc_read_reg(dispc_reg_att[plane]);
2a205f34
SS		 948 if (dss_has_feature(FEAT_MGR_LCD2)) {
949 switch (channel) {
950 case OMAP_DSS_CHANNEL_LCD:
951 chan = 0;
952 chan2 = 0;
953 break;
954 case OMAP_DSS_CHANNEL_DIGIT:
955 chan = 1;
956 chan2 = 0;
957 break;
958 case OMAP_DSS_CHANNEL_LCD2:
959 chan = 0;
960 chan2 = 1;
961 break;
962 default:
963 BUG();
964 }
965
966 val = FLD_MOD(val, chan, shift, shift);
967 val = FLD_MOD(val, chan2, 31, 30);
968 } else {
969 val = FLD_MOD(val, channel, shift, shift);
970 }
80c39712
TV		 971 dispc_write_reg(dispc_reg_att[plane], val);
972}
973
974void dispc_set_burst_size(enum omap_plane plane,
975 enum omap_burst_size burst_size)
976{
977 int shift;
978 u32 val;
979
980 enable_clocks(1);
981
982 switch (plane) {
983 case OMAP_DSS_GFX:
984 shift = 6;
985 break;
986 case OMAP_DSS_VIDEO1:
987 case OMAP_DSS_VIDEO2:
988 shift = 14;
989 break;
990 default:
991 BUG();
992 return;
993 }
994
995 val = dispc_read_reg(dispc_reg_att[plane]);
996 val = FLD_MOD(val, burst_size, shift+1, shift);
997 dispc_write_reg(dispc_reg_att[plane], val);
998
999 enable_clocks(0);
1000}
1001
1002static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1003{
1004 u32 val;
1005
1006 BUG_ON(plane == OMAP_DSS_GFX);
1007
1008 val = dispc_read_reg(dispc_reg_att[plane]);
1009 val = FLD_MOD(val, enable, 9, 9);
1010 dispc_write_reg(dispc_reg_att[plane], val);
1011}
1012
1013void dispc_enable_replication(enum omap_plane plane, bool enable)
1014{
1015 int bit;
1016
1017 if (plane == OMAP_DSS_GFX)
1018 bit = 5;
1019 else
1020 bit = 10;
1021
1022 enable_clocks(1);
1023 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1024 enable_clocks(0);
1025}
1026
64ba4f74 1027void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1028{
1029 u32 val;
1030 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1031 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1032 enable_clocks(1);
64ba4f74 1033 dispc_write_reg(DISPC_SIZE_LCD(channel), val);
80c39712
TV		 1034 enable_clocks(0);
1035}
1036
1037void dispc_set_digit_size(u16 width, u16 height)
1038{
1039 u32 val;
1040 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1041 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1042 enable_clocks(1);
1043 dispc_write_reg(DISPC_SIZE_DIG, val);
1044 enable_clocks(0);
1045}
1046
1047static void dispc_read_plane_fifo_sizes(void)
1048{
1049 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1050 DISPC_VID_FIFO_SIZE_STATUS(0),
1051 DISPC_VID_FIFO_SIZE_STATUS(1) };
1052 u32 size;
1053 int plane;
a0acb557 1054 u8 start, end;
80c39712
TV		 1055
1056 enable_clocks(1);
1057
a0acb557 1058 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1059
a0acb557
AT		 1060 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1061 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
80c39712
TV		 1062 dispc.fifo_size[plane] = size;
1063 }
1064
1065 enable_clocks(0);
1066}
1067
1068u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1069{
1070 return dispc.fifo_size[plane];
1071}
1072
1073void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1074{
1075 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1076 DISPC_VID_FIFO_THRESHOLD(0),
1077 DISPC_VID_FIFO_THRESHOLD(1) };
a0acb557
AT		 1078 u8 hi_start, hi_end, lo_start, lo_end;
1079
80c39712
TV		 1080 enable_clocks(1);
1081
1082 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1083 plane,
1084 REG_GET(ftrs_reg[plane], 11, 0),
1085 REG_GET(ftrs_reg[plane], 27, 16),
1086 low, high);
1087
a0acb557
AT		 1088 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1089 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1090
1091 dispc_write_reg(ftrs_reg[plane],
1092 FLD_VAL(high, hi_start, hi_end) |
1093 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1094
1095 enable_clocks(0);
1096}
1097
1098void dispc_enable_fifomerge(bool enable)
1099{
1100 enable_clocks(1);
1101
1102 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1103 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1104
1105 enable_clocks(0);
1106}
1107
1108static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1109{
1110 u32 val;
1111 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1112 DISPC_VID_FIR(1) };
a0acb557 1113 u8 hinc_start, hinc_end, vinc_start, vinc_end;
80c39712
TV		 1114
1115 BUG_ON(plane == OMAP_DSS_GFX);
1116
a0acb557
AT		 1117 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1118 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1119
1120 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1121 FLD_VAL(hinc, hinc_start, hinc_end);
1122
80c39712
TV		 1123 dispc_write_reg(fir_reg[plane-1], val);
1124}
1125
1126static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1127{
1128 u32 val;
1129 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1130 DISPC_VID_ACCU0(1) };
1131
1132 BUG_ON(plane == OMAP_DSS_GFX);
1133
1134 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1135 dispc_write_reg(ac0_reg[plane-1], val);
1136}
1137
1138static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1139{
1140 u32 val;
1141 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1142 DISPC_VID_ACCU1(1) };
1143
1144 BUG_ON(plane == OMAP_DSS_GFX);
1145
1146 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1147 dispc_write_reg(ac1_reg[plane-1], val);
1148}
1149
1150
1151static void _dispc_set_scaling(enum omap_plane plane,
1152 u16 orig_width, u16 orig_height,
1153 u16 out_width, u16 out_height,
1154 bool ilace, bool five_taps,
1155 bool fieldmode)
1156{
1157 int fir_hinc;
1158 int fir_vinc;
1159 int hscaleup, vscaleup;
1160 int accu0 = 0;
1161 int accu1 = 0;
1162 u32 l;
1163
1164 BUG_ON(plane == OMAP_DSS_GFX);
1165
1166 hscaleup = orig_width <= out_width;
1167 vscaleup = orig_height <= out_height;
1168
1169 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1170
1171 if (!orig_width || orig_width == out_width)
1172 fir_hinc = 0;
1173 else
1174 fir_hinc = 1024 * orig_width / out_width;
1175
1176 if (!orig_height || orig_height == out_height)
1177 fir_vinc = 0;
1178 else
1179 fir_vinc = 1024 * orig_height / out_height;
1180
1181 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1182
1183 l = dispc_read_reg(dispc_reg_att[plane]);
1184 l &= ~((0x0f << 5) | (0x3 << 21));
1185
1186 l |= fir_hinc ? (1 << 5) : 0;
1187 l |= fir_vinc ? (1 << 6) : 0;
1188
1189 l |= hscaleup ? 0 : (1 << 7);
1190 l |= vscaleup ? 0 : (1 << 8);
1191
1192 l |= five_taps ? (1 << 21) : 0;
1193 l |= five_taps ? (1 << 22) : 0;
1194
1195 dispc_write_reg(dispc_reg_att[plane], l);
1196
1197 /*
1198 * field 0 = even field = bottom field
1199 * field 1 = odd field = top field
1200 */
1201 if (ilace && !fieldmode) {
1202 accu1 = 0;
1203 accu0 = (fir_vinc / 2) & 0x3ff;
1204 if (accu0 >= 1024/2) {
1205 accu1 = 1024/2;
1206 accu0 -= accu1;
1207 }
1208 }
1209
1210 _dispc_set_vid_accu0(plane, 0, accu0);
1211 _dispc_set_vid_accu1(plane, 0, accu1);
1212}
1213
1214static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1215 bool mirroring, enum omap_color_mode color_mode)
1216{
1217 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1218 color_mode == OMAP_DSS_COLOR_UYVY) {
1219 int vidrot = 0;
1220
1221 if (mirroring) {
1222 switch (rotation) {
1223 case OMAP_DSS_ROT_0:
1224 vidrot = 2;
1225 break;
1226 case OMAP_DSS_ROT_90:
1227 vidrot = 1;
1228 break;
1229 case OMAP_DSS_ROT_180:
1230 vidrot = 0;
1231 break;
1232 case OMAP_DSS_ROT_270:
1233 vidrot = 3;
1234 break;
1235 }
1236 } else {
1237 switch (rotation) {
1238 case OMAP_DSS_ROT_0:
1239 vidrot = 0;
1240 break;
1241 case OMAP_DSS_ROT_90:
1242 vidrot = 1;
1243 break;
1244 case OMAP_DSS_ROT_180:
1245 vidrot = 2;
1246 break;
1247 case OMAP_DSS_ROT_270:
1248 vidrot = 3;
1249 break;
1250 }
1251 }
1252
1253 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1254
1255 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1256 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1257 else
1258 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1259 } else {
1260 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1261 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1262 }
1263}
1264
1265static int color_mode_to_bpp(enum omap_color_mode color_mode)
1266{
1267 switch (color_mode) {
1268 case OMAP_DSS_COLOR_CLUT1:
1269 return 1;
1270 case OMAP_DSS_COLOR_CLUT2:
1271 return 2;
1272 case OMAP_DSS_COLOR_CLUT4:
1273 return 4;
1274 case OMAP_DSS_COLOR_CLUT8:
1275 return 8;
1276 case OMAP_DSS_COLOR_RGB12U:
1277 case OMAP_DSS_COLOR_RGB16:
1278 case OMAP_DSS_COLOR_ARGB16:
1279 case OMAP_DSS_COLOR_YUV2:
1280 case OMAP_DSS_COLOR_UYVY:
1281 return 16;
1282 case OMAP_DSS_COLOR_RGB24P:
1283 return 24;
1284 case OMAP_DSS_COLOR_RGB24U:
1285 case OMAP_DSS_COLOR_ARGB32:
1286 case OMAP_DSS_COLOR_RGBA32:
1287 case OMAP_DSS_COLOR_RGBX32:
1288 return 32;
1289 default:
1290 BUG();
1291 }
1292}
1293
1294static s32 pixinc(int pixels, u8 ps)
1295{
1296 if (pixels == 1)
1297 return 1;
1298 else if (pixels > 1)
1299 return 1 + (pixels - 1) * ps;
1300 else if (pixels < 0)
1301 return 1 - (-pixels + 1) * ps;
1302 else
1303 BUG();
1304}
1305
1306static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1307 u16 screen_width,
1308 u16 width, u16 height,
1309 enum omap_color_mode color_mode, bool fieldmode,
1310 unsigned int field_offset,
1311 unsigned *offset0, unsigned *offset1,
1312 s32 *row_inc, s32 *pix_inc)
1313{
1314 u8 ps;
1315
1316 /* FIXME CLUT formats */
1317 switch (color_mode) {
1318 case OMAP_DSS_COLOR_CLUT1:
1319 case OMAP_DSS_COLOR_CLUT2:
1320 case OMAP_DSS_COLOR_CLUT4:
1321 case OMAP_DSS_COLOR_CLUT8:
1322 BUG();
1323 return;
1324 case OMAP_DSS_COLOR_YUV2:
1325 case OMAP_DSS_COLOR_UYVY:
1326 ps = 4;
1327 break;
1328 default:
1329 ps = color_mode_to_bpp(color_mode) / 8;
1330 break;
1331 }
1332
1333 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1334 width, height);
1335
1336 /*
1337 * field 0 = even field = bottom field
1338 * field 1 = odd field = top field
1339 */
1340 switch (rotation + mirror * 4) {
1341 case OMAP_DSS_ROT_0:
1342 case OMAP_DSS_ROT_180:
1343 /*
1344 * If the pixel format is YUV or UYVY divide the width
1345 * of the image by 2 for 0 and 180 degree rotation.
1346 */
1347 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1348 color_mode == OMAP_DSS_COLOR_UYVY)
1349 width = width >> 1;
1350 case OMAP_DSS_ROT_90:
1351 case OMAP_DSS_ROT_270:
1352 *offset1 = 0;
1353 if (field_offset)
1354 *offset0 = field_offset * screen_width * ps;
1355 else
1356 *offset0 = 0;
1357
1358 *row_inc = pixinc(1 + (screen_width - width) +
1359 (fieldmode ? screen_width : 0),
1360 ps);
1361 *pix_inc = pixinc(1, ps);
1362 break;
1363
1364 case OMAP_DSS_ROT_0 + 4:
1365 case OMAP_DSS_ROT_180 + 4:
1366 /* If the pixel format is YUV or UYVY divide the width
1367 * of the image by 2 for 0 degree and 180 degree
1368 */
1369 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1370 color_mode == OMAP_DSS_COLOR_UYVY)
1371 width = width >> 1;
1372 case OMAP_DSS_ROT_90 + 4:
1373 case OMAP_DSS_ROT_270 + 4:
1374 *offset1 = 0;
1375 if (field_offset)
1376 *offset0 = field_offset * screen_width * ps;
1377 else
1378 *offset0 = 0;
1379 *row_inc = pixinc(1 - (screen_width + width) -
1380 (fieldmode ? screen_width : 0),
1381 ps);
1382 *pix_inc = pixinc(1, ps);
1383 break;
1384
1385 default:
1386 BUG();
1387 }
1388}
1389
1390static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1391 u16 screen_width,
1392 u16 width, u16 height,
1393 enum omap_color_mode color_mode, bool fieldmode,
1394 unsigned int field_offset,
1395 unsigned *offset0, unsigned *offset1,
1396 s32 *row_inc, s32 *pix_inc)
1397{
1398 u8 ps;
1399 u16 fbw, fbh;
1400
1401 /* FIXME CLUT formats */
1402 switch (color_mode) {
1403 case OMAP_DSS_COLOR_CLUT1:
1404 case OMAP_DSS_COLOR_CLUT2:
1405 case OMAP_DSS_COLOR_CLUT4:
1406 case OMAP_DSS_COLOR_CLUT8:
1407 BUG();
1408 return;
1409 default:
1410 ps = color_mode_to_bpp(color_mode) / 8;
1411 break;
1412 }
1413
1414 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1415 width, height);
1416
1417 /* width & height are overlay sizes, convert to fb sizes */
1418
1419 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1420 fbw = width;
1421 fbh = height;
1422 } else {
1423 fbw = height;
1424 fbh = width;
1425 }
1426
1427 /*
1428 * field 0 = even field = bottom field
1429 * field 1 = odd field = top field
1430 */
1431 switch (rotation + mirror * 4) {
1432 case OMAP_DSS_ROT_0:
1433 *offset1 = 0;
1434 if (field_offset)
1435 *offset0 = *offset1 + field_offset * screen_width * ps;
1436 else
1437 *offset0 = *offset1;
1438 *row_inc = pixinc(1 + (screen_width - fbw) +
1439 (fieldmode ? screen_width : 0),
1440 ps);
1441 *pix_inc = pixinc(1, ps);
1442 break;
1443 case OMAP_DSS_ROT_90:
1444 *offset1 = screen_width * (fbh - 1) * ps;
1445 if (field_offset)
1446 *offset0 = *offset1 + field_offset * ps;
1447 else
1448 *offset0 = *offset1;
1449 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1450 (fieldmode ? 1 : 0), ps);
1451 *pix_inc = pixinc(-screen_width, ps);
1452 break;
1453 case OMAP_DSS_ROT_180:
1454 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1455 if (field_offset)
1456 *offset0 = *offset1 - field_offset * screen_width * ps;
1457 else
1458 *offset0 = *offset1;
1459 *row_inc = pixinc(-1 -
1460 (screen_width - fbw) -
1461 (fieldmode ? screen_width : 0),
1462 ps);
1463 *pix_inc = pixinc(-1, ps);
1464 break;
1465 case OMAP_DSS_ROT_270:
1466 *offset1 = (fbw - 1) * ps;
1467 if (field_offset)
1468 *offset0 = *offset1 - field_offset * ps;
1469 else
1470 *offset0 = *offset1;
1471 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1472 (fieldmode ? 1 : 0), ps);
1473 *pix_inc = pixinc(screen_width, ps);
1474 break;
1475
1476 /* mirroring */
1477 case OMAP_DSS_ROT_0 + 4:
1478 *offset1 = (fbw - 1) * ps;
1479 if (field_offset)
1480 *offset0 = *offset1 + field_offset * screen_width * ps;
1481 else
1482 *offset0 = *offset1;
1483 *row_inc = pixinc(screen_width * 2 - 1 +
1484 (fieldmode ? screen_width : 0),
1485 ps);
1486 *pix_inc = pixinc(-1, ps);
1487 break;
1488
1489 case OMAP_DSS_ROT_90 + 4:
1490 *offset1 = 0;
1491 if (field_offset)
1492 *offset0 = *offset1 + field_offset * ps;
1493 else
1494 *offset0 = *offset1;
1495 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1496 (fieldmode ? 1 : 0),
1497 ps);
1498 *pix_inc = pixinc(screen_width, ps);
1499 break;
1500
1501 case OMAP_DSS_ROT_180 + 4:
1502 *offset1 = screen_width * (fbh - 1) * ps;
1503 if (field_offset)
1504 *offset0 = *offset1 - field_offset * screen_width * ps;
1505 else
1506 *offset0 = *offset1;
1507 *row_inc = pixinc(1 - screen_width * 2 -
1508 (fieldmode ? screen_width : 0),
1509 ps);
1510 *pix_inc = pixinc(1, ps);
1511 break;
1512
1513 case OMAP_DSS_ROT_270 + 4:
1514 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1515 if (field_offset)
1516 *offset0 = *offset1 - field_offset * ps;
1517 else
1518 *offset0 = *offset1;
1519 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1520 (fieldmode ? 1 : 0),
1521 ps);
1522 *pix_inc = pixinc(-screen_width, ps);
1523 break;
1524
1525 default:
1526 BUG();
1527 }
1528}
1529
ff1b2cde
SS		 1530static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1531 u16 height, u16 out_width, u16 out_height,
1532 enum omap_color_mode color_mode)
80c39712
TV		 1533{
1534 u32 fclk = 0;
1535 /* FIXME venc pclk? */
ff1b2cde 1536 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1537
1538 if (height > out_height) {
1539 /* FIXME get real display PPL */
1540 unsigned int ppl = 800;
1541
1542 tmp = pclk * height * out_width;
1543 do_div(tmp, 2 * out_height * ppl);
1544 fclk = tmp;
1545
2d9c5597
VS		 1546 if (height > 2 * out_height) {
1547 if (ppl == out_width)
1548 return 0;
1549
80c39712
TV		 1550 tmp = pclk * (height - 2 * out_height) * out_width;
1551 do_div(tmp, 2 * out_height * (ppl - out_width));
1552 fclk = max(fclk, (u32) tmp);
1553 }
1554 }
1555
1556 if (width > out_width) {
1557 tmp = pclk * width;
1558 do_div(tmp, out_width);
1559 fclk = max(fclk, (u32) tmp);
1560
1561 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1562 fclk <<= 1;
1563 }
1564
1565 return fclk;
1566}
1567
ff1b2cde
SS		 1568static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1569 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1570{
1571 unsigned int hf, vf;
1572
1573 /*
1574 * FIXME how to determine the 'A' factor
1575 * for the no downscaling case ?
1576 */
1577
1578 if (width > 3 * out_width)
1579 hf = 4;
1580 else if (width > 2 * out_width)
1581 hf = 3;
1582 else if (width > out_width)
1583 hf = 2;
1584 else
1585 hf = 1;
1586
1587 if (height > out_height)
1588 vf = 2;
1589 else
1590 vf = 1;
1591
1592 /* FIXME venc pclk? */
ff1b2cde 1593 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1594}
1595
1596void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1597{
1598 enable_clocks(1);
1599 _dispc_set_channel_out(plane, channel_out);
1600 enable_clocks(0);
1601}
1602
1603static int _dispc_setup_plane(enum omap_plane plane,
1604 u32 paddr, u16 screen_width,
1605 u16 pos_x, u16 pos_y,
1606 u16 width, u16 height,
1607 u16 out_width, u16 out_height,
1608 enum omap_color_mode color_mode,
1609 bool ilace,
1610 enum omap_dss_rotation_type rotation_type,
1611 u8 rotation, int mirror,
18faa1b6
SS		 1612 u8 global_alpha, u8 pre_mult_alpha,
1613 enum omap_channel channel)
80c39712
TV		 1614{
1615 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1616 bool five_taps = 0;
1617 bool fieldmode = 0;
1618 int cconv = 0;
1619 unsigned offset0, offset1;
1620 s32 row_inc;
1621 s32 pix_inc;
1622 u16 frame_height = height;
1623 unsigned int field_offset = 0;
1624
1625 if (paddr == 0)
1626 return -EINVAL;
1627
1628 if (ilace && height == out_height)
1629 fieldmode = 1;
1630
1631 if (ilace) {
1632 if (fieldmode)
1633 height /= 2;
1634 pos_y /= 2;
1635 out_height /= 2;
1636
1637 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1638 "out_height %d\n",
1639 height, pos_y, out_height);
1640 }
1641
8dad2ab6
AT		 1642 if (!dss_feat_color_mode_supported(plane, color_mode))
1643 return -EINVAL;
1644
80c39712
TV		 1645 if (plane == OMAP_DSS_GFX) {
1646 if (width != out_width || height != out_height)
1647 return -EINVAL;
80c39712
TV		 1648 } else {
1649 /* video plane */
1650
1651 unsigned long fclk = 0;
1652
1653 if (out_width < width / maxdownscale ||
1654 out_width > width * 8)
1655 return -EINVAL;
1656
1657 if (out_height < height / maxdownscale ||
1658 out_height > height * 8)
1659 return -EINVAL;
1660
8dad2ab6
AT		 1661 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1662 color_mode == OMAP_DSS_COLOR_UYVY)
80c39712 1663 cconv = 1;
80c39712
TV		 1664
1665 /* Must use 5-tap filter? */
1666 five_taps = height > out_height * 2;
1667
1668 if (!five_taps) {
18faa1b6
SS		 1669 fclk = calc_fclk(channel, width, height, out_width,
1670 out_height);
80c39712
TV		 1671
1672 /* Try 5-tap filter if 3-tap fclk is too high */
1673 if (cpu_is_omap34xx() && height > out_height &&
1674 fclk > dispc_fclk_rate())
1675 five_taps = true;
1676 }
1677
1678 if (width > (2048 >> five_taps)) {
1679 DSSERR("failed to set up scaling, fclk too low\n");
1680 return -EINVAL;
1681 }
1682
1683 if (five_taps)
18faa1b6
SS		 1684 fclk = calc_fclk_five_taps(channel, width, height,
1685 out_width, out_height, color_mode);
80c39712
TV		 1686
1687 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1688 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1689
2d9c5597 1690 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1691 DSSERR("failed to set up scaling, "
1692 "required fclk rate = %lu Hz, "
1693 "current fclk rate = %lu Hz\n",
1694 fclk, dispc_fclk_rate());
1695 return -EINVAL;
1696 }
1697 }
1698
1699 if (ilace && !fieldmode) {
1700 /*
1701 * when downscaling the bottom field may have to start several
1702 * source lines below the top field. Unfortunately ACCUI
1703 * registers will only hold the fractional part of the offset
1704 * so the integer part must be added to the base address of the
1705 * bottom field.
1706 */
1707 if (!height || height == out_height)
1708 field_offset = 0;
1709 else
1710 field_offset = height / out_height / 2;
1711 }
1712
1713 /* Fields are independent but interleaved in memory. */
1714 if (fieldmode)
1715 field_offset = 1;
1716
1717 if (rotation_type == OMAP_DSS_ROT_DMA)
1718 calc_dma_rotation_offset(rotation, mirror,
1719 screen_width, width, frame_height, color_mode,
1720 fieldmode, field_offset,
1721 &offset0, &offset1, &row_inc, &pix_inc);
1722 else
1723 calc_vrfb_rotation_offset(rotation, mirror,
1724 screen_width, width, frame_height, color_mode,
1725 fieldmode, field_offset,
1726 &offset0, &offset1, &row_inc, &pix_inc);
1727
1728 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1729 offset0, offset1, row_inc, pix_inc);
1730
1731 _dispc_set_color_mode(plane, color_mode);
1732
1733 _dispc_set_plane_ba0(plane, paddr + offset0);
1734 _dispc_set_plane_ba1(plane, paddr + offset1);
1735
1736 _dispc_set_row_inc(plane, row_inc);
1737 _dispc_set_pix_inc(plane, pix_inc);
1738
1739 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1740 out_width, out_height);
1741
1742 _dispc_set_plane_pos(plane, pos_x, pos_y);
1743
1744 _dispc_set_pic_size(plane, width, height);
1745
1746 if (plane != OMAP_DSS_GFX) {
1747 _dispc_set_scaling(plane, width, height,
1748 out_width, out_height,
1749 ilace, five_taps, fieldmode);
1750 _dispc_set_vid_size(plane, out_width, out_height);
1751 _dispc_set_vid_color_conv(plane, cconv);
1752 }
1753
1754 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1755
fd28a390
R		 1756 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1757 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1758
1759 return 0;
1760}
1761
1762static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1763{
1764 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1765}
1766
1767static void dispc_disable_isr(void *data, u32 mask)
1768{
1769 struct completion *compl = data;
1770 complete(compl);
1771}
1772
2a205f34 1773static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1774{
2a205f34
SS		 1775 if (channel == OMAP_DSS_CHANNEL_LCD2)
1776 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1777 else
1778 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1779}
1780
2a205f34 1781static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1782{
1783 struct completion frame_done_completion;
1784 bool is_on;
1785 int r;
2a205f34 1786 u32 irq;
80c39712
TV		 1787
1788 enable_clocks(1);
1789
1790 /* When we disable LCD output, we need to wait until frame is done.
1791 * Otherwise the DSS is still working, and turning off the clocks
1792 * prevents DSS from going to OFF mode */
2a205f34
SS		 1793 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1794 REG_GET(DISPC_CONTROL2, 0, 0) :
1795 REG_GET(DISPC_CONTROL, 0, 0);
1796
1797 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1798 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1799
1800 if (!enable && is_on) {
1801 init_completion(&frame_done_completion);
1802
1803 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1804 &frame_done_completion, irq);
80c39712
TV		 1805
1806 if (r)
1807 DSSERR("failed to register FRAMEDONE isr\n");
1808 }
1809
2a205f34 1810 _enable_lcd_out(channel, enable);
80c39712
TV		 1811
1812 if (!enable && is_on) {
1813 if (!wait_for_completion_timeout(&frame_done_completion,
1814 msecs_to_jiffies(100)))
1815 DSSERR("timeout waiting for FRAME DONE\n");
1816
1817 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1818 &frame_done_completion, irq);
80c39712
TV		 1819
1820 if (r)
1821 DSSERR("failed to unregister FRAMEDONE isr\n");
1822 }
1823
1824 enable_clocks(0);
1825}
1826
1827static void _enable_digit_out(bool enable)
1828{
1829 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1830}
1831
a2faee84 1832static void dispc_enable_digit_out(bool enable)
80c39712
TV		 1833{
1834 struct completion frame_done_completion;
1835 int r;
1836
1837 enable_clocks(1);
1838
1839 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1840 enable_clocks(0);
1841 return;
1842 }
1843
1844 if (enable) {
1845 unsigned long flags;
1846 /* When we enable digit output, we'll get an extra digit
1847 * sync lost interrupt, that we need to ignore */
1848 spin_lock_irqsave(&dispc.irq_lock, flags);
1849 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1850 _omap_dispc_set_irqs();
1851 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1852 }
1853
1854 /* When we disable digit output, we need to wait until fields are done.
1855 * Otherwise the DSS is still working, and turning off the clocks
1856 * prevents DSS from going to OFF mode. And when enabling, we need to
1857 * wait for the extra sync losts */
1858 init_completion(&frame_done_completion);
1859
1860 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1861 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1862 if (r)
1863 DSSERR("failed to register EVSYNC isr\n");
1864
1865 _enable_digit_out(enable);
1866
1867 /* XXX I understand from TRM that we should only wait for the
1868 * current field to complete. But it seems we have to wait
1869 * for both fields */
1870 if (!wait_for_completion_timeout(&frame_done_completion,
1871 msecs_to_jiffies(100)))
1872 DSSERR("timeout waiting for EVSYNC\n");
1873
1874 if (!wait_for_completion_timeout(&frame_done_completion,
1875 msecs_to_jiffies(100)))
1876 DSSERR("timeout waiting for EVSYNC\n");
1877
1878 r = omap_dispc_unregister_isr(dispc_disable_isr,
1879 &frame_done_completion,
1880 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1881 if (r)
1882 DSSERR("failed to unregister EVSYNC isr\n");
1883
1884 if (enable) {
1885 unsigned long flags;
1886 spin_lock_irqsave(&dispc.irq_lock, flags);
1887 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 1888 if (dss_has_feature(FEAT_MGR_LCD2))
1889 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 1890 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1891 _omap_dispc_set_irqs();
1892 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1893 }
1894
1895 enable_clocks(0);
1896}
1897
a2faee84
TV		 1898bool dispc_is_channel_enabled(enum omap_channel channel)
1899{
1900 if (channel == OMAP_DSS_CHANNEL_LCD)
1901 return !!REG_GET(DISPC_CONTROL, 0, 0);
1902 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1903 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 1904 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1905 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 1906 else
1907 BUG();
1908}
1909
1910void dispc_enable_channel(enum omap_channel channel, bool enable)
1911{
2a205f34
SS		 1912 if (channel == OMAP_DSS_CHANNEL_LCD ||
1913 channel == OMAP_DSS_CHANNEL_LCD2)
1914 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 1915 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1916 dispc_enable_digit_out(enable);
1917 else
1918 BUG();
1919}
1920
80c39712
TV		 1921void dispc_lcd_enable_signal_polarity(bool act_high)
1922{
6ced40bf
AT		 1923 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1924 return;
1925
80c39712
TV		 1926 enable_clocks(1);
1927 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1928 enable_clocks(0);
1929}
1930
1931void dispc_lcd_enable_signal(bool enable)
1932{
6ced40bf
AT		 1933 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1934 return;
1935
80c39712
TV		 1936 enable_clocks(1);
1937 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1938 enable_clocks(0);
1939}
1940
1941void dispc_pck_free_enable(bool enable)
1942{
6ced40bf
AT		 1943 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1944 return;
1945
80c39712
TV		 1946 enable_clocks(1);
1947 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1948 enable_clocks(0);
1949}
1950
64ba4f74 1951void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712
TV		 1952{
1953 enable_clocks(1);
2a205f34
SS		 1954 if (channel == OMAP_DSS_CHANNEL_LCD2)
1955 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1956 else
1957 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 1958 enable_clocks(0);
1959}
1960
1961
64ba4f74
SS		 1962void dispc_set_lcd_display_type(enum omap_channel channel,
1963 enum omap_lcd_display_type type)
80c39712
TV		 1964{
1965 int mode;
1966
1967 switch (type) {
1968 case OMAP_DSS_LCD_DISPLAY_STN:
1969 mode = 0;
1970 break;
1971
1972 case OMAP_DSS_LCD_DISPLAY_TFT:
1973 mode = 1;
1974 break;
1975
1976 default:
1977 BUG();
1978 return;
1979 }
1980
1981 enable_clocks(1);
2a205f34
SS		 1982 if (channel == OMAP_DSS_CHANNEL_LCD2)
1983 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1984 else
1985 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 1986 enable_clocks(0);
1987}
1988
1989void dispc_set_loadmode(enum omap_dss_load_mode mode)
1990{
1991 enable_clocks(1);
1992 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1993 enable_clocks(0);
1994}
1995
1996
1997void dispc_set_default_color(enum omap_channel channel, u32 color)
1998{
80c39712 1999 enable_clocks(1);
8613b000 2000 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2001 enable_clocks(0);
2002}
2003
2004u32 dispc_get_default_color(enum omap_channel channel)
2005{
80c39712
TV		 2006 u32 l;
2007
2008 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2009 channel != OMAP_DSS_CHANNEL_LCD &&
2010 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712
TV		 2011
2012 enable_clocks(1);
8613b000 2013 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2014 enable_clocks(0);
2015
2016 return l;
2017}
2018
2019void dispc_set_trans_key(enum omap_channel ch,
2020 enum omap_dss_trans_key_type type,
2021 u32 trans_key)
2022{
80c39712
TV		 2023 enable_clocks(1);
2024 if (ch == OMAP_DSS_CHANNEL_LCD)
2025 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2026 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2027 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2028 else /* OMAP_DSS_CHANNEL_LCD2 */
2029 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2030
8613b000 2031 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2032 enable_clocks(0);
2033}
2034
2035void dispc_get_trans_key(enum omap_channel ch,
2036 enum omap_dss_trans_key_type *type,
2037 u32 *trans_key)
2038{
80c39712
TV		 2039 enable_clocks(1);
2040 if (type) {
2041 if (ch == OMAP_DSS_CHANNEL_LCD)
2042 *type = REG_GET(DISPC_CONFIG, 11, 11);
2043 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2044 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2045 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2046 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2047 else
2048 BUG();
2049 }
2050
2051 if (trans_key)
8613b000 2052 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2053 enable_clocks(0);
2054}
2055
2056void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2057{
2058 enable_clocks(1);
2059 if (ch == OMAP_DSS_CHANNEL_LCD)
2060 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2061 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2062 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2063 else /* OMAP_DSS_CHANNEL_LCD2 */
2064 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2065 enable_clocks(0);
2066}
2067void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2068{
a0acb557 2069 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2070 return;
2071
2072 enable_clocks(1);
2073 if (ch == OMAP_DSS_CHANNEL_LCD)
2074 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2075 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2076 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2077 else /* OMAP_DSS_CHANNEL_LCD2 */
2078 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2079 enable_clocks(0);
2080}
2081bool dispc_alpha_blending_enabled(enum omap_channel ch)
2082{
2083 bool enabled;
2084
a0acb557 2085 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2086 return false;
2087
2088 enable_clocks(1);
2089 if (ch == OMAP_DSS_CHANNEL_LCD)
2090 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2091 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2092 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2093 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2094 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2095 else
2096 BUG();
2097 enable_clocks(0);
2098
2099 return enabled;
80c39712
TV		 2100}
2101
2102
2103bool dispc_trans_key_enabled(enum omap_channel ch)
2104{
2105 bool enabled;
2106
2107 enable_clocks(1);
2108 if (ch == OMAP_DSS_CHANNEL_LCD)
2109 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2110 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2111 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2112 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2113 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2114 else
2115 BUG();
2116 enable_clocks(0);
2117
2118 return enabled;
2119}
2120
2121
64ba4f74 2122void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2123{
2124 int code;
2125
2126 switch (data_lines) {
2127 case 12:
2128 code = 0;
2129 break;
2130 case 16:
2131 code = 1;
2132 break;
2133 case 18:
2134 code = 2;
2135 break;
2136 case 24:
2137 code = 3;
2138 break;
2139 default:
2140 BUG();
2141 return;
2142 }
2143
2144 enable_clocks(1);
2a205f34
SS		 2145 if (channel == OMAP_DSS_CHANNEL_LCD2)
2146 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2147 else
2148 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2149 enable_clocks(0);
2150}
2151
64ba4f74
SS		 2152void dispc_set_parallel_interface_mode(enum omap_channel channel,
2153 enum omap_parallel_interface_mode mode)
80c39712
TV		 2154{
2155 u32 l;
2156 int stallmode;
2157 int gpout0 = 1;
2158 int gpout1;
2159
2160 switch (mode) {
2161 case OMAP_DSS_PARALLELMODE_BYPASS:
2162 stallmode = 0;
2163 gpout1 = 1;
2164 break;
2165
2166 case OMAP_DSS_PARALLELMODE_RFBI:
2167 stallmode = 1;
2168 gpout1 = 0;
2169 break;
2170
2171 case OMAP_DSS_PARALLELMODE_DSI:
2172 stallmode = 1;
2173 gpout1 = 1;
2174 break;
2175
2176 default:
2177 BUG();
2178 return;
2179 }
2180
2181 enable_clocks(1);
2182
2a205f34
SS		 2183 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2184 l = dispc_read_reg(DISPC_CONTROL2);
2185 l = FLD_MOD(l, stallmode, 11, 11);
2186 dispc_write_reg(DISPC_CONTROL2, l);
2187 } else {
2188 l = dispc_read_reg(DISPC_CONTROL);
2189 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2190 l = FLD_MOD(l, gpout0, 15, 15);
2191 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2192 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2193 }
80c39712
TV		 2194
2195 enable_clocks(0);
2196}
2197
2198static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2199 int vsw, int vfp, int vbp)
2200{
2201 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2202 if (hsw < 1 || hsw > 64 ||
2203 hfp < 1 || hfp > 256 ||
2204 hbp < 1 || hbp > 256 ||
2205 vsw < 1 || vsw > 64 ||
2206 vfp < 0 || vfp > 255 ||
2207 vbp < 0 || vbp > 255)
2208 return false;
2209 } else {
2210 if (hsw < 1 || hsw > 256 ||
2211 hfp < 1 || hfp > 4096 ||
2212 hbp < 1 || hbp > 4096 ||
2213 vsw < 1 || vsw > 256 ||
2214 vfp < 0 || vfp > 4095 ||
2215 vbp < 0 || vbp > 4095)
2216 return false;
2217 }
2218
2219 return true;
2220}
2221
2222bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2223{
2224 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2225 timings->hbp, timings->vsw,
2226 timings->vfp, timings->vbp);
2227}
2228
64ba4f74
SS		 2229static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2230 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2231{
2232 u32 timing_h, timing_v;
2233
2234 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2235 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2236 FLD_VAL(hbp-1, 27, 20);
2237
2238 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2239 FLD_VAL(vbp, 27, 20);
2240 } else {
2241 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2242 FLD_VAL(hbp-1, 31, 20);
2243
2244 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2245 FLD_VAL(vbp, 31, 20);
2246 }
2247
2248 enable_clocks(1);
64ba4f74
SS		 2249 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2250 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2251 enable_clocks(0);
2252}
2253
2254/* change name to mode? */
64ba4f74
SS		 2255void dispc_set_lcd_timings(enum omap_channel channel,
2256 struct omap_video_timings *timings)
80c39712
TV		 2257{
2258 unsigned xtot, ytot;
2259 unsigned long ht, vt;
2260
2261 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2262 timings->hbp, timings->vsw,
2263 timings->vfp, timings->vbp))
2264 BUG();
2265
64ba4f74
SS		 2266 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2267 timings->hbp, timings->vsw, timings->vfp,
2268 timings->vbp);
80c39712 2269
64ba4f74 2270 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2271
2272 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2273 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2274
2275 ht = (timings->pixel_clock * 1000) / xtot;
2276 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2277
2a205f34
SS		 2278 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2279 timings->y_res);
80c39712
TV		 2280 DSSDBG("pck %u\n", timings->pixel_clock);
2281 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2282 timings->hsw, timings->hfp, timings->hbp,
2283 timings->vsw, timings->vfp, timings->vbp);
2284
2285 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2286}
2287
ff1b2cde
SS		 2288static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2289 u16 pck_div)
80c39712
TV		 2290{
2291 BUG_ON(lck_div < 1);
2292 BUG_ON(pck_div < 2);
2293
2294 enable_clocks(1);
ff1b2cde 2295 dispc_write_reg(DISPC_DIVISOR(channel),
80c39712
TV		 2296 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2297 enable_clocks(0);
2298}
2299
2a205f34
SS		 2300static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2301 int *pck_div)
80c39712
TV		 2302{
2303 u32 l;
2a205f34 2304 l = dispc_read_reg(DISPC_DIVISOR(channel));
80c39712
TV		 2305 *lck_div = FLD_GET(l, 23, 16);
2306 *pck_div = FLD_GET(l, 7, 0);
2307}
2308
2309unsigned long dispc_fclk_rate(void)
2310{
2311 unsigned long r = 0;
2312
63cf28ac 2313 if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
6af9cd14 2314 r = dss_clk_get_rate(DSS_CLK_FCK);
80c39712
TV		 2315 else
2316#ifdef CONFIG_OMAP2_DSS_DSI
2317 r = dsi_get_dsi1_pll_rate();
2318#else
2319 BUG();
2320#endif
2321 return r;
2322}
2323
ff1b2cde 2324unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712
TV		 2325{
2326 int lcd;
2327 unsigned long r;
2328 u32 l;
2329
ff1b2cde 2330 l = dispc_read_reg(DISPC_DIVISOR(channel));
80c39712
TV		 2331
2332 lcd = FLD_GET(l, 23, 16);
2333
2334 r = dispc_fclk_rate();
2335
2336 return r / lcd;
2337}
2338
ff1b2cde 2339unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712
TV		 2340{
2341 int lcd, pcd;
2342 unsigned long r;
2343 u32 l;
2344
ff1b2cde 2345 l = dispc_read_reg(DISPC_DIVISOR(channel));
80c39712
TV		 2346
2347 lcd = FLD_GET(l, 23, 16);
2348 pcd = FLD_GET(l, 7, 0);
2349
2350 r = dispc_fclk_rate();
2351
2352 return r / lcd / pcd;
2353}
2354
2355void dispc_dump_clocks(struct seq_file *s)
2356{
2357 int lcd, pcd;
2358
2359 enable_clocks(1);
2360
80c39712
TV		 2361 seq_printf(s, "- DISPC -\n");
2362
2363 seq_printf(s, "dispc fclk source = %s\n",
63cf28ac 2364 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
80c39712
TV		 2365 "dss1_alwon_fclk" : "dsi1_pll_fclk");
2366
2367 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34
SS		 2368
2369 seq_printf(s, "- LCD1 -\n");
2370
2371 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2372
ff1b2cde
SS		 2373 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2374 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2375 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2376 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2377 if (dss_has_feature(FEAT_MGR_LCD2)) {
2378 seq_printf(s, "- LCD2 -\n");
2379
2380 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2381
2a205f34
SS		 2382 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2383 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2384 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2385 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2386 }
80c39712
TV		 2387 enable_clocks(0);
2388}
2389
dfc0fd8d
TV		 2390#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2391void dispc_dump_irqs(struct seq_file *s)
2392{
2393 unsigned long flags;
2394 struct dispc_irq_stats stats;
2395
2396 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2397
2398 stats = dispc.irq_stats;
2399 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2400 dispc.irq_stats.last_reset = jiffies;
2401
2402 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2403
2404 seq_printf(s, "period %u ms\n",
2405 jiffies_to_msecs(jiffies - stats.last_reset));
2406
2407 seq_printf(s, "irqs %d\n", stats.irq_count);
2408#define PIS(x) \
2409 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2410
2411 PIS(FRAMEDONE);
2412 PIS(VSYNC);
2413 PIS(EVSYNC_EVEN);
2414 PIS(EVSYNC_ODD);
2415 PIS(ACBIAS_COUNT_STAT);
2416 PIS(PROG_LINE_NUM);
2417 PIS(GFX_FIFO_UNDERFLOW);
2418 PIS(GFX_END_WIN);
2419 PIS(PAL_GAMMA_MASK);
2420 PIS(OCP_ERR);
2421 PIS(VID1_FIFO_UNDERFLOW);
2422 PIS(VID1_END_WIN);
2423 PIS(VID2_FIFO_UNDERFLOW);
2424 PIS(VID2_END_WIN);
2425 PIS(SYNC_LOST);
2426 PIS(SYNC_LOST_DIGIT);
2427 PIS(WAKEUP);
2a205f34
SS		 2428 if (dss_has_feature(FEAT_MGR_LCD2)) {
2429 PIS(FRAMEDONE2);
2430 PIS(VSYNC2);
2431 PIS(ACBIAS_COUNT_STAT2);
2432 PIS(SYNC_LOST2);
2433 }
dfc0fd8d
TV		 2434#undef PIS
2435}
dfc0fd8d
TV		 2436#endif
2437
80c39712
TV		 2438void dispc_dump_regs(struct seq_file *s)
2439{
2440#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2441
6af9cd14 2442 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2443
2444 DUMPREG(DISPC_REVISION);
2445 DUMPREG(DISPC_SYSCONFIG);
2446 DUMPREG(DISPC_SYSSTATUS);
2447 DUMPREG(DISPC_IRQSTATUS);
2448 DUMPREG(DISPC_IRQENABLE);
2449 DUMPREG(DISPC_CONTROL);
2450 DUMPREG(DISPC_CONFIG);
2451 DUMPREG(DISPC_CAPABLE);
8613b000
SS		 2452 DUMPREG(DISPC_DEFAULT_COLOR(0));
2453 DUMPREG(DISPC_DEFAULT_COLOR(1));
2454 DUMPREG(DISPC_TRANS_COLOR(0));
2455 DUMPREG(DISPC_TRANS_COLOR(1));
80c39712
TV		 2456 DUMPREG(DISPC_LINE_STATUS);
2457 DUMPREG(DISPC_LINE_NUMBER);
8613b000
SS		 2458 DUMPREG(DISPC_TIMING_H(0));
2459 DUMPREG(DISPC_TIMING_V(0));
2460 DUMPREG(DISPC_POL_FREQ(0));
2461 DUMPREG(DISPC_DIVISOR(0));
80c39712
TV		 2462 DUMPREG(DISPC_GLOBAL_ALPHA);
2463 DUMPREG(DISPC_SIZE_DIG);
8613b000 2464 DUMPREG(DISPC_SIZE_LCD(0));
2a205f34
SS		 2465 if (dss_has_feature(FEAT_MGR_LCD2)) {
2466 DUMPREG(DISPC_CONTROL2);
2467 DUMPREG(DISPC_CONFIG2);
2468 DUMPREG(DISPC_DEFAULT_COLOR(2));
2469 DUMPREG(DISPC_TRANS_COLOR(2));
2470 DUMPREG(DISPC_TIMING_H(2));
2471 DUMPREG(DISPC_TIMING_V(2));
2472 DUMPREG(DISPC_POL_FREQ(2));
2473 DUMPREG(DISPC_DIVISOR(2));
2474 DUMPREG(DISPC_SIZE_LCD(2));
2475 }
80c39712
TV		 2476
2477 DUMPREG(DISPC_GFX_BA0);
2478 DUMPREG(DISPC_GFX_BA1);
2479 DUMPREG(DISPC_GFX_POSITION);
2480 DUMPREG(DISPC_GFX_SIZE);
2481 DUMPREG(DISPC_GFX_ATTRIBUTES);
2482 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2483 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2484 DUMPREG(DISPC_GFX_ROW_INC);
2485 DUMPREG(DISPC_GFX_PIXEL_INC);
2486 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2487 DUMPREG(DISPC_GFX_TABLE_BA);
2488
8613b000
SS		 2489 DUMPREG(DISPC_DATA_CYCLE1(0));
2490 DUMPREG(DISPC_DATA_CYCLE2(0));
2491 DUMPREG(DISPC_DATA_CYCLE3(0));
80c39712 2492
8613b000
SS		 2493 DUMPREG(DISPC_CPR_COEF_R(0));
2494 DUMPREG(DISPC_CPR_COEF_G(0));
2495 DUMPREG(DISPC_CPR_COEF_B(0));
2a205f34
SS		 2496 if (dss_has_feature(FEAT_MGR_LCD2)) {
2497 DUMPREG(DISPC_DATA_CYCLE1(2));
2498 DUMPREG(DISPC_DATA_CYCLE2(2));
2499 DUMPREG(DISPC_DATA_CYCLE3(2));
2500
2501 DUMPREG(DISPC_CPR_COEF_R(2));
2502 DUMPREG(DISPC_CPR_COEF_G(2));
2503 DUMPREG(DISPC_CPR_COEF_B(2));
2504 }
80c39712
TV		 2505
2506 DUMPREG(DISPC_GFX_PRELOAD);
2507
2508 DUMPREG(DISPC_VID_BA0(0));
2509 DUMPREG(DISPC_VID_BA1(0));
2510 DUMPREG(DISPC_VID_POSITION(0));
2511 DUMPREG(DISPC_VID_SIZE(0));
2512 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2513 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2514 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2515 DUMPREG(DISPC_VID_ROW_INC(0));
2516 DUMPREG(DISPC_VID_PIXEL_INC(0));
2517 DUMPREG(DISPC_VID_FIR(0));
2518 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2519 DUMPREG(DISPC_VID_ACCU0(0));
2520 DUMPREG(DISPC_VID_ACCU1(0));
2521
2522 DUMPREG(DISPC_VID_BA0(1));
2523 DUMPREG(DISPC_VID_BA1(1));
2524 DUMPREG(DISPC_VID_POSITION(1));
2525 DUMPREG(DISPC_VID_SIZE(1));
2526 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2527 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2528 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2529 DUMPREG(DISPC_VID_ROW_INC(1));
2530 DUMPREG(DISPC_VID_PIXEL_INC(1));
2531 DUMPREG(DISPC_VID_FIR(1));
2532 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2533 DUMPREG(DISPC_VID_ACCU0(1));
2534 DUMPREG(DISPC_VID_ACCU1(1));
2535
2536 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2537 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2538 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2539 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2540 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2541 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2542 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2543 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2544 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2545 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2546 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2547 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2548 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2549 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2550 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2551 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2552 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2553 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2554 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2555 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2556 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2557 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2558 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2559 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2560 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2561 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2562 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2563 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2564 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2565
2566 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2567 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2568 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2569 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2570 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2571 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2572 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2573 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2574 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2575 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2576 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2577 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2578 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2579 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2580 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2581 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2582 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2583 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2584 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2585 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2586 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2587 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2588 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2589 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2590 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2591 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2592 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2593 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2594 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2595
2596 DUMPREG(DISPC_VID_PRELOAD(0));
2597 DUMPREG(DISPC_VID_PRELOAD(1));
2598
6af9cd14 2599 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2600#undef DUMPREG
2601}
2602
ff1b2cde
SS		 2603static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2604 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2605{
2606 u32 l = 0;
2607
2608 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2609 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2610
2611 l |= FLD_VAL(onoff, 17, 17);
2612 l |= FLD_VAL(rf, 16, 16);
2613 l |= FLD_VAL(ieo, 15, 15);
2614 l |= FLD_VAL(ipc, 14, 14);
2615 l |= FLD_VAL(ihs, 13, 13);
2616 l |= FLD_VAL(ivs, 12, 12);
2617 l |= FLD_VAL(acbi, 11, 8);
2618 l |= FLD_VAL(acb, 7, 0);
2619
2620 enable_clocks(1);
ff1b2cde 2621 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2622 enable_clocks(0);
2623}
2624
ff1b2cde
SS		 2625void dispc_set_pol_freq(enum omap_channel channel,
2626 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2627{
ff1b2cde 2628 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2629 (config & OMAP_DSS_LCD_RF) != 0,
2630 (config & OMAP_DSS_LCD_IEO) != 0,
2631 (config & OMAP_DSS_LCD_IPC) != 0,
2632 (config & OMAP_DSS_LCD_IHS) != 0,
2633 (config & OMAP_DSS_LCD_IVS) != 0,
2634 acbi, acb);
2635}
2636
2637/* with fck as input clock rate, find dispc dividers that produce req_pck */
2638void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2639 struct dispc_clock_info *cinfo)
2640{
2641 u16 pcd_min = is_tft ? 2 : 3;
2642 unsigned long best_pck;
2643 u16 best_ld, cur_ld;
2644 u16 best_pd, cur_pd;
2645
2646 best_pck = 0;
2647 best_ld = 0;
2648 best_pd = 0;
2649
2650 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2651 unsigned long lck = fck / cur_ld;
2652
2653 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2654 unsigned long pck = lck / cur_pd;
2655 long old_delta = abs(best_pck - req_pck);
2656 long new_delta = abs(pck - req_pck);
2657
2658 if (best_pck == 0 || new_delta < old_delta) {
2659 best_pck = pck;
2660 best_ld = cur_ld;
2661 best_pd = cur_pd;
2662
2663 if (pck == req_pck)
2664 goto found;
2665 }
2666
2667 if (pck < req_pck)
2668 break;
2669 }
2670
2671 if (lck / pcd_min < req_pck)
2672 break;
2673 }
2674
2675found:
2676 cinfo->lck_div = best_ld;
2677 cinfo->pck_div = best_pd;
2678 cinfo->lck = fck / cinfo->lck_div;
2679 cinfo->pck = cinfo->lck / cinfo->pck_div;
2680}
2681
2682/* calculate clock rates using dividers in cinfo */
2683int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2684 struct dispc_clock_info *cinfo)
2685{
2686 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2687 return -EINVAL;
2688 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2689 return -EINVAL;
2690
2691 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2692 cinfo->pck = cinfo->lck / cinfo->pck_div;
2693
2694 return 0;
2695}
2696
ff1b2cde
SS		 2697int dispc_set_clock_div(enum omap_channel channel,
2698 struct dispc_clock_info *cinfo)
80c39712
TV		 2699{
2700 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2701 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2702
ff1b2cde 2703 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2704
2705 return 0;
2706}
2707
ff1b2cde
SS		 2708int dispc_get_clock_div(enum omap_channel channel,
2709 struct dispc_clock_info *cinfo)
80c39712
TV		 2710{
2711 unsigned long fck;
2712
2713 fck = dispc_fclk_rate();
2714
ff1b2cde
SS		 2715 cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
2716 cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
80c39712
TV		 2717
2718 cinfo->lck = fck / cinfo->lck_div;
2719 cinfo->pck = cinfo->lck / cinfo->pck_div;
2720
2721 return 0;
2722}
2723
2724/* dispc.irq_lock has to be locked by the caller */
2725static void _omap_dispc_set_irqs(void)
2726{
2727 u32 mask;
2728 u32 old_mask;
2729 int i;
2730 struct omap_dispc_isr_data *isr_data;
2731
2732 mask = dispc.irq_error_mask;
2733
2734 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2735 isr_data = &dispc.registered_isr[i];
2736
2737 if (isr_data->isr == NULL)
2738 continue;
2739
2740 mask |= isr_data->mask;
2741 }
2742
2743 enable_clocks(1);
2744
2745 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2746 /* clear the irqstatus for newly enabled irqs */
2747 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2748
2749 dispc_write_reg(DISPC_IRQENABLE, mask);
2750
2751 enable_clocks(0);
2752}
2753
2754int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2755{
2756 int i;
2757 int ret;
2758 unsigned long flags;
2759 struct omap_dispc_isr_data *isr_data;
2760
2761 if (isr == NULL)
2762 return -EINVAL;
2763
2764 spin_lock_irqsave(&dispc.irq_lock, flags);
2765
2766 /* check for duplicate entry */
2767 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2768 isr_data = &dispc.registered_isr[i];
2769 if (isr_data->isr == isr && isr_data->arg == arg &&
2770 isr_data->mask == mask) {
2771 ret = -EINVAL;
2772 goto err;
2773 }
2774 }
2775
2776 isr_data = NULL;
2777 ret = -EBUSY;
2778
2779 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2780 isr_data = &dispc.registered_isr[i];
2781
2782 if (isr_data->isr != NULL)
2783 continue;
2784
2785 isr_data->isr = isr;
2786 isr_data->arg = arg;
2787 isr_data->mask = mask;
2788 ret = 0;
2789
2790 break;
2791 }
2792
2793 _omap_dispc_set_irqs();
2794
2795 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2796
2797 return 0;
2798err:
2799 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2800
2801 return ret;
2802}
2803EXPORT_SYMBOL(omap_dispc_register_isr);
2804
2805int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2806{
2807 int i;
2808 unsigned long flags;
2809 int ret = -EINVAL;
2810 struct omap_dispc_isr_data *isr_data;
2811
2812 spin_lock_irqsave(&dispc.irq_lock, flags);
2813
2814 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2815 isr_data = &dispc.registered_isr[i];
2816 if (isr_data->isr != isr || isr_data->arg != arg ||
2817 isr_data->mask != mask)
2818 continue;
2819
2820 /* found the correct isr */
2821
2822 isr_data->isr = NULL;
2823 isr_data->arg = NULL;
2824 isr_data->mask = 0;
2825
2826 ret = 0;
2827 break;
2828 }
2829
2830 if (ret == 0)
2831 _omap_dispc_set_irqs();
2832
2833 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2834
2835 return ret;
2836}
2837EXPORT_SYMBOL(omap_dispc_unregister_isr);
2838
2839#ifdef DEBUG
2840static void print_irq_status(u32 status)
2841{
2842 if ((status & dispc.irq_error_mask) == 0)
2843 return;
2844
2845 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2846
2847#define PIS(x) \
2848 if (status & DISPC_IRQ_##x) \
2849 printk(#x " ");
2850 PIS(GFX_FIFO_UNDERFLOW);
2851 PIS(OCP_ERR);
2852 PIS(VID1_FIFO_UNDERFLOW);
2853 PIS(VID2_FIFO_UNDERFLOW);
2854 PIS(SYNC_LOST);
2855 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2856 if (dss_has_feature(FEAT_MGR_LCD2))
2857 PIS(SYNC_LOST2);
80c39712
TV		 2858#undef PIS
2859
2860 printk("\n");
2861}
2862#endif
2863
2864/* Called from dss.c. Note that we don't touch clocks here,
2865 * but we presume they are on because we got an IRQ. However,
2866 * an irq handler may turn the clocks off, so we may not have
2867 * clock later in the function. */
2868void dispc_irq_handler(void)
2869{
2870 int i;
2871 u32 irqstatus;
2872 u32 handledirqs = 0;
2873 u32 unhandled_errors;
2874 struct omap_dispc_isr_data *isr_data;
2875 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2876
2877 spin_lock(&dispc.irq_lock);
2878
2879 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2880
dfc0fd8d
TV		 2881#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2882 spin_lock(&dispc.irq_stats_lock);
2883 dispc.irq_stats.irq_count++;
2884 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2885 spin_unlock(&dispc.irq_stats_lock);
2886#endif
2887
80c39712
TV		 2888#ifdef DEBUG
2889 if (dss_debug)
2890 print_irq_status(irqstatus);
2891#endif
2892 /* Ack the interrupt. Do it here before clocks are possibly turned
2893 * off */
2894 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2895 /* flush posted write */
2896 dispc_read_reg(DISPC_IRQSTATUS);
2897
2898 /* make a copy and unlock, so that isrs can unregister
2899 * themselves */
2900 memcpy(registered_isr, dispc.registered_isr,
2901 sizeof(registered_isr));
2902
2903 spin_unlock(&dispc.irq_lock);
2904
2905 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2906 isr_data = &registered_isr[i];
2907
2908 if (!isr_data->isr)
2909 continue;
2910
2911 if (isr_data->mask & irqstatus) {
2912 isr_data->isr(isr_data->arg, irqstatus);
2913 handledirqs |= isr_data->mask;
2914 }
2915 }
2916
2917 spin_lock(&dispc.irq_lock);
2918
2919 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2920
2921 if (unhandled_errors) {
2922 dispc.error_irqs |= unhandled_errors;
2923
2924 dispc.irq_error_mask &= ~unhandled_errors;
2925 _omap_dispc_set_irqs();
2926
2927 schedule_work(&dispc.error_work);
2928 }
2929
2930 spin_unlock(&dispc.irq_lock);
2931}
2932
2933static void dispc_error_worker(struct work_struct *work)
2934{
2935 int i;
2936 u32 errors;
2937 unsigned long flags;
2938
2939 spin_lock_irqsave(&dispc.irq_lock, flags);
2940 errors = dispc.error_irqs;
2941 dispc.error_irqs = 0;
2942 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2943
2944 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2945 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2946 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2947 struct omap_overlay *ovl;
2948 ovl = omap_dss_get_overlay(i);
2949
2950 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2951 continue;
2952
2953 if (ovl->id == 0) {
2954 dispc_enable_plane(ovl->id, 0);
2955 dispc_go(ovl->manager->id);
2956 mdelay(50);
2957 break;
2958 }
2959 }
2960 }
2961
2962 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2963 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2964 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2965 struct omap_overlay *ovl;
2966 ovl = omap_dss_get_overlay(i);
2967
2968 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2969 continue;
2970
2971 if (ovl->id == 1) {
2972 dispc_enable_plane(ovl->id, 0);
2973 dispc_go(ovl->manager->id);
2974 mdelay(50);
2975 break;
2976 }
2977 }
2978 }
2979
2980 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2981 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2982 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2983 struct omap_overlay *ovl;
2984 ovl = omap_dss_get_overlay(i);
2985
2986 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2987 continue;
2988
2989 if (ovl->id == 2) {
2990 dispc_enable_plane(ovl->id, 0);
2991 dispc_go(ovl->manager->id);
2992 mdelay(50);
2993 break;
2994 }
2995 }
2996 }
2997
2998 if (errors & DISPC_IRQ_SYNC_LOST) {
2999 struct omap_overlay_manager *manager = NULL;
3000 bool enable = false;
3001
3002 DSSERR("SYNC_LOST, disabling LCD\n");
3003
3004 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3005 struct omap_overlay_manager *mgr;
3006 mgr = omap_dss_get_overlay_manager(i);
3007
3008 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3009 manager = mgr;
3010 enable = mgr->device->state ==
3011 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3012 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3013 break;
3014 }
3015 }
3016
3017 if (manager) {
37ac60e4 3018 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3019 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3020 struct omap_overlay *ovl;
3021 ovl = omap_dss_get_overlay(i);
3022
3023 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3024 continue;
3025
3026 if (ovl->id != 0 && ovl->manager == manager)
3027 dispc_enable_plane(ovl->id, 0);
3028 }
3029
3030 dispc_go(manager->id);
3031 mdelay(50);
3032 if (enable)
37ac60e4 3033 dssdev->driver->enable(dssdev);
80c39712
TV		 3034 }
3035 }
3036
3037 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3038 struct omap_overlay_manager *manager = NULL;
3039 bool enable = false;
3040
3041 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3042
3043 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3044 struct omap_overlay_manager *mgr;
3045 mgr = omap_dss_get_overlay_manager(i);
3046
3047 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3048 manager = mgr;
3049 enable = mgr->device->state ==
3050 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3051 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3052 break;
3053 }
3054 }
3055
3056 if (manager) {
37ac60e4 3057 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3058 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3059 struct omap_overlay *ovl;
3060 ovl = omap_dss_get_overlay(i);
3061
3062 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3063 continue;
3064
3065 if (ovl->id != 0 && ovl->manager == manager)
3066 dispc_enable_plane(ovl->id, 0);
3067 }
3068
3069 dispc_go(manager->id);
3070 mdelay(50);
3071 if (enable)
37ac60e4 3072 dssdev->driver->enable(dssdev);
80c39712
TV		 3073 }
3074 }
3075
2a205f34
SS		 3076 if (errors & DISPC_IRQ_SYNC_LOST2) {
3077 struct omap_overlay_manager *manager = NULL;
3078 bool enable = false;
3079
3080 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3081
3082 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3083 struct omap_overlay_manager *mgr;
3084 mgr = omap_dss_get_overlay_manager(i);
3085
3086 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3087 manager = mgr;
3088 enable = mgr->device->state ==
3089 OMAP_DSS_DISPLAY_ACTIVE;
3090 mgr->device->driver->disable(mgr->device);
3091 break;
3092 }
3093 }
3094
3095 if (manager) {
3096 struct omap_dss_device *dssdev = manager->device;
3097 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3098 struct omap_overlay *ovl;
3099 ovl = omap_dss_get_overlay(i);
3100
3101 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3102 continue;
3103
3104 if (ovl->id != 0 && ovl->manager == manager)
3105 dispc_enable_plane(ovl->id, 0);
3106 }
3107
3108 dispc_go(manager->id);
3109 mdelay(50);
3110 if (enable)
3111 dssdev->driver->enable(dssdev);
3112 }
3113 }
3114
80c39712
TV		 3115 if (errors & DISPC_IRQ_OCP_ERR) {
3116 DSSERR("OCP_ERR\n");
3117 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3118 struct omap_overlay_manager *mgr;
3119 mgr = omap_dss_get_overlay_manager(i);
3120
3121 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3122 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3123 }
3124 }
3125
3126 spin_lock_irqsave(&dispc.irq_lock, flags);
3127 dispc.irq_error_mask |= errors;
3128 _omap_dispc_set_irqs();
3129 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3130}
3131
3132int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3133{
3134 void dispc_irq_wait_handler(void *data, u32 mask)
3135 {
3136 complete((struct completion *)data);
3137 }
3138
3139 int r;
3140 DECLARE_COMPLETION_ONSTACK(completion);
3141
3142 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3143 irqmask);
3144
3145 if (r)
3146 return r;
3147
3148 timeout = wait_for_completion_timeout(&completion, timeout);
3149
3150 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3151
3152 if (timeout == 0)
3153 return -ETIMEDOUT;
3154
3155 if (timeout == -ERESTARTSYS)
3156 return -ERESTARTSYS;
3157
3158 return 0;
3159}
3160
3161int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3162 unsigned long timeout)
3163{
3164 void dispc_irq_wait_handler(void *data, u32 mask)
3165 {
3166 complete((struct completion *)data);
3167 }
3168
3169 int r;
3170 DECLARE_COMPLETION_ONSTACK(completion);
3171
3172 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3173 irqmask);
3174
3175 if (r)
3176 return r;
3177
3178 timeout = wait_for_completion_interruptible_timeout(&completion,
3179 timeout);
3180
3181 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3182
3183 if (timeout == 0)
3184 return -ETIMEDOUT;
3185
3186 if (timeout == -ERESTARTSYS)
3187 return -ERESTARTSYS;
3188
3189 return 0;
3190}
3191
3192#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3193void dispc_fake_vsync_irq(void)
3194{
3195 u32 irqstatus = DISPC_IRQ_VSYNC;
3196 int i;
3197
ab83b14c 3198 WARN_ON(!in_interrupt());
80c39712
TV		 3199
3200 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3201 struct omap_dispc_isr_data *isr_data;
3202 isr_data = &dispc.registered_isr[i];
3203
3204 if (!isr_data->isr)
3205 continue;
3206
3207 if (isr_data->mask & irqstatus)
3208 isr_data->isr(isr_data->arg, irqstatus);
3209 }
80c39712
TV		 3210}
3211#endif
3212
3213static void _omap_dispc_initialize_irq(void)
3214{
3215 unsigned long flags;
3216
3217 spin_lock_irqsave(&dispc.irq_lock, flags);
3218
3219 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3220
3221 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3222 if (dss_has_feature(FEAT_MGR_LCD2))
3223 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3224
3225 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3226 * so clear it */
3227 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3228
3229 _omap_dispc_set_irqs();
3230
3231 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3232}
3233
3234void dispc_enable_sidle(void)
3235{
3236 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3237}
3238
3239void dispc_disable_sidle(void)
3240{
3241 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3242}
3243
3244static void _omap_dispc_initial_config(void)
3245{
3246 u32 l;
3247
3248 l = dispc_read_reg(DISPC_SYSCONFIG);
3249 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3250 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3251 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3252 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3253 dispc_write_reg(DISPC_SYSCONFIG, l);
3254
3255 /* FUNCGATED */
6ced40bf
AT		 3256 if (dss_has_feature(FEAT_FUNCGATED))
3257 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3258
3259 /* L3 firewall setting: enable access to OCM RAM */
3260 /* XXX this should be somewhere in plat-omap */
3261 if (cpu_is_omap24xx())
3262 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3263
3264 _dispc_setup_color_conv_coef();
3265
3266 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3267
3268 dispc_read_plane_fifo_sizes();
3269}
3270
80c39712
TV		 3271int dispc_enable_plane(enum omap_plane plane, bool enable)
3272{
3273 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3274
3275 enable_clocks(1);
3276 _dispc_enable_plane(plane, enable);
3277 enable_clocks(0);
3278
3279 return 0;
3280}
3281
3282int dispc_setup_plane(enum omap_plane plane,
3283 u32 paddr, u16 screen_width,
3284 u16 pos_x, u16 pos_y,
3285 u16 width, u16 height,
3286 u16 out_width, u16 out_height,
3287 enum omap_color_mode color_mode,
3288 bool ilace,
3289 enum omap_dss_rotation_type rotation_type,
fd28a390 3290 u8 rotation, bool mirror, u8 global_alpha,
18faa1b6 3291 u8 pre_mult_alpha, enum omap_channel channel)
80c39712
TV		 3292{
3293 int r = 0;
3294
3295 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
18faa1b6 3296 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
80c39712
TV		 3297 plane, paddr, screen_width, pos_x, pos_y,
3298 width, height,
3299 out_width, out_height,
3300 ilace, color_mode,
18faa1b6 3301 rotation, mirror, channel);
80c39712
TV		 3302
3303 enable_clocks(1);
3304
3305 r = _dispc_setup_plane(plane,
3306 paddr, screen_width,
3307 pos_x, pos_y,
3308 width, height,
3309 out_width, out_height,
3310 color_mode, ilace,
3311 rotation_type,
3312 rotation, mirror,
fd28a390 3313 global_alpha,
18faa1b6 3314 pre_mult_alpha, channel);
80c39712
TV		 3315
3316 enable_clocks(0);
3317
3318 return r;
3319}
060b6d9c
SG		 3320
3321/* DISPC HW IP initialisation */
3322static int omap_dispchw_probe(struct platform_device *pdev)
3323{
3324 u32 rev;
ea9da36a
SG		 3325 struct resource *dispc_mem;
3326
060b6d9c
SG		 3327 dispc.pdev = pdev;
3328
3329 spin_lock_init(&dispc.irq_lock);
3330
3331#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3332 spin_lock_init(&dispc.irq_stats_lock);
3333 dispc.irq_stats.last_reset = jiffies;
3334#endif
3335
3336 INIT_WORK(&dispc.error_work, dispc_error_worker);
3337
ea9da36a
SG		 3338 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3339 if (!dispc_mem) {
3340 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3341 return -EINVAL;
3342 }
3343 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3344 if (!dispc.base) {
3345 DSSERR("can't ioremap DISPC\n");
3346 return -ENOMEM;
3347 }
3348
3349 enable_clocks(1);
3350
3351 _omap_dispc_initial_config();
3352
3353 _omap_dispc_initialize_irq();
3354
3355 dispc_save_context();
3356
3357 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3358 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3359 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3360
3361 enable_clocks(0);
3362
3363 return 0;
3364}
3365
3366static int omap_dispchw_remove(struct platform_device *pdev)
3367{
3368 iounmap(dispc.base);
3369 return 0;
3370}
3371
3372static struct platform_driver omap_dispchw_driver = {
3373 .probe = omap_dispchw_probe,
3374 .remove = omap_dispchw_remove,
3375 .driver = {
3376 .name = "omapdss_dispc",
3377 .owner = THIS_MODULE,
3378 },
3379};
3380
3381int dispc_init_platform_driver(void)
3382{
3383 return platform_driver_register(&omap_dispchw_driver);
3384}
3385
3386void dispc_uninit_platform_driver(void)
3387{
3388 return platform_driver_unregister(&omap_dispchw_driver);
3389}
kernel source for telekom puls (alcatel/mediatek)