projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
omapfb: lcd_ams_delta: add support for contrast control
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap2 / dss / core.c
CommitLineData
559d6701
TV		 1/*
2 * linux/drivers/video/omap2/dss/core.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "CORE"
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/platform_device.h>
30#include <linux/seq_file.h>
31#include <linux/debugfs.h>
32#include <linux/io.h>
33#include <linux/device.h>
34
35#include <plat/display.h>
36#include <plat/clock.h>
37
38#include "dss.h"
39
40static struct {
41 struct platform_device *pdev;
42 int ctx_id;
43
44 struct clk *dss_ick;
45 struct clk *dss1_fck;
46 struct clk *dss2_fck;
47 struct clk *dss_54m_fck;
48 struct clk *dss_96m_fck;
49 unsigned num_clks_enabled;
50} core;
51
52static void dss_clk_enable_all_no_ctx(void);
53static void dss_clk_disable_all_no_ctx(void);
54static void dss_clk_enable_no_ctx(enum dss_clock clks);
55static void dss_clk_disable_no_ctx(enum dss_clock clks);
56
57static char *def_disp_name;
58module_param_named(def_disp, def_disp_name, charp, 0);
59MODULE_PARM_DESC(def_disp_name, "default display name");
60
61#ifdef DEBUG
62unsigned int dss_debug;
63module_param_named(debug, dss_debug, bool, 0644);
64#endif
65
66/* CONTEXT */
67static int dss_get_ctx_id(void)
68{
69 struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
70 int r;
71
72 if (!pdata->get_last_off_on_transaction_id)
73 return 0;
74 r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
75 if (r < 0) {
76 dev_err(&core.pdev->dev, "getting transaction ID failed, "
77 "will force context restore\n");
78 r = -1;
79 }
80 return r;
81}
82
83int dss_need_ctx_restore(void)
84{
85 int id = dss_get_ctx_id();
86
87 if (id < 0 || id != core.ctx_id) {
88 DSSDBG("ctx id %d -> id %d\n",
89 core.ctx_id, id);
90 core.ctx_id = id;
91 return 1;
92 } else {
93 return 0;
94 }
95}
96
97static void save_all_ctx(void)
98{
99 DSSDBG("save context\n");
100
101 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
102
103 dss_save_context();
104 dispc_save_context();
105#ifdef CONFIG_OMAP2_DSS_DSI
106 dsi_save_context();
107#endif
108
109 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
110}
111
112static void restore_all_ctx(void)
113{
114 DSSDBG("restore context\n");
115
116 dss_clk_enable_all_no_ctx();
117
118 dss_restore_context();
119 dispc_restore_context();
120#ifdef CONFIG_OMAP2_DSS_DSI
121 dsi_restore_context();
122#endif
123
124 dss_clk_disable_all_no_ctx();
125}
126
5c18df85 127#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
559d6701
TV		 128/* CLOCKS */
129static void core_dump_clocks(struct seq_file *s)
130{
131 int i;
132 struct clk *clocks[5] = {
133 core.dss_ick,
134 core.dss1_fck,
135 core.dss2_fck,
136 core.dss_54m_fck,
137 core.dss_96m_fck
138 };
139
140 seq_printf(s, "- CORE -\n");
141
142 seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
143
144 for (i = 0; i < 5; i++) {
145 if (!clocks[i])
146 continue;
147 seq_printf(s, "%-15s\t%lu\t%d\n",
148 clocks[i]->name,
149 clk_get_rate(clocks[i]),
150 clocks[i]->usecount);
151 }
152}
5c18df85 153#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
559d6701
TV		 154
155static int dss_get_clock(struct clk **clock, const char *clk_name)
156{
157 struct clk *clk;
158
159 clk = clk_get(&core.pdev->dev, clk_name);
160
161 if (IS_ERR(clk)) {
162 DSSERR("can't get clock %s", clk_name);
163 return PTR_ERR(clk);
164 }
165
166 *clock = clk;
167
168 DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
169
170 return 0;
171}
172
173static int dss_get_clocks(void)
174{
175 int r;
176
177 core.dss_ick = NULL;
178 core.dss1_fck = NULL;
179 core.dss2_fck = NULL;
180 core.dss_54m_fck = NULL;
181 core.dss_96m_fck = NULL;
182
183 r = dss_get_clock(&core.dss_ick, "ick");
184 if (r)
185 goto err;
186
187 r = dss_get_clock(&core.dss1_fck, "dss1_fck");
188 if (r)
189 goto err;
190
191 r = dss_get_clock(&core.dss2_fck, "dss2_fck");
192 if (r)
193 goto err;
194
195 r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
196 if (r)
197 goto err;
198
199 r = dss_get_clock(&core.dss_96m_fck, "video_fck");
200 if (r)
201 goto err;
202
203 return 0;
204
205err:
206 if (core.dss_ick)
207 clk_put(core.dss_ick);
208 if (core.dss1_fck)
209 clk_put(core.dss1_fck);
210 if (core.dss2_fck)
211 clk_put(core.dss2_fck);
212 if (core.dss_54m_fck)
213 clk_put(core.dss_54m_fck);
214 if (core.dss_96m_fck)
215 clk_put(core.dss_96m_fck);
216
217 return r;
218}
219
220static void dss_put_clocks(void)
221{
222 if (core.dss_96m_fck)
223 clk_put(core.dss_96m_fck);
224 clk_put(core.dss_54m_fck);
225 clk_put(core.dss1_fck);
226 clk_put(core.dss2_fck);
227 clk_put(core.dss_ick);
228}
229
230unsigned long dss_clk_get_rate(enum dss_clock clk)
231{
232 switch (clk) {
233 case DSS_CLK_ICK:
234 return clk_get_rate(core.dss_ick);
235 case DSS_CLK_FCK1:
236 return clk_get_rate(core.dss1_fck);
237 case DSS_CLK_FCK2:
238 return clk_get_rate(core.dss2_fck);
239 case DSS_CLK_54M:
240 return clk_get_rate(core.dss_54m_fck);
241 case DSS_CLK_96M:
242 return clk_get_rate(core.dss_96m_fck);
243 }
244
245 BUG();
246 return 0;
247}
248
249static unsigned count_clk_bits(enum dss_clock clks)
250{
251 unsigned num_clks = 0;
252
253 if (clks & DSS_CLK_ICK)
254 ++num_clks;
255 if (clks & DSS_CLK_FCK1)
256 ++num_clks;
257 if (clks & DSS_CLK_FCK2)
258 ++num_clks;
259 if (clks & DSS_CLK_54M)
260 ++num_clks;
261 if (clks & DSS_CLK_96M)
262 ++num_clks;
263
264 return num_clks;
265}
266
267static void dss_clk_enable_no_ctx(enum dss_clock clks)
268{
269 unsigned num_clks = count_clk_bits(clks);
270
271 if (clks & DSS_CLK_ICK)
272 clk_enable(core.dss_ick);
273 if (clks & DSS_CLK_FCK1)
274 clk_enable(core.dss1_fck);
275 if (clks & DSS_CLK_FCK2)
276 clk_enable(core.dss2_fck);
277 if (clks & DSS_CLK_54M)
278 clk_enable(core.dss_54m_fck);
279 if (clks & DSS_CLK_96M)
280 clk_enable(core.dss_96m_fck);
281
282 core.num_clks_enabled += num_clks;
283}
284
285void dss_clk_enable(enum dss_clock clks)
286{
287 dss_clk_enable_no_ctx(clks);
288
289 if (cpu_is_omap34xx() && dss_need_ctx_restore())
290 restore_all_ctx();
291}
292
293static void dss_clk_disable_no_ctx(enum dss_clock clks)
294{
295 unsigned num_clks = count_clk_bits(clks);
296
297 if (clks & DSS_CLK_ICK)
298 clk_disable(core.dss_ick);
299 if (clks & DSS_CLK_FCK1)
300 clk_disable(core.dss1_fck);
301 if (clks & DSS_CLK_FCK2)
302 clk_disable(core.dss2_fck);
303 if (clks & DSS_CLK_54M)
304 clk_disable(core.dss_54m_fck);
305 if (clks & DSS_CLK_96M)
306 clk_disable(core.dss_96m_fck);
307
308 core.num_clks_enabled -= num_clks;
309}
310
311void dss_clk_disable(enum dss_clock clks)
312{
313 if (cpu_is_omap34xx()) {
314 unsigned num_clks = count_clk_bits(clks);
315
316 BUG_ON(core.num_clks_enabled < num_clks);
317
318 if (core.num_clks_enabled == num_clks)
319 save_all_ctx();
320 }
321
322 dss_clk_disable_no_ctx(clks);
323}
324
325static void dss_clk_enable_all_no_ctx(void)
326{
327 enum dss_clock clks;
328
329 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
330 if (cpu_is_omap34xx())
331 clks |= DSS_CLK_96M;
332 dss_clk_enable_no_ctx(clks);
333}
334
335static void dss_clk_disable_all_no_ctx(void)
336{
337 enum dss_clock clks;
338
339 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
340 if (cpu_is_omap34xx())
341 clks |= DSS_CLK_96M;
342 dss_clk_disable_no_ctx(clks);
343}
344
345static void dss_clk_disable_all(void)
346{
347 enum dss_clock clks;
348
349 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
350 if (cpu_is_omap34xx())
351 clks |= DSS_CLK_96M;
352 dss_clk_disable(clks);
353}
354
355/* DEBUGFS */
356#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
357static void dss_debug_dump_clocks(struct seq_file *s)
358{
359 core_dump_clocks(s);
360 dss_dump_clocks(s);
361 dispc_dump_clocks(s);
362#ifdef CONFIG_OMAP2_DSS_DSI
363 dsi_dump_clocks(s);
364#endif
365}
366
367static int dss_debug_show(struct seq_file *s, void *unused)
368{
369 void (*func)(struct seq_file *) = s->private;
370 func(s);
371 return 0;
372}
373
374static int dss_debug_open(struct inode *inode, struct file *file)
375{
376 return single_open(file, dss_debug_show, inode->i_private);
377}
378
379static const struct file_operations dss_debug_fops = {
380 .open = dss_debug_open,
381 .read = seq_read,
382 .llseek = seq_lseek,
383 .release = single_release,
384};
385
386static struct dentry *dss_debugfs_dir;
387
388static int dss_initialize_debugfs(void)
389{
390 dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
391 if (IS_ERR(dss_debugfs_dir)) {
392 int err = PTR_ERR(dss_debugfs_dir);
393 dss_debugfs_dir = NULL;
394 return err;
395 }
396
397 debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
398 &dss_debug_dump_clocks, &dss_debug_fops);
399
dfc0fd8d
TV		 400 debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir,
401 &dispc_dump_irqs, &dss_debug_fops);
402
403#ifdef CONFIG_OMAP2_DSS_DSI
404 debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
405 &dsi_dump_irqs, &dss_debug_fops);
406#endif
407
559d6701
TV		 408 debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
409 &dss_dump_regs, &dss_debug_fops);
410 debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
411 &dispc_dump_regs, &dss_debug_fops);
412#ifdef CONFIG_OMAP2_DSS_RFBI
413 debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
414 &rfbi_dump_regs, &dss_debug_fops);
415#endif
416#ifdef CONFIG_OMAP2_DSS_DSI
417 debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
418 &dsi_dump_regs, &dss_debug_fops);
419#endif
420#ifdef CONFIG_OMAP2_DSS_VENC
421 debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
422 &venc_dump_regs, &dss_debug_fops);
423#endif
424 return 0;
425}
426
427static void dss_uninitialize_debugfs(void)
428{
429 if (dss_debugfs_dir)
430 debugfs_remove_recursive(dss_debugfs_dir);
431}
432#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
433
434/* PLATFORM DEVICE */
435static int omap_dss_probe(struct platform_device *pdev)
436{
437 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
438 int skip_init = 0;
439 int r;
440 int i;
441
442 core.pdev = pdev;
443
444 dss_init_overlay_managers(pdev);
445 dss_init_overlays(pdev);
446
447 r = dss_get_clocks();
448 if (r)
449 goto fail0;
450
451 dss_clk_enable_all_no_ctx();
452
453 core.ctx_id = dss_get_ctx_id();
454 DSSDBG("initial ctx id %u\n", core.ctx_id);
455
456#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
457 /* DISPC_CONTROL */
458 if (omap_readl(0x48050440) & 1) /* LCD enabled? */
459 skip_init = 1;
460#endif
461
462 r = dss_init(skip_init);
463 if (r) {
464 DSSERR("Failed to initialize DSS\n");
465 goto fail0;
466 }
467
468#ifdef CONFIG_OMAP2_DSS_RFBI
469 r = rfbi_init();
470 if (r) {
471 DSSERR("Failed to initialize rfbi\n");
472 goto fail0;
473 }
474#endif
475
476 r = dpi_init();
477 if (r) {
478 DSSERR("Failed to initialize dpi\n");
479 goto fail0;
480 }
481
482 r = dispc_init();
483 if (r) {
484 DSSERR("Failed to initialize dispc\n");
485 goto fail0;
486 }
487#ifdef CONFIG_OMAP2_DSS_VENC
488 r = venc_init(pdev);
489 if (r) {
490 DSSERR("Failed to initialize venc\n");
491 goto fail0;
492 }
493#endif
494 if (cpu_is_omap34xx()) {
495#ifdef CONFIG_OMAP2_DSS_SDI
496 r = sdi_init(skip_init);
497 if (r) {
498 DSSERR("Failed to initialize SDI\n");
499 goto fail0;
500 }
501#endif
502#ifdef CONFIG_OMAP2_DSS_DSI
503 r = dsi_init(pdev);
504 if (r) {
505 DSSERR("Failed to initialize DSI\n");
506 goto fail0;
507 }
508#endif
509 }
510
511#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
512 r = dss_initialize_debugfs();
513 if (r)
514 goto fail0;
515#endif
516
517 for (i = 0; i < pdata->num_devices; ++i) {
518 struct omap_dss_device *dssdev = pdata->devices[i];
519
520 r = omap_dss_register_device(dssdev);
521 if (r)
522 DSSERR("device reg failed %d\n", i);
523
524 if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
525 pdata->default_device = dssdev;
526 }
527
528 dss_clk_disable_all();
529
530 return 0;
531
532 /* XXX fail correctly */
533fail0:
534 return r;
535}
536
537static int omap_dss_remove(struct platform_device *pdev)
538{
539 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
540 int i;
541 int c;
542
543#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
544 dss_uninitialize_debugfs();
545#endif
546
547#ifdef CONFIG_OMAP2_DSS_VENC
548 venc_exit();
549#endif
550 dispc_exit();
551 dpi_exit();
552#ifdef CONFIG_OMAP2_DSS_RFBI
553 rfbi_exit();
554#endif
555 if (cpu_is_omap34xx()) {
556#ifdef CONFIG_OMAP2_DSS_DSI
557 dsi_exit();
558#endif
559#ifdef CONFIG_OMAP2_DSS_SDI
560 sdi_exit();
561#endif
562 }
563
564 dss_exit();
565
566 /* these should be removed at some point */
567 c = core.dss_ick->usecount;
568 if (c > 0) {
569 DSSERR("warning: dss_ick usecount %d, disabling\n", c);
570 while (c-- > 0)
571 clk_disable(core.dss_ick);
572 }
573
574 c = core.dss1_fck->usecount;
575 if (c > 0) {
576 DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
577 while (c-- > 0)
578 clk_disable(core.dss1_fck);
579 }
580
581 c = core.dss2_fck->usecount;
582 if (c > 0) {
583 DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
584 while (c-- > 0)
585 clk_disable(core.dss2_fck);
586 }
587
588 c = core.dss_54m_fck->usecount;
589 if (c > 0) {
590 DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
591 while (c-- > 0)
592 clk_disable(core.dss_54m_fck);
593 }
594
595 if (core.dss_96m_fck) {
596 c = core.dss_96m_fck->usecount;
597 if (c > 0) {
598 DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
599 c);
600 while (c-- > 0)
601 clk_disable(core.dss_96m_fck);
602 }
603 }
604
605 dss_put_clocks();
606
607 dss_uninit_overlays(pdev);
608 dss_uninit_overlay_managers(pdev);
609
610 for (i = 0; i < pdata->num_devices; ++i)
611 omap_dss_unregister_device(pdata->devices[i]);
612
613 return 0;
614}
615
616static void omap_dss_shutdown(struct platform_device *pdev)
617{
618 DSSDBG("shutdown\n");
619 dss_disable_all_devices();
620}
621
622static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
623{
624 DSSDBG("suspend %d\n", state.event);
625
626 return dss_suspend_all_devices();
627}
628
629static int omap_dss_resume(struct platform_device *pdev)
630{
631 DSSDBG("resume\n");
632
633 return dss_resume_all_devices();
634}
635
636static struct platform_driver omap_dss_driver = {
637 .probe = omap_dss_probe,
638 .remove = omap_dss_remove,
639 .shutdown = omap_dss_shutdown,
640 .suspend = omap_dss_suspend,
641 .resume = omap_dss_resume,
642 .driver = {
643 .name = "omapdss",
644 .owner = THIS_MODULE,
645 },
646};
647
648/* BUS */
649static int dss_bus_match(struct device *dev, struct device_driver *driver)
650{
651 struct omap_dss_device *dssdev = to_dss_device(dev);
652
653 DSSDBG("bus_match. dev %s/%s, drv %s\n",
654 dev_name(dev), dssdev->driver_name, driver->name);
655
656 return strcmp(dssdev->driver_name, driver->name) == 0;
657}
658
659static ssize_t device_name_show(struct device *dev,
660 struct device_attribute *attr, char *buf)
661{
662 struct omap_dss_device *dssdev = to_dss_device(dev);
663 return snprintf(buf, PAGE_SIZE, "%s\n",
664 dssdev->name ?
665 dssdev->name : "");
666}
667
668static struct device_attribute default_dev_attrs[] = {
669 __ATTR(name, S_IRUGO, device_name_show, NULL),
670 __ATTR_NULL,
671};
672
673static ssize_t driver_name_show(struct device_driver *drv, char *buf)
674{
675 struct omap_dss_driver *dssdrv = to_dss_driver(drv);
676 return snprintf(buf, PAGE_SIZE, "%s\n",
677 dssdrv->driver.name ?
678 dssdrv->driver.name : "");
679}
680static struct driver_attribute default_drv_attrs[] = {
681 __ATTR(name, S_IRUGO, driver_name_show, NULL),
682 __ATTR_NULL,
683};
684
685static struct bus_type dss_bus_type = {
686 .name = "omapdss",
687 .match = dss_bus_match,
688 .dev_attrs = default_dev_attrs,
689 .drv_attrs = default_drv_attrs,
690};
691
692static void dss_bus_release(struct device *dev)
693{
694 DSSDBG("bus_release\n");
695}
696
697static struct device dss_bus = {
698 .release = dss_bus_release,
699};
700
701struct bus_type *dss_get_bus(void)
702{
703 return &dss_bus_type;
704}
705
706/* DRIVER */
707static int dss_driver_probe(struct device *dev)
708{
709 int r;
710 struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
711 struct omap_dss_device *dssdev = to_dss_device(dev);
712 struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
713 bool force;
714
715 DSSDBG("driver_probe: dev %s/%s, drv %s\n",
716 dev_name(dev), dssdev->driver_name,
717 dssdrv->driver.name);
718
719 dss_init_device(core.pdev, dssdev);
720
721 /* skip this if the device is behind a ctrl */
722 if (!dssdev->panel.ctrl) {
723 force = pdata->default_device == dssdev;
724 dss_recheck_connections(dssdev, force);
725 }
726
727 r = dssdrv->probe(dssdev);
728
729 if (r) {
730 DSSERR("driver probe failed: %d\n", r);
731 return r;
732 }
733
734 DSSDBG("probe done for device %s\n", dev_name(dev));
735
736 dssdev->driver = dssdrv;
737
738 return 0;
739}
740
741static int dss_driver_remove(struct device *dev)
742{
743 struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
744 struct omap_dss_device *dssdev = to_dss_device(dev);
745
746 DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
747 dssdev->driver_name);
748
749 dssdrv->remove(dssdev);
750
751 dss_uninit_device(core.pdev, dssdev);
752
753 dssdev->driver = NULL;
754
755 return 0;
756}
757
758int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
759{
760 dssdriver->driver.bus = &dss_bus_type;
761 dssdriver->driver.probe = dss_driver_probe;
762 dssdriver->driver.remove = dss_driver_remove;
763 return driver_register(&dssdriver->driver);
764}
765EXPORT_SYMBOL(omap_dss_register_driver);
766
767void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
768{
769 driver_unregister(&dssdriver->driver);
770}
771EXPORT_SYMBOL(omap_dss_unregister_driver);
772
773/* DEVICE */
774static void reset_device(struct device *dev, int check)
775{
776 u8 *dev_p = (u8 *)dev;
777 u8 *dev_end = dev_p + sizeof(*dev);
778 void *saved_pdata;
779
780 saved_pdata = dev->platform_data;
781 if (check) {
782 /*
783 * Check if there is any other setting than platform_data
784 * in struct device; warn that these will be reset by our
785 * init.
786 */
787 dev->platform_data = NULL;
788 while (dev_p < dev_end) {
789 if (*dev_p) {
790 WARN("%s: struct device fields will be "
791 "discarded\n",
792 __func__);
793 break;
794 }
795 dev_p++;
796 }
797 }
798 memset(dev, 0, sizeof(*dev));
799 dev->platform_data = saved_pdata;
800}
801
802
803static void omap_dss_dev_release(struct device *dev)
804{
805 reset_device(dev, 0);
806}
807
808int omap_dss_register_device(struct omap_dss_device *dssdev)
809{
810 static int dev_num;
811 static int panel_num;
812 int r;
813
814 WARN_ON(!dssdev->driver_name);
815
816 reset_device(&dssdev->dev, 1);
817 dssdev->dev.bus = &dss_bus_type;
818 dssdev->dev.parent = &dss_bus;
819 dssdev->dev.release = omap_dss_dev_release;
820 dev_set_name(&dssdev->dev, "display%d", dev_num++);
821 r = device_register(&dssdev->dev);
822 if (r)
823 return r;
824
825 if (dssdev->ctrl.panel) {
826 struct omap_dss_device *panel = dssdev->ctrl.panel;
827
828 panel->panel.ctrl = dssdev;
829
830 reset_device(&panel->dev, 1);
831 panel->dev.bus = &dss_bus_type;
832 panel->dev.parent = &dssdev->dev;
833 panel->dev.release = omap_dss_dev_release;
834 dev_set_name(&panel->dev, "panel%d", panel_num++);
835 r = device_register(&panel->dev);
836 if (r)
837 return r;
838 }
839
840 return 0;
841}
842
843void omap_dss_unregister_device(struct omap_dss_device *dssdev)
844{
845 device_unregister(&dssdev->dev);
846
847 if (dssdev->ctrl.panel) {
848 struct omap_dss_device *panel = dssdev->ctrl.panel;
849 device_unregister(&panel->dev);
850 }
851}
852
853/* BUS */
854static int omap_dss_bus_register(void)
855{
856 int r;
857
858 r = bus_register(&dss_bus_type);
859 if (r) {
860 DSSERR("bus register failed\n");
861 return r;
862 }
863
864 dev_set_name(&dss_bus, "omapdss");
865 r = device_register(&dss_bus);
866 if (r) {
867 DSSERR("bus driver register failed\n");
868 bus_unregister(&dss_bus_type);
869 return r;
870 }
871
872 return 0;
873}
874
875/* INIT */
876
877#ifdef CONFIG_OMAP2_DSS_MODULE
878static void omap_dss_bus_unregister(void)
879{
880 device_unregister(&dss_bus);
881
882 bus_unregister(&dss_bus_type);
883}
884
885static int __init omap_dss_init(void)
886{
887 int r;
888
889 r = omap_dss_bus_register();
890 if (r)
891 return r;
892
893 r = platform_driver_register(&omap_dss_driver);
894 if (r) {
895 omap_dss_bus_unregister();
896 return r;
897 }
898
899 return 0;
900}
901
902static void __exit omap_dss_exit(void)
903{
904 platform_driver_unregister(&omap_dss_driver);
905
906 omap_dss_bus_unregister();
907}
908
909module_init(omap_dss_init);
910module_exit(omap_dss_exit);
911#else
912static int __init omap_dss_init(void)
913{
914 return omap_dss_bus_register();
915}
916
917static int __init omap_dss_init2(void)
918{
919 return platform_driver_register(&omap_dss_driver);
920}
921
922core_initcall(omap_dss_init);
923device_initcall(omap_dss_init2);
924#endif
925
926MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
927MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
928MODULE_LICENSE("GPL v2");
929
kernel source for telekom puls (alcatel/mediatek)