projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAP: DSS2: move enable/disable_channel to overlay manager
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap2 / dss / core.c
CommitLineData
559d6701
TV		 1/*
2 * linux/drivers/video/omap2/dss/core.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "CORE"
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/platform_device.h>
30#include <linux/seq_file.h>
31#include <linux/debugfs.h>
32#include <linux/io.h>
33#include <linux/device.h>
8a2cfea8 34#include <linux/regulator/consumer.h>
559d6701
TV		 35
36#include <plat/display.h>
37#include <plat/clock.h>
38
39#include "dss.h"
40
41static struct {
42 struct platform_device *pdev;
43 int ctx_id;
44
45 struct clk *dss_ick;
46 struct clk *dss1_fck;
47 struct clk *dss2_fck;
48 struct clk *dss_54m_fck;
49 struct clk *dss_96m_fck;
50 unsigned num_clks_enabled;
8a2cfea8
TV		 51
52 struct regulator *vdds_dsi_reg;
53 struct regulator *vdds_sdi_reg;
54 struct regulator *vdda_dac_reg;
559d6701
TV		 55} core;
56
57static void dss_clk_enable_all_no_ctx(void);
58static void dss_clk_disable_all_no_ctx(void);
59static void dss_clk_enable_no_ctx(enum dss_clock clks);
60static void dss_clk_disable_no_ctx(enum dss_clock clks);
61
62static char *def_disp_name;
63module_param_named(def_disp, def_disp_name, charp, 0);
64MODULE_PARM_DESC(def_disp_name, "default display name");
65
66#ifdef DEBUG
67unsigned int dss_debug;
68module_param_named(debug, dss_debug, bool, 0644);
69#endif
70
71/* CONTEXT */
72static int dss_get_ctx_id(void)
73{
74 struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
75 int r;
76
77 if (!pdata->get_last_off_on_transaction_id)
78 return 0;
79 r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
80 if (r < 0) {
81 dev_err(&core.pdev->dev, "getting transaction ID failed, "
82 "will force context restore\n");
83 r = -1;
84 }
85 return r;
86}
87
88int dss_need_ctx_restore(void)
89{
90 int id = dss_get_ctx_id();
91
92 if (id < 0 || id != core.ctx_id) {
93 DSSDBG("ctx id %d -> id %d\n",
94 core.ctx_id, id);
95 core.ctx_id = id;
96 return 1;
97 } else {
98 return 0;
99 }
100}
101
102static void save_all_ctx(void)
103{
104 DSSDBG("save context\n");
105
106 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
107
108 dss_save_context();
109 dispc_save_context();
110#ifdef CONFIG_OMAP2_DSS_DSI
111 dsi_save_context();
112#endif
113
114 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
115}
116
117static void restore_all_ctx(void)
118{
119 DSSDBG("restore context\n");
120
121 dss_clk_enable_all_no_ctx();
122
123 dss_restore_context();
124 dispc_restore_context();
125#ifdef CONFIG_OMAP2_DSS_DSI
126 dsi_restore_context();
127#endif
128
129 dss_clk_disable_all_no_ctx();
130}
131
5c18df85 132#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
559d6701
TV		 133/* CLOCKS */
134static void core_dump_clocks(struct seq_file *s)
135{
136 int i;
137 struct clk *clocks[5] = {
138 core.dss_ick,
139 core.dss1_fck,
140 core.dss2_fck,
141 core.dss_54m_fck,
142 core.dss_96m_fck
143 };
144
145 seq_printf(s, "- CORE -\n");
146
147 seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
148
149 for (i = 0; i < 5; i++) {
150 if (!clocks[i])
151 continue;
152 seq_printf(s, "%-15s\t%lu\t%d\n",
153 clocks[i]->name,
154 clk_get_rate(clocks[i]),
155 clocks[i]->usecount);
156 }
157}
5c18df85 158#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
559d6701
TV		 159
160static int dss_get_clock(struct clk **clock, const char *clk_name)
161{
162 struct clk *clk;
163
164 clk = clk_get(&core.pdev->dev, clk_name);
165
166 if (IS_ERR(clk)) {
167 DSSERR("can't get clock %s", clk_name);
168 return PTR_ERR(clk);
169 }
170
171 *clock = clk;
172
173 DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
174
175 return 0;
176}
177
178static int dss_get_clocks(void)
179{
180 int r;
181
182 core.dss_ick = NULL;
183 core.dss1_fck = NULL;
184 core.dss2_fck = NULL;
185 core.dss_54m_fck = NULL;
186 core.dss_96m_fck = NULL;
187
188 r = dss_get_clock(&core.dss_ick, "ick");
189 if (r)
190 goto err;
191
192 r = dss_get_clock(&core.dss1_fck, "dss1_fck");
193 if (r)
194 goto err;
195
196 r = dss_get_clock(&core.dss2_fck, "dss2_fck");
197 if (r)
198 goto err;
199
200 r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
201 if (r)
202 goto err;
203
204 r = dss_get_clock(&core.dss_96m_fck, "video_fck");
205 if (r)
206 goto err;
207
208 return 0;
209
210err:
211 if (core.dss_ick)
212 clk_put(core.dss_ick);
213 if (core.dss1_fck)
214 clk_put(core.dss1_fck);
215 if (core.dss2_fck)
216 clk_put(core.dss2_fck);
217 if (core.dss_54m_fck)
218 clk_put(core.dss_54m_fck);
219 if (core.dss_96m_fck)
220 clk_put(core.dss_96m_fck);
221
222 return r;
223}
224
225static void dss_put_clocks(void)
226{
227 if (core.dss_96m_fck)
228 clk_put(core.dss_96m_fck);
229 clk_put(core.dss_54m_fck);
230 clk_put(core.dss1_fck);
231 clk_put(core.dss2_fck);
232 clk_put(core.dss_ick);
233}
234
235unsigned long dss_clk_get_rate(enum dss_clock clk)
236{
237 switch (clk) {
238 case DSS_CLK_ICK:
239 return clk_get_rate(core.dss_ick);
240 case DSS_CLK_FCK1:
241 return clk_get_rate(core.dss1_fck);
242 case DSS_CLK_FCK2:
243 return clk_get_rate(core.dss2_fck);
244 case DSS_CLK_54M:
245 return clk_get_rate(core.dss_54m_fck);
246 case DSS_CLK_96M:
247 return clk_get_rate(core.dss_96m_fck);
248 }
249
250 BUG();
251 return 0;
252}
253
254static unsigned count_clk_bits(enum dss_clock clks)
255{
256 unsigned num_clks = 0;
257
258 if (clks & DSS_CLK_ICK)
259 ++num_clks;
260 if (clks & DSS_CLK_FCK1)
261 ++num_clks;
262 if (clks & DSS_CLK_FCK2)
263 ++num_clks;
264 if (clks & DSS_CLK_54M)
265 ++num_clks;
266 if (clks & DSS_CLK_96M)
267 ++num_clks;
268
269 return num_clks;
270}
271
272static void dss_clk_enable_no_ctx(enum dss_clock clks)
273{
274 unsigned num_clks = count_clk_bits(clks);
275
276 if (clks & DSS_CLK_ICK)
277 clk_enable(core.dss_ick);
278 if (clks & DSS_CLK_FCK1)
279 clk_enable(core.dss1_fck);
280 if (clks & DSS_CLK_FCK2)
281 clk_enable(core.dss2_fck);
282 if (clks & DSS_CLK_54M)
283 clk_enable(core.dss_54m_fck);
284 if (clks & DSS_CLK_96M)
285 clk_enable(core.dss_96m_fck);
286
287 core.num_clks_enabled += num_clks;
288}
289
290void dss_clk_enable(enum dss_clock clks)
291{
e2962649
TV		 292 bool check_ctx = core.num_clks_enabled == 0;
293
559d6701
TV		 294 dss_clk_enable_no_ctx(clks);
295
e2962649 296 if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
559d6701
TV		 297 restore_all_ctx();
298}
299
300static void dss_clk_disable_no_ctx(enum dss_clock clks)
301{
302 unsigned num_clks = count_clk_bits(clks);
303
304 if (clks & DSS_CLK_ICK)
305 clk_disable(core.dss_ick);
306 if (clks & DSS_CLK_FCK1)
307 clk_disable(core.dss1_fck);
308 if (clks & DSS_CLK_FCK2)
309 clk_disable(core.dss2_fck);
310 if (clks & DSS_CLK_54M)
311 clk_disable(core.dss_54m_fck);
312 if (clks & DSS_CLK_96M)
313 clk_disable(core.dss_96m_fck);
314
315 core.num_clks_enabled -= num_clks;
316}
317
318void dss_clk_disable(enum dss_clock clks)
319{
320 if (cpu_is_omap34xx()) {
321 unsigned num_clks = count_clk_bits(clks);
322
323 BUG_ON(core.num_clks_enabled < num_clks);
324
325 if (core.num_clks_enabled == num_clks)
326 save_all_ctx();
327 }
328
329 dss_clk_disable_no_ctx(clks);
330}
331
332static void dss_clk_enable_all_no_ctx(void)
333{
334 enum dss_clock clks;
335
336 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
337 if (cpu_is_omap34xx())
338 clks |= DSS_CLK_96M;
339 dss_clk_enable_no_ctx(clks);
340}
341
342static void dss_clk_disable_all_no_ctx(void)
343{
344 enum dss_clock clks;
345
346 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
347 if (cpu_is_omap34xx())
348 clks |= DSS_CLK_96M;
349 dss_clk_disable_no_ctx(clks);
350}
351
352static void dss_clk_disable_all(void)
353{
354 enum dss_clock clks;
355
356 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
357 if (cpu_is_omap34xx())
358 clks |= DSS_CLK_96M;
359 dss_clk_disable(clks);
360}
361
8a2cfea8
TV		 362/* REGULATORS */
363
364struct regulator *dss_get_vdds_dsi(void)
365{
366 struct regulator *reg;
367
368 if (core.vdds_dsi_reg != NULL)
369 return core.vdds_dsi_reg;
370
371 reg = regulator_get(&core.pdev->dev, "vdds_dsi");
372 if (!IS_ERR(reg))
373 core.vdds_dsi_reg = reg;
374
375 return reg;
376}
377
378struct regulator *dss_get_vdds_sdi(void)
379{
380 struct regulator *reg;
381
382 if (core.vdds_sdi_reg != NULL)
383 return core.vdds_sdi_reg;
384
385 reg = regulator_get(&core.pdev->dev, "vdds_sdi");
386 if (!IS_ERR(reg))
387 core.vdds_sdi_reg = reg;
388
389 return reg;
390}
391
392struct regulator *dss_get_vdda_dac(void)
393{
394 struct regulator *reg;
395
396 if (core.vdda_dac_reg != NULL)
397 return core.vdda_dac_reg;
398
399 reg = regulator_get(&core.pdev->dev, "vdda_dac");
400 if (!IS_ERR(reg))
401 core.vdda_dac_reg = reg;
402
403 return reg;
404}
405
559d6701
TV		 406/* DEBUGFS */
407#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
408static void dss_debug_dump_clocks(struct seq_file *s)
409{
410 core_dump_clocks(s);
411 dss_dump_clocks(s);
412 dispc_dump_clocks(s);
413#ifdef CONFIG_OMAP2_DSS_DSI
414 dsi_dump_clocks(s);
415#endif
416}
417
418static int dss_debug_show(struct seq_file *s, void *unused)
419{
420 void (*func)(struct seq_file *) = s->private;
421 func(s);
422 return 0;
423}
424
425static int dss_debug_open(struct inode *inode, struct file *file)
426{
427 return single_open(file, dss_debug_show, inode->i_private);
428}
429
430static const struct file_operations dss_debug_fops = {
431 .open = dss_debug_open,
432 .read = seq_read,
433 .llseek = seq_lseek,
434 .release = single_release,
435};
436
437static struct dentry *dss_debugfs_dir;
438
439static int dss_initialize_debugfs(void)
440{
441 dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
442 if (IS_ERR(dss_debugfs_dir)) {
443 int err = PTR_ERR(dss_debugfs_dir);
444 dss_debugfs_dir = NULL;
445 return err;
446 }
447
448 debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
449 &dss_debug_dump_clocks, &dss_debug_fops);
450
853525d7 451#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
dfc0fd8d
TV		 452 debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir,
453 &dispc_dump_irqs, &dss_debug_fops);
853525d7 454#endif
dfc0fd8d 455
853525d7 456#if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS)
dfc0fd8d
TV		 457 debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
458 &dsi_dump_irqs, &dss_debug_fops);
459#endif
460
559d6701
TV		 461 debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
462 &dss_dump_regs, &dss_debug_fops);
463 debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
464 &dispc_dump_regs, &dss_debug_fops);
465#ifdef CONFIG_OMAP2_DSS_RFBI
466 debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
467 &rfbi_dump_regs, &dss_debug_fops);
468#endif
469#ifdef CONFIG_OMAP2_DSS_DSI
470 debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
471 &dsi_dump_regs, &dss_debug_fops);
472#endif
473#ifdef CONFIG_OMAP2_DSS_VENC
474 debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
475 &venc_dump_regs, &dss_debug_fops);
476#endif
477 return 0;
478}
479
480static void dss_uninitialize_debugfs(void)
481{
482 if (dss_debugfs_dir)
483 debugfs_remove_recursive(dss_debugfs_dir);
484}
485#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
486
487/* PLATFORM DEVICE */
488static int omap_dss_probe(struct platform_device *pdev)
489{
490 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
491 int skip_init = 0;
492 int r;
493 int i;
494
495 core.pdev = pdev;
496
497 dss_init_overlay_managers(pdev);
498 dss_init_overlays(pdev);
499
500 r = dss_get_clocks();
501 if (r)
502 goto fail0;
503
504 dss_clk_enable_all_no_ctx();
505
506 core.ctx_id = dss_get_ctx_id();
507 DSSDBG("initial ctx id %u\n", core.ctx_id);
508
509#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
510 /* DISPC_CONTROL */
511 if (omap_readl(0x48050440) & 1) /* LCD enabled? */
512 skip_init = 1;
513#endif
514
515 r = dss_init(skip_init);
516 if (r) {
517 DSSERR("Failed to initialize DSS\n");
518 goto fail0;
519 }
520
521#ifdef CONFIG_OMAP2_DSS_RFBI
522 r = rfbi_init();
523 if (r) {
524 DSSERR("Failed to initialize rfbi\n");
525 goto fail0;
526 }
527#endif
528
8a2cfea8 529 r = dpi_init(pdev);
559d6701
TV		 530 if (r) {
531 DSSERR("Failed to initialize dpi\n");
532 goto fail0;
533 }
534
535 r = dispc_init();
536 if (r) {
537 DSSERR("Failed to initialize dispc\n");
538 goto fail0;
539 }
540#ifdef CONFIG_OMAP2_DSS_VENC
541 r = venc_init(pdev);
542 if (r) {
543 DSSERR("Failed to initialize venc\n");
544 goto fail0;
545 }
546#endif
547 if (cpu_is_omap34xx()) {
548#ifdef CONFIG_OMAP2_DSS_SDI
549 r = sdi_init(skip_init);
550 if (r) {
551 DSSERR("Failed to initialize SDI\n");
552 goto fail0;
553 }
554#endif
555#ifdef CONFIG_OMAP2_DSS_DSI
556 r = dsi_init(pdev);
557 if (r) {
558 DSSERR("Failed to initialize DSI\n");
559 goto fail0;
560 }
561#endif
562 }
563
564#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
565 r = dss_initialize_debugfs();
566 if (r)
567 goto fail0;
568#endif
569
570 for (i = 0; i < pdata->num_devices; ++i) {
571 struct omap_dss_device *dssdev = pdata->devices[i];
572
573 r = omap_dss_register_device(dssdev);
574 if (r)
575 DSSERR("device reg failed %d\n", i);
576
577 if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
578 pdata->default_device = dssdev;
579 }
580
581 dss_clk_disable_all();
582
583 return 0;
584
585 /* XXX fail correctly */
586fail0:
587 return r;
588}
589
590static int omap_dss_remove(struct platform_device *pdev)
591{
592 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
593 int i;
594 int c;
595
596#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
597 dss_uninitialize_debugfs();
598#endif
599
600#ifdef CONFIG_OMAP2_DSS_VENC
601 venc_exit();
602#endif
603 dispc_exit();
604 dpi_exit();
605#ifdef CONFIG_OMAP2_DSS_RFBI
606 rfbi_exit();
607#endif
608 if (cpu_is_omap34xx()) {
609#ifdef CONFIG_OMAP2_DSS_DSI
610 dsi_exit();
611#endif
612#ifdef CONFIG_OMAP2_DSS_SDI
613 sdi_exit();
614#endif
615 }
616
617 dss_exit();
618
619 /* these should be removed at some point */
620 c = core.dss_ick->usecount;
621 if (c > 0) {
622 DSSERR("warning: dss_ick usecount %d, disabling\n", c);
623 while (c-- > 0)
624 clk_disable(core.dss_ick);
625 }
626
627 c = core.dss1_fck->usecount;
628 if (c > 0) {
629 DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
630 while (c-- > 0)
631 clk_disable(core.dss1_fck);
632 }
633
634 c = core.dss2_fck->usecount;
635 if (c > 0) {
636 DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
637 while (c-- > 0)
638 clk_disable(core.dss2_fck);
639 }
640
641 c = core.dss_54m_fck->usecount;
642 if (c > 0) {
643 DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
644 while (c-- > 0)
645 clk_disable(core.dss_54m_fck);
646 }
647
648 if (core.dss_96m_fck) {
649 c = core.dss_96m_fck->usecount;
650 if (c > 0) {
651 DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
652 c);
653 while (c-- > 0)
654 clk_disable(core.dss_96m_fck);
655 }
656 }
657
658 dss_put_clocks();
659
660 dss_uninit_overlays(pdev);
661 dss_uninit_overlay_managers(pdev);
662
663 for (i = 0; i < pdata->num_devices; ++i)
664 omap_dss_unregister_device(pdata->devices[i]);
665
666 return 0;
667}
668
669static void omap_dss_shutdown(struct platform_device *pdev)
670{
671 DSSDBG("shutdown\n");
672 dss_disable_all_devices();
673}
674
675static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
676{
677 DSSDBG("suspend %d\n", state.event);
678
679 return dss_suspend_all_devices();
680}
681
682static int omap_dss_resume(struct platform_device *pdev)
683{
684 DSSDBG("resume\n");
685
686 return dss_resume_all_devices();
687}
688
689static struct platform_driver omap_dss_driver = {
690 .probe = omap_dss_probe,
691 .remove = omap_dss_remove,
692 .shutdown = omap_dss_shutdown,
693 .suspend = omap_dss_suspend,
694 .resume = omap_dss_resume,
695 .driver = {
696 .name = "omapdss",
697 .owner = THIS_MODULE,
698 },
699};
700
701/* BUS */
702static int dss_bus_match(struct device *dev, struct device_driver *driver)
703{
704 struct omap_dss_device *dssdev = to_dss_device(dev);
705
706 DSSDBG("bus_match. dev %s/%s, drv %s\n",
707 dev_name(dev), dssdev->driver_name, driver->name);
708
709 return strcmp(dssdev->driver_name, driver->name) == 0;
710}
711
712static ssize_t device_name_show(struct device *dev,
713 struct device_attribute *attr, char *buf)
714{
715 struct omap_dss_device *dssdev = to_dss_device(dev);
716 return snprintf(buf, PAGE_SIZE, "%s\n",
717 dssdev->name ?
718 dssdev->name : "");
719}
720
721static struct device_attribute default_dev_attrs[] = {
722 __ATTR(name, S_IRUGO, device_name_show, NULL),
723 __ATTR_NULL,
724};
725
726static ssize_t driver_name_show(struct device_driver *drv, char *buf)
727{
728 struct omap_dss_driver *dssdrv = to_dss_driver(drv);
729 return snprintf(buf, PAGE_SIZE, "%s\n",
730 dssdrv->driver.name ?
731 dssdrv->driver.name : "");
732}
733static struct driver_attribute default_drv_attrs[] = {
734 __ATTR(name, S_IRUGO, driver_name_show, NULL),
735 __ATTR_NULL,
736};
737
738static struct bus_type dss_bus_type = {
739 .name = "omapdss",
740 .match = dss_bus_match,
741 .dev_attrs = default_dev_attrs,
742 .drv_attrs = default_drv_attrs,
743};
744
745static void dss_bus_release(struct device *dev)
746{
747 DSSDBG("bus_release\n");
748}
749
750static struct device dss_bus = {
751 .release = dss_bus_release,
752};
753
754struct bus_type *dss_get_bus(void)
755{
756 return &dss_bus_type;
757}
758
759/* DRIVER */
760static int dss_driver_probe(struct device *dev)
761{
762 int r;
763 struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
764 struct omap_dss_device *dssdev = to_dss_device(dev);
765 struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
766 bool force;
767
768 DSSDBG("driver_probe: dev %s/%s, drv %s\n",
769 dev_name(dev), dssdev->driver_name,
770 dssdrv->driver.name);
771
772 dss_init_device(core.pdev, dssdev);
773
e020f9af
TV		 774 force = pdata->default_device == dssdev;
775 dss_recheck_connections(dssdev, force);
559d6701
TV		 776
777 r = dssdrv->probe(dssdev);
778
779 if (r) {
780 DSSERR("driver probe failed: %d\n", r);
c121b152 781 dss_uninit_device(core.pdev, dssdev);
559d6701
TV		 782 return r;
783 }
784
785 DSSDBG("probe done for device %s\n", dev_name(dev));
786
787 dssdev->driver = dssdrv;
788
789 return 0;
790}
791
792static int dss_driver_remove(struct device *dev)
793{
794 struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
795 struct omap_dss_device *dssdev = to_dss_device(dev);
796
797 DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
798 dssdev->driver_name);
799
800 dssdrv->remove(dssdev);
801
802 dss_uninit_device(core.pdev, dssdev);
803
804 dssdev->driver = NULL;
805
806 return 0;
807}
808
809int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
810{
811 dssdriver->driver.bus = &dss_bus_type;
812 dssdriver->driver.probe = dss_driver_probe;
813 dssdriver->driver.remove = dss_driver_remove;
814 return driver_register(&dssdriver->driver);
815}
816EXPORT_SYMBOL(omap_dss_register_driver);
817
818void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
819{
820 driver_unregister(&dssdriver->driver);
821}
822EXPORT_SYMBOL(omap_dss_unregister_driver);
823
824/* DEVICE */
825static void reset_device(struct device *dev, int check)
826{
827 u8 *dev_p = (u8 *)dev;
828 u8 *dev_end = dev_p + sizeof(*dev);
829 void *saved_pdata;
830
831 saved_pdata = dev->platform_data;
832 if (check) {
833 /*
834 * Check if there is any other setting than platform_data
835 * in struct device; warn that these will be reset by our
836 * init.
837 */
838 dev->platform_data = NULL;
839 while (dev_p < dev_end) {
840 if (*dev_p) {
841 WARN("%s: struct device fields will be "
842 "discarded\n",
843 __func__);
844 break;
845 }
846 dev_p++;
847 }
848 }
849 memset(dev, 0, sizeof(*dev));
850 dev->platform_data = saved_pdata;
851}
852
853
854static void omap_dss_dev_release(struct device *dev)
855{
856 reset_device(dev, 0);
857}
858
859int omap_dss_register_device(struct omap_dss_device *dssdev)
860{
861 static int dev_num;
559d6701
TV		 862
863 WARN_ON(!dssdev->driver_name);
864
865 reset_device(&dssdev->dev, 1);
866 dssdev->dev.bus = &dss_bus_type;
867 dssdev->dev.parent = &dss_bus;
868 dssdev->dev.release = omap_dss_dev_release;
869 dev_set_name(&dssdev->dev, "display%d", dev_num++);
e020f9af 870 return device_register(&dssdev->dev);
559d6701
TV		 871}
872
873void omap_dss_unregister_device(struct omap_dss_device *dssdev)
874{
875 device_unregister(&dssdev->dev);
559d6701
TV		 876}
877
878/* BUS */
879static int omap_dss_bus_register(void)
880{
881 int r;
882
883 r = bus_register(&dss_bus_type);
884 if (r) {
885 DSSERR("bus register failed\n");
886 return r;
887 }
888
889 dev_set_name(&dss_bus, "omapdss");
890 r = device_register(&dss_bus);
891 if (r) {
892 DSSERR("bus driver register failed\n");
893 bus_unregister(&dss_bus_type);
894 return r;
895 }
896
897 return 0;
898}
899
900/* INIT */
901
902#ifdef CONFIG_OMAP2_DSS_MODULE
903static void omap_dss_bus_unregister(void)
904{
905 device_unregister(&dss_bus);
906
907 bus_unregister(&dss_bus_type);
908}
909
910static int __init omap_dss_init(void)
911{
912 int r;
913
914 r = omap_dss_bus_register();
915 if (r)
916 return r;
917
918 r = platform_driver_register(&omap_dss_driver);
919 if (r) {
920 omap_dss_bus_unregister();
921 return r;
922 }
923
924 return 0;
925}
926
927static void __exit omap_dss_exit(void)
928{
8a2cfea8
TV		 929 if (core.vdds_dsi_reg != NULL) {
930 regulator_put(core.vdds_dsi_reg);
931 core.vdds_dsi_reg = NULL;
932 }
933
934 if (core.vdds_sdi_reg != NULL) {
935 regulator_put(core.vdds_sdi_reg);
936 core.vdds_sdi_reg = NULL;
937 }
938
939 if (core.vdda_dac_reg != NULL) {
940 regulator_put(core.vdda_dac_reg);
941 core.vdda_dac_reg = NULL;
942 }
943
559d6701
TV		 944 platform_driver_unregister(&omap_dss_driver);
945
946 omap_dss_bus_unregister();
947}
948
949module_init(omap_dss_init);
950module_exit(omap_dss_exit);
951#else
952static int __init omap_dss_init(void)
953{
954 return omap_dss_bus_register();
955}
956
957static int __init omap_dss_init2(void)
958{
959 return platform_driver_register(&omap_dss_driver);
960}
961
962core_initcall(omap_dss_init);
963device_initcall(omap_dss_init2);
964#endif
965
966MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
967MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
968MODULE_LICENSE("GPL v2");
969
kernel source for telekom puls (alcatel/mediatek)