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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/core.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "CORE" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/err.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/seq_file.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/device.h> | |
8a2cfea8 | 34 | #include <linux/regulator/consumer.h> |
559d6701 TV |
35 | |
36 | #include <plat/display.h> | |
37 | #include <plat/clock.h> | |
38 | ||
39 | #include "dss.h" | |
a0acb557 | 40 | #include "dss_features.h" |
559d6701 TV |
41 | |
42 | static struct { | |
43 | struct platform_device *pdev; | |
44 | int ctx_id; | |
45 | ||
46 | struct clk *dss_ick; | |
47 | struct clk *dss1_fck; | |
48 | struct clk *dss2_fck; | |
49 | struct clk *dss_54m_fck; | |
50 | struct clk *dss_96m_fck; | |
51 | unsigned num_clks_enabled; | |
8a2cfea8 TV |
52 | |
53 | struct regulator *vdds_dsi_reg; | |
54 | struct regulator *vdds_sdi_reg; | |
55 | struct regulator *vdda_dac_reg; | |
559d6701 TV |
56 | } core; |
57 | ||
58 | static void dss_clk_enable_all_no_ctx(void); | |
59 | static void dss_clk_disable_all_no_ctx(void); | |
60 | static void dss_clk_enable_no_ctx(enum dss_clock clks); | |
61 | static void dss_clk_disable_no_ctx(enum dss_clock clks); | |
62 | ||
63 | static char *def_disp_name; | |
64 | module_param_named(def_disp, def_disp_name, charp, 0); | |
65 | MODULE_PARM_DESC(def_disp_name, "default display name"); | |
66 | ||
67 | #ifdef DEBUG | |
68 | unsigned int dss_debug; | |
69 | module_param_named(debug, dss_debug, bool, 0644); | |
70 | #endif | |
71 | ||
72 | /* CONTEXT */ | |
73 | static int dss_get_ctx_id(void) | |
74 | { | |
75 | struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; | |
76 | int r; | |
77 | ||
78 | if (!pdata->get_last_off_on_transaction_id) | |
79 | return 0; | |
80 | r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); | |
81 | if (r < 0) { | |
82 | dev_err(&core.pdev->dev, "getting transaction ID failed, " | |
83 | "will force context restore\n"); | |
84 | r = -1; | |
85 | } | |
86 | return r; | |
87 | } | |
88 | ||
89 | int dss_need_ctx_restore(void) | |
90 | { | |
91 | int id = dss_get_ctx_id(); | |
92 | ||
93 | if (id < 0 || id != core.ctx_id) { | |
94 | DSSDBG("ctx id %d -> id %d\n", | |
95 | core.ctx_id, id); | |
96 | core.ctx_id = id; | |
97 | return 1; | |
98 | } else { | |
99 | return 0; | |
100 | } | |
101 | } | |
102 | ||
103 | static void save_all_ctx(void) | |
104 | { | |
105 | DSSDBG("save context\n"); | |
106 | ||
107 | dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); | |
108 | ||
109 | dss_save_context(); | |
110 | dispc_save_context(); | |
111 | #ifdef CONFIG_OMAP2_DSS_DSI | |
112 | dsi_save_context(); | |
113 | #endif | |
114 | ||
115 | dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); | |
116 | } | |
117 | ||
118 | static void restore_all_ctx(void) | |
119 | { | |
120 | DSSDBG("restore context\n"); | |
121 | ||
122 | dss_clk_enable_all_no_ctx(); | |
123 | ||
124 | dss_restore_context(); | |
125 | dispc_restore_context(); | |
126 | #ifdef CONFIG_OMAP2_DSS_DSI | |
127 | dsi_restore_context(); | |
128 | #endif | |
129 | ||
130 | dss_clk_disable_all_no_ctx(); | |
131 | } | |
132 | ||
5c18df85 | 133 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
559d6701 TV |
134 | /* CLOCKS */ |
135 | static void core_dump_clocks(struct seq_file *s) | |
136 | { | |
137 | int i; | |
138 | struct clk *clocks[5] = { | |
139 | core.dss_ick, | |
140 | core.dss1_fck, | |
141 | core.dss2_fck, | |
142 | core.dss_54m_fck, | |
143 | core.dss_96m_fck | |
144 | }; | |
145 | ||
146 | seq_printf(s, "- CORE -\n"); | |
147 | ||
148 | seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled); | |
149 | ||
150 | for (i = 0; i < 5; i++) { | |
151 | if (!clocks[i]) | |
152 | continue; | |
153 | seq_printf(s, "%-15s\t%lu\t%d\n", | |
154 | clocks[i]->name, | |
155 | clk_get_rate(clocks[i]), | |
156 | clocks[i]->usecount); | |
157 | } | |
158 | } | |
5c18df85 | 159 | #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ |
559d6701 TV |
160 | |
161 | static int dss_get_clock(struct clk **clock, const char *clk_name) | |
162 | { | |
163 | struct clk *clk; | |
164 | ||
165 | clk = clk_get(&core.pdev->dev, clk_name); | |
166 | ||
167 | if (IS_ERR(clk)) { | |
168 | DSSERR("can't get clock %s", clk_name); | |
169 | return PTR_ERR(clk); | |
170 | } | |
171 | ||
172 | *clock = clk; | |
173 | ||
174 | DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static int dss_get_clocks(void) | |
180 | { | |
181 | int r; | |
182 | ||
183 | core.dss_ick = NULL; | |
184 | core.dss1_fck = NULL; | |
185 | core.dss2_fck = NULL; | |
186 | core.dss_54m_fck = NULL; | |
187 | core.dss_96m_fck = NULL; | |
188 | ||
189 | r = dss_get_clock(&core.dss_ick, "ick"); | |
190 | if (r) | |
191 | goto err; | |
192 | ||
193 | r = dss_get_clock(&core.dss1_fck, "dss1_fck"); | |
194 | if (r) | |
195 | goto err; | |
196 | ||
197 | r = dss_get_clock(&core.dss2_fck, "dss2_fck"); | |
198 | if (r) | |
199 | goto err; | |
200 | ||
201 | r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); | |
202 | if (r) | |
203 | goto err; | |
204 | ||
205 | r = dss_get_clock(&core.dss_96m_fck, "video_fck"); | |
206 | if (r) | |
207 | goto err; | |
208 | ||
209 | return 0; | |
210 | ||
211 | err: | |
212 | if (core.dss_ick) | |
213 | clk_put(core.dss_ick); | |
214 | if (core.dss1_fck) | |
215 | clk_put(core.dss1_fck); | |
216 | if (core.dss2_fck) | |
217 | clk_put(core.dss2_fck); | |
218 | if (core.dss_54m_fck) | |
219 | clk_put(core.dss_54m_fck); | |
220 | if (core.dss_96m_fck) | |
221 | clk_put(core.dss_96m_fck); | |
222 | ||
223 | return r; | |
224 | } | |
225 | ||
226 | static void dss_put_clocks(void) | |
227 | { | |
228 | if (core.dss_96m_fck) | |
229 | clk_put(core.dss_96m_fck); | |
230 | clk_put(core.dss_54m_fck); | |
231 | clk_put(core.dss1_fck); | |
232 | clk_put(core.dss2_fck); | |
233 | clk_put(core.dss_ick); | |
234 | } | |
235 | ||
236 | unsigned long dss_clk_get_rate(enum dss_clock clk) | |
237 | { | |
238 | switch (clk) { | |
239 | case DSS_CLK_ICK: | |
240 | return clk_get_rate(core.dss_ick); | |
241 | case DSS_CLK_FCK1: | |
242 | return clk_get_rate(core.dss1_fck); | |
243 | case DSS_CLK_FCK2: | |
244 | return clk_get_rate(core.dss2_fck); | |
245 | case DSS_CLK_54M: | |
246 | return clk_get_rate(core.dss_54m_fck); | |
247 | case DSS_CLK_96M: | |
248 | return clk_get_rate(core.dss_96m_fck); | |
249 | } | |
250 | ||
251 | BUG(); | |
252 | return 0; | |
253 | } | |
254 | ||
255 | static unsigned count_clk_bits(enum dss_clock clks) | |
256 | { | |
257 | unsigned num_clks = 0; | |
258 | ||
259 | if (clks & DSS_CLK_ICK) | |
260 | ++num_clks; | |
261 | if (clks & DSS_CLK_FCK1) | |
262 | ++num_clks; | |
263 | if (clks & DSS_CLK_FCK2) | |
264 | ++num_clks; | |
265 | if (clks & DSS_CLK_54M) | |
266 | ++num_clks; | |
267 | if (clks & DSS_CLK_96M) | |
268 | ++num_clks; | |
269 | ||
270 | return num_clks; | |
271 | } | |
272 | ||
273 | static void dss_clk_enable_no_ctx(enum dss_clock clks) | |
274 | { | |
275 | unsigned num_clks = count_clk_bits(clks); | |
276 | ||
277 | if (clks & DSS_CLK_ICK) | |
278 | clk_enable(core.dss_ick); | |
279 | if (clks & DSS_CLK_FCK1) | |
280 | clk_enable(core.dss1_fck); | |
281 | if (clks & DSS_CLK_FCK2) | |
282 | clk_enable(core.dss2_fck); | |
283 | if (clks & DSS_CLK_54M) | |
284 | clk_enable(core.dss_54m_fck); | |
285 | if (clks & DSS_CLK_96M) | |
286 | clk_enable(core.dss_96m_fck); | |
287 | ||
288 | core.num_clks_enabled += num_clks; | |
289 | } | |
290 | ||
291 | void dss_clk_enable(enum dss_clock clks) | |
292 | { | |
e2962649 TV |
293 | bool check_ctx = core.num_clks_enabled == 0; |
294 | ||
559d6701 TV |
295 | dss_clk_enable_no_ctx(clks); |
296 | ||
e2962649 | 297 | if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) |
559d6701 TV |
298 | restore_all_ctx(); |
299 | } | |
300 | ||
301 | static void dss_clk_disable_no_ctx(enum dss_clock clks) | |
302 | { | |
303 | unsigned num_clks = count_clk_bits(clks); | |
304 | ||
305 | if (clks & DSS_CLK_ICK) | |
306 | clk_disable(core.dss_ick); | |
307 | if (clks & DSS_CLK_FCK1) | |
308 | clk_disable(core.dss1_fck); | |
309 | if (clks & DSS_CLK_FCK2) | |
310 | clk_disable(core.dss2_fck); | |
311 | if (clks & DSS_CLK_54M) | |
312 | clk_disable(core.dss_54m_fck); | |
313 | if (clks & DSS_CLK_96M) | |
314 | clk_disable(core.dss_96m_fck); | |
315 | ||
316 | core.num_clks_enabled -= num_clks; | |
317 | } | |
318 | ||
319 | void dss_clk_disable(enum dss_clock clks) | |
320 | { | |
321 | if (cpu_is_omap34xx()) { | |
322 | unsigned num_clks = count_clk_bits(clks); | |
323 | ||
324 | BUG_ON(core.num_clks_enabled < num_clks); | |
325 | ||
326 | if (core.num_clks_enabled == num_clks) | |
327 | save_all_ctx(); | |
328 | } | |
329 | ||
330 | dss_clk_disable_no_ctx(clks); | |
331 | } | |
332 | ||
333 | static void dss_clk_enable_all_no_ctx(void) | |
334 | { | |
335 | enum dss_clock clks; | |
336 | ||
337 | clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; | |
338 | if (cpu_is_omap34xx()) | |
339 | clks |= DSS_CLK_96M; | |
340 | dss_clk_enable_no_ctx(clks); | |
341 | } | |
342 | ||
343 | static void dss_clk_disable_all_no_ctx(void) | |
344 | { | |
345 | enum dss_clock clks; | |
346 | ||
347 | clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; | |
348 | if (cpu_is_omap34xx()) | |
349 | clks |= DSS_CLK_96M; | |
350 | dss_clk_disable_no_ctx(clks); | |
351 | } | |
352 | ||
353 | static void dss_clk_disable_all(void) | |
354 | { | |
355 | enum dss_clock clks; | |
356 | ||
357 | clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; | |
358 | if (cpu_is_omap34xx()) | |
359 | clks |= DSS_CLK_96M; | |
360 | dss_clk_disable(clks); | |
361 | } | |
362 | ||
8a2cfea8 TV |
363 | /* REGULATORS */ |
364 | ||
365 | struct regulator *dss_get_vdds_dsi(void) | |
366 | { | |
367 | struct regulator *reg; | |
368 | ||
369 | if (core.vdds_dsi_reg != NULL) | |
370 | return core.vdds_dsi_reg; | |
371 | ||
372 | reg = regulator_get(&core.pdev->dev, "vdds_dsi"); | |
373 | if (!IS_ERR(reg)) | |
374 | core.vdds_dsi_reg = reg; | |
375 | ||
376 | return reg; | |
377 | } | |
378 | ||
379 | struct regulator *dss_get_vdds_sdi(void) | |
380 | { | |
381 | struct regulator *reg; | |
382 | ||
383 | if (core.vdds_sdi_reg != NULL) | |
384 | return core.vdds_sdi_reg; | |
385 | ||
386 | reg = regulator_get(&core.pdev->dev, "vdds_sdi"); | |
387 | if (!IS_ERR(reg)) | |
388 | core.vdds_sdi_reg = reg; | |
389 | ||
390 | return reg; | |
391 | } | |
392 | ||
393 | struct regulator *dss_get_vdda_dac(void) | |
394 | { | |
395 | struct regulator *reg; | |
396 | ||
397 | if (core.vdda_dac_reg != NULL) | |
398 | return core.vdda_dac_reg; | |
399 | ||
400 | reg = regulator_get(&core.pdev->dev, "vdda_dac"); | |
401 | if (!IS_ERR(reg)) | |
402 | core.vdda_dac_reg = reg; | |
403 | ||
404 | return reg; | |
405 | } | |
406 | ||
559d6701 TV |
407 | /* DEBUGFS */ |
408 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
409 | static void dss_debug_dump_clocks(struct seq_file *s) | |
410 | { | |
411 | core_dump_clocks(s); | |
412 | dss_dump_clocks(s); | |
413 | dispc_dump_clocks(s); | |
414 | #ifdef CONFIG_OMAP2_DSS_DSI | |
415 | dsi_dump_clocks(s); | |
416 | #endif | |
417 | } | |
418 | ||
419 | static int dss_debug_show(struct seq_file *s, void *unused) | |
420 | { | |
421 | void (*func)(struct seq_file *) = s->private; | |
422 | func(s); | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static int dss_debug_open(struct inode *inode, struct file *file) | |
427 | { | |
428 | return single_open(file, dss_debug_show, inode->i_private); | |
429 | } | |
430 | ||
431 | static const struct file_operations dss_debug_fops = { | |
432 | .open = dss_debug_open, | |
433 | .read = seq_read, | |
434 | .llseek = seq_lseek, | |
435 | .release = single_release, | |
436 | }; | |
437 | ||
438 | static struct dentry *dss_debugfs_dir; | |
439 | ||
440 | static int dss_initialize_debugfs(void) | |
441 | { | |
442 | dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); | |
443 | if (IS_ERR(dss_debugfs_dir)) { | |
444 | int err = PTR_ERR(dss_debugfs_dir); | |
445 | dss_debugfs_dir = NULL; | |
446 | return err; | |
447 | } | |
448 | ||
449 | debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, | |
450 | &dss_debug_dump_clocks, &dss_debug_fops); | |
451 | ||
853525d7 | 452 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
dfc0fd8d TV |
453 | debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir, |
454 | &dispc_dump_irqs, &dss_debug_fops); | |
853525d7 | 455 | #endif |
dfc0fd8d | 456 | |
853525d7 | 457 | #if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS) |
dfc0fd8d TV |
458 | debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir, |
459 | &dsi_dump_irqs, &dss_debug_fops); | |
460 | #endif | |
461 | ||
559d6701 TV |
462 | debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir, |
463 | &dss_dump_regs, &dss_debug_fops); | |
464 | debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir, | |
465 | &dispc_dump_regs, &dss_debug_fops); | |
466 | #ifdef CONFIG_OMAP2_DSS_RFBI | |
467 | debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir, | |
468 | &rfbi_dump_regs, &dss_debug_fops); | |
469 | #endif | |
470 | #ifdef CONFIG_OMAP2_DSS_DSI | |
471 | debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir, | |
472 | &dsi_dump_regs, &dss_debug_fops); | |
473 | #endif | |
474 | #ifdef CONFIG_OMAP2_DSS_VENC | |
475 | debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir, | |
476 | &venc_dump_regs, &dss_debug_fops); | |
477 | #endif | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static void dss_uninitialize_debugfs(void) | |
482 | { | |
483 | if (dss_debugfs_dir) | |
484 | debugfs_remove_recursive(dss_debugfs_dir); | |
485 | } | |
368a148e JN |
486 | #else /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ |
487 | static inline int dss_initialize_debugfs(void) | |
488 | { | |
489 | return 0; | |
490 | } | |
491 | static inline void dss_uninitialize_debugfs(void) | |
492 | { | |
493 | } | |
559d6701 TV |
494 | #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ |
495 | ||
496 | /* PLATFORM DEVICE */ | |
497 | static int omap_dss_probe(struct platform_device *pdev) | |
498 | { | |
499 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
500 | int skip_init = 0; | |
501 | int r; | |
502 | int i; | |
503 | ||
504 | core.pdev = pdev; | |
505 | ||
a0acb557 AT |
506 | dss_features_init(); |
507 | ||
559d6701 TV |
508 | dss_init_overlay_managers(pdev); |
509 | dss_init_overlays(pdev); | |
510 | ||
511 | r = dss_get_clocks(); | |
512 | if (r) | |
fce064cb | 513 | goto err_clocks; |
559d6701 TV |
514 | |
515 | dss_clk_enable_all_no_ctx(); | |
516 | ||
517 | core.ctx_id = dss_get_ctx_id(); | |
518 | DSSDBG("initial ctx id %u\n", core.ctx_id); | |
519 | ||
96c401bc | 520 | r = dss_init_platform_driver(); |
559d6701 | 521 | if (r) { |
96c401bc | 522 | DSSERR("Failed to initialize DSS platform driver\n"); |
fce064cb | 523 | goto err_dss; |
559d6701 TV |
524 | } |
525 | ||
559d6701 TV |
526 | r = rfbi_init(); |
527 | if (r) { | |
528 | DSSERR("Failed to initialize rfbi\n"); | |
fce064cb | 529 | goto err_rfbi; |
559d6701 | 530 | } |
559d6701 | 531 | |
8a2cfea8 | 532 | r = dpi_init(pdev); |
559d6701 TV |
533 | if (r) { |
534 | DSSERR("Failed to initialize dpi\n"); | |
fce064cb | 535 | goto err_dpi; |
559d6701 TV |
536 | } |
537 | ||
538 | r = dispc_init(); | |
539 | if (r) { | |
540 | DSSERR("Failed to initialize dispc\n"); | |
fce064cb | 541 | goto err_dispc; |
559d6701 | 542 | } |
368a148e | 543 | |
559d6701 TV |
544 | r = venc_init(pdev); |
545 | if (r) { | |
546 | DSSERR("Failed to initialize venc\n"); | |
fce064cb | 547 | goto err_venc; |
559d6701 | 548 | } |
368a148e | 549 | |
96c401bc SG |
550 | #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT |
551 | /* DISPC_CONTROL */ | |
552 | if (omap_readl(0x48050440) & 1) /* LCD enabled? */ | |
553 | skip_init = 1; | |
554 | #endif | |
559d6701 | 555 | if (cpu_is_omap34xx()) { |
559d6701 TV |
556 | r = sdi_init(skip_init); |
557 | if (r) { | |
558 | DSSERR("Failed to initialize SDI\n"); | |
fce064cb | 559 | goto err_sdi; |
559d6701 | 560 | } |
368a148e | 561 | |
559d6701 TV |
562 | r = dsi_init(pdev); |
563 | if (r) { | |
564 | DSSERR("Failed to initialize DSI\n"); | |
fce064cb | 565 | goto err_dsi; |
559d6701 | 566 | } |
559d6701 TV |
567 | } |
568 | ||
559d6701 TV |
569 | r = dss_initialize_debugfs(); |
570 | if (r) | |
fce064cb | 571 | goto err_debugfs; |
559d6701 TV |
572 | |
573 | for (i = 0; i < pdata->num_devices; ++i) { | |
574 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
575 | ||
576 | r = omap_dss_register_device(dssdev); | |
fce064cb JN |
577 | if (r) { |
578 | DSSERR("device %d %s register failed %d\n", i, | |
579 | dssdev->name ?: "unnamed", r); | |
580 | ||
581 | while (--i >= 0) | |
582 | omap_dss_unregister_device(pdata->devices[i]); | |
583 | ||
584 | goto err_register; | |
585 | } | |
559d6701 TV |
586 | |
587 | if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0) | |
588 | pdata->default_device = dssdev; | |
589 | } | |
590 | ||
591 | dss_clk_disable_all(); | |
592 | ||
593 | return 0; | |
594 | ||
fce064cb JN |
595 | err_register: |
596 | dss_uninitialize_debugfs(); | |
597 | err_debugfs: | |
598 | if (cpu_is_omap34xx()) | |
599 | dsi_exit(); | |
600 | err_dsi: | |
601 | if (cpu_is_omap34xx()) | |
602 | sdi_exit(); | |
603 | err_sdi: | |
604 | venc_exit(); | |
605 | err_venc: | |
606 | dispc_exit(); | |
607 | err_dispc: | |
608 | dpi_exit(); | |
609 | err_dpi: | |
610 | rfbi_exit(); | |
611 | err_rfbi: | |
96c401bc | 612 | dss_uninit_platform_driver(); |
fce064cb JN |
613 | err_dss: |
614 | dss_clk_disable_all_no_ctx(); | |
615 | dss_put_clocks(); | |
616 | err_clocks: | |
617 | ||
559d6701 TV |
618 | return r; |
619 | } | |
620 | ||
621 | static int omap_dss_remove(struct platform_device *pdev) | |
622 | { | |
623 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
624 | int i; | |
559d6701 | 625 | |
559d6701 | 626 | dss_uninitialize_debugfs(); |
559d6701 | 627 | |
559d6701 | 628 | venc_exit(); |
559d6701 TV |
629 | dispc_exit(); |
630 | dpi_exit(); | |
559d6701 | 631 | rfbi_exit(); |
559d6701 | 632 | if (cpu_is_omap34xx()) { |
559d6701 | 633 | dsi_exit(); |
559d6701 | 634 | sdi_exit(); |
559d6701 TV |
635 | } |
636 | ||
96c401bc | 637 | dss_uninit_platform_driver(); |
559d6701 | 638 | |
8ba775ca SS |
639 | /* |
640 | * As part of hwmod changes, DSS is not the only controller of dss | |
641 | * clocks; hwmod framework itself will also enable clocks during hwmod | |
642 | * init for dss, and autoidle is set in h/w for DSS. Hence, there's no | |
643 | * need to disable clocks if their usecounts > 1. | |
644 | */ | |
645 | WARN_ON(core.num_clks_enabled > 0); | |
559d6701 TV |
646 | |
647 | dss_put_clocks(); | |
648 | ||
649 | dss_uninit_overlays(pdev); | |
650 | dss_uninit_overlay_managers(pdev); | |
651 | ||
652 | for (i = 0; i < pdata->num_devices; ++i) | |
653 | omap_dss_unregister_device(pdata->devices[i]); | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | static void omap_dss_shutdown(struct platform_device *pdev) | |
659 | { | |
660 | DSSDBG("shutdown\n"); | |
661 | dss_disable_all_devices(); | |
662 | } | |
663 | ||
664 | static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state) | |
665 | { | |
666 | DSSDBG("suspend %d\n", state.event); | |
667 | ||
668 | return dss_suspend_all_devices(); | |
669 | } | |
670 | ||
671 | static int omap_dss_resume(struct platform_device *pdev) | |
672 | { | |
673 | DSSDBG("resume\n"); | |
674 | ||
675 | return dss_resume_all_devices(); | |
676 | } | |
677 | ||
678 | static struct platform_driver omap_dss_driver = { | |
679 | .probe = omap_dss_probe, | |
680 | .remove = omap_dss_remove, | |
681 | .shutdown = omap_dss_shutdown, | |
682 | .suspend = omap_dss_suspend, | |
683 | .resume = omap_dss_resume, | |
684 | .driver = { | |
685 | .name = "omapdss", | |
686 | .owner = THIS_MODULE, | |
687 | }, | |
688 | }; | |
689 | ||
690 | /* BUS */ | |
691 | static int dss_bus_match(struct device *dev, struct device_driver *driver) | |
692 | { | |
693 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
694 | ||
695 | DSSDBG("bus_match. dev %s/%s, drv %s\n", | |
696 | dev_name(dev), dssdev->driver_name, driver->name); | |
697 | ||
698 | return strcmp(dssdev->driver_name, driver->name) == 0; | |
699 | } | |
700 | ||
701 | static ssize_t device_name_show(struct device *dev, | |
702 | struct device_attribute *attr, char *buf) | |
703 | { | |
704 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
705 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
706 | dssdev->name ? | |
707 | dssdev->name : ""); | |
708 | } | |
709 | ||
710 | static struct device_attribute default_dev_attrs[] = { | |
711 | __ATTR(name, S_IRUGO, device_name_show, NULL), | |
712 | __ATTR_NULL, | |
713 | }; | |
714 | ||
715 | static ssize_t driver_name_show(struct device_driver *drv, char *buf) | |
716 | { | |
717 | struct omap_dss_driver *dssdrv = to_dss_driver(drv); | |
718 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
719 | dssdrv->driver.name ? | |
720 | dssdrv->driver.name : ""); | |
721 | } | |
722 | static struct driver_attribute default_drv_attrs[] = { | |
723 | __ATTR(name, S_IRUGO, driver_name_show, NULL), | |
724 | __ATTR_NULL, | |
725 | }; | |
726 | ||
727 | static struct bus_type dss_bus_type = { | |
728 | .name = "omapdss", | |
729 | .match = dss_bus_match, | |
730 | .dev_attrs = default_dev_attrs, | |
731 | .drv_attrs = default_drv_attrs, | |
732 | }; | |
733 | ||
734 | static void dss_bus_release(struct device *dev) | |
735 | { | |
736 | DSSDBG("bus_release\n"); | |
737 | } | |
738 | ||
739 | static struct device dss_bus = { | |
740 | .release = dss_bus_release, | |
741 | }; | |
742 | ||
743 | struct bus_type *dss_get_bus(void) | |
744 | { | |
745 | return &dss_bus_type; | |
746 | } | |
747 | ||
748 | /* DRIVER */ | |
749 | static int dss_driver_probe(struct device *dev) | |
750 | { | |
751 | int r; | |
752 | struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); | |
753 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
754 | struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; | |
755 | bool force; | |
756 | ||
757 | DSSDBG("driver_probe: dev %s/%s, drv %s\n", | |
758 | dev_name(dev), dssdev->driver_name, | |
759 | dssdrv->driver.name); | |
760 | ||
761 | dss_init_device(core.pdev, dssdev); | |
762 | ||
e020f9af TV |
763 | force = pdata->default_device == dssdev; |
764 | dss_recheck_connections(dssdev, force); | |
559d6701 TV |
765 | |
766 | r = dssdrv->probe(dssdev); | |
767 | ||
768 | if (r) { | |
769 | DSSERR("driver probe failed: %d\n", r); | |
c121b152 | 770 | dss_uninit_device(core.pdev, dssdev); |
559d6701 TV |
771 | return r; |
772 | } | |
773 | ||
774 | DSSDBG("probe done for device %s\n", dev_name(dev)); | |
775 | ||
776 | dssdev->driver = dssdrv; | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
781 | static int dss_driver_remove(struct device *dev) | |
782 | { | |
783 | struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); | |
784 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
785 | ||
786 | DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev), | |
787 | dssdev->driver_name); | |
788 | ||
789 | dssdrv->remove(dssdev); | |
790 | ||
791 | dss_uninit_device(core.pdev, dssdev); | |
792 | ||
793 | dssdev->driver = NULL; | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | int omap_dss_register_driver(struct omap_dss_driver *dssdriver) | |
799 | { | |
800 | dssdriver->driver.bus = &dss_bus_type; | |
801 | dssdriver->driver.probe = dss_driver_probe; | |
802 | dssdriver->driver.remove = dss_driver_remove; | |
96adcece TV |
803 | |
804 | if (dssdriver->get_resolution == NULL) | |
805 | dssdriver->get_resolution = omapdss_default_get_resolution; | |
a2699504 TV |
806 | if (dssdriver->get_recommended_bpp == NULL) |
807 | dssdriver->get_recommended_bpp = | |
808 | omapdss_default_get_recommended_bpp; | |
96adcece | 809 | |
559d6701 TV |
810 | return driver_register(&dssdriver->driver); |
811 | } | |
812 | EXPORT_SYMBOL(omap_dss_register_driver); | |
813 | ||
814 | void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver) | |
815 | { | |
816 | driver_unregister(&dssdriver->driver); | |
817 | } | |
818 | EXPORT_SYMBOL(omap_dss_unregister_driver); | |
819 | ||
820 | /* DEVICE */ | |
821 | static void reset_device(struct device *dev, int check) | |
822 | { | |
823 | u8 *dev_p = (u8 *)dev; | |
824 | u8 *dev_end = dev_p + sizeof(*dev); | |
825 | void *saved_pdata; | |
826 | ||
827 | saved_pdata = dev->platform_data; | |
828 | if (check) { | |
829 | /* | |
830 | * Check if there is any other setting than platform_data | |
831 | * in struct device; warn that these will be reset by our | |
832 | * init. | |
833 | */ | |
834 | dev->platform_data = NULL; | |
835 | while (dev_p < dev_end) { | |
836 | if (*dev_p) { | |
837 | WARN("%s: struct device fields will be " | |
838 | "discarded\n", | |
839 | __func__); | |
840 | break; | |
841 | } | |
842 | dev_p++; | |
843 | } | |
844 | } | |
845 | memset(dev, 0, sizeof(*dev)); | |
846 | dev->platform_data = saved_pdata; | |
847 | } | |
848 | ||
849 | ||
850 | static void omap_dss_dev_release(struct device *dev) | |
851 | { | |
852 | reset_device(dev, 0); | |
853 | } | |
854 | ||
855 | int omap_dss_register_device(struct omap_dss_device *dssdev) | |
856 | { | |
857 | static int dev_num; | |
559d6701 TV |
858 | |
859 | WARN_ON(!dssdev->driver_name); | |
860 | ||
861 | reset_device(&dssdev->dev, 1); | |
862 | dssdev->dev.bus = &dss_bus_type; | |
863 | dssdev->dev.parent = &dss_bus; | |
864 | dssdev->dev.release = omap_dss_dev_release; | |
865 | dev_set_name(&dssdev->dev, "display%d", dev_num++); | |
e020f9af | 866 | return device_register(&dssdev->dev); |
559d6701 TV |
867 | } |
868 | ||
869 | void omap_dss_unregister_device(struct omap_dss_device *dssdev) | |
870 | { | |
871 | device_unregister(&dssdev->dev); | |
559d6701 TV |
872 | } |
873 | ||
874 | /* BUS */ | |
875 | static int omap_dss_bus_register(void) | |
876 | { | |
877 | int r; | |
878 | ||
879 | r = bus_register(&dss_bus_type); | |
880 | if (r) { | |
881 | DSSERR("bus register failed\n"); | |
882 | return r; | |
883 | } | |
884 | ||
885 | dev_set_name(&dss_bus, "omapdss"); | |
886 | r = device_register(&dss_bus); | |
887 | if (r) { | |
888 | DSSERR("bus driver register failed\n"); | |
889 | bus_unregister(&dss_bus_type); | |
890 | return r; | |
891 | } | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | /* INIT */ | |
897 | ||
898 | #ifdef CONFIG_OMAP2_DSS_MODULE | |
899 | static void omap_dss_bus_unregister(void) | |
900 | { | |
901 | device_unregister(&dss_bus); | |
902 | ||
903 | bus_unregister(&dss_bus_type); | |
904 | } | |
905 | ||
906 | static int __init omap_dss_init(void) | |
907 | { | |
908 | int r; | |
909 | ||
910 | r = omap_dss_bus_register(); | |
911 | if (r) | |
912 | return r; | |
913 | ||
914 | r = platform_driver_register(&omap_dss_driver); | |
915 | if (r) { | |
916 | omap_dss_bus_unregister(); | |
917 | return r; | |
918 | } | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
923 | static void __exit omap_dss_exit(void) | |
924 | { | |
8a2cfea8 TV |
925 | if (core.vdds_dsi_reg != NULL) { |
926 | regulator_put(core.vdds_dsi_reg); | |
927 | core.vdds_dsi_reg = NULL; | |
928 | } | |
929 | ||
930 | if (core.vdds_sdi_reg != NULL) { | |
931 | regulator_put(core.vdds_sdi_reg); | |
932 | core.vdds_sdi_reg = NULL; | |
933 | } | |
934 | ||
935 | if (core.vdda_dac_reg != NULL) { | |
936 | regulator_put(core.vdda_dac_reg); | |
937 | core.vdda_dac_reg = NULL; | |
938 | } | |
939 | ||
559d6701 TV |
940 | platform_driver_unregister(&omap_dss_driver); |
941 | ||
942 | omap_dss_bus_unregister(); | |
943 | } | |
944 | ||
945 | module_init(omap_dss_init); | |
946 | module_exit(omap_dss_exit); | |
947 | #else | |
948 | static int __init omap_dss_init(void) | |
949 | { | |
950 | return omap_dss_bus_register(); | |
951 | } | |
952 | ||
953 | static int __init omap_dss_init2(void) | |
954 | { | |
955 | return platform_driver_register(&omap_dss_driver); | |
956 | } | |
957 | ||
958 | core_initcall(omap_dss_init); | |
959 | device_initcall(omap_dss_init2); | |
960 | #endif | |
961 | ||
962 | MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); | |
963 | MODULE_DESCRIPTION("OMAP2/3 Display Subsystem"); | |
964 | MODULE_LICENSE("GPL v2"); | |
965 |